DATASHEET

DATASHEET
High-Performance Notebook PWM Controller With
Audio-Frequency Clamp
ISL6269B
Features
The ISL6269B IC is a Single-phase Synchronous-Buck PWM
controller featuring Intersil's Robust Ripple Regulator R3™
Technology that delivers truly superior dynamic response to
input voltage and output load transients. Integrated MOSFET
drivers and bootstrap diode result in fewer components and
smaller implementation area.
• High performance R3™ Technology
Intersil’s R3™ Technology combines the best features of
fixed-frequency PWM and hysteretic PWM while eliminating
many of their shortcomings. R3™ Technology employs an
innovative modulator that synthesizes an AC ripple voltage
signal VR, analogous to the output inductor ripple current. The
AC signal VR enters a window comparator where the lower
threshold is the error amplifier output VCOMP and the upper
threshold is a programmable voltage reference VW, resulting in
generation of the PWM signal. The voltage reference VW sets
the steady-state PWM frequency. Both edges of the PWM can be
modulated in response to input voltage transients and output
load transients, much faster than conventional fixed-frequency
PWM controllers. Unlike a conventional hysteretic converter, the
ISL6269B has an error amplifier that provides ±1% voltage
regulation at the FB pin.
• Output voltage range: +0.6V to +3.3V
The ISL6269B has a 1.5ms digital soft-start and can be
started into a pre-biased output voltage. A resistor divider is
used to program the output voltage setpoint. The ISL6269B
can be configured to operate in Continuous Conduction Mode
(CCM) or Diode Emulation Mode (DEM), which improves
light-load efficiency. In CCM the controller always operates as a
synchronous rectifier, however when DEM is enabled, the
low-side MOSFET is permitted to stay off, blocking negative
current flow into the low-side MOSFET from the output
inductor.
• Fast transient response
• ±1% regulation accuracy: -10°C to +100°C and
-40° to +100°C
• Wide input voltage range: +5V to +25V
• Wide output load range: 0A to 25A
• Selectable diode emulation mode for increased light load
efficiency
• Programmable PWM frequency: 200kHz to 600kHz
• Pre-biased output start-up capability
• Integrated MOSFET drivers and bootstrap diode
• Internal digital soft-start
• Power-good monitor
• PWM minimum frequency above audible spectrum
• Fault protection
- Undervoltage protection
- Soft crowbar overvoltage protection
- Low-side MOSFET rDS(ON) overcurrent protection
- Over-temperature protection
- Fault identification by PGOOD pull-down resistance
• Pb-free (RoHS compliant)
Applications
• PCI express graphical processing unit
• Auxiliary power rail
• VRM
• Network adapter
November 17, 2014
FN6280.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2006-2007, 2014. All Rights Reserved
Intersil (and design) and R3 Technology are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6269B
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG. DWG. #
ISL6269BCRZ
62 69BCRZ
-10 to +100
16 Ld 4x4 QFN
L16.4x4
ISL6269BIRZ
62 69BIRZ
-40 to +100
16 Ld 4x4 QFN
L16.4x4
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL6269B. For more information on MSL, please see tech brief TB363.
Pin Configuration
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2
PGOOD
PHASE
UG
BOOT
ISL6269B
(16 LD 4x4 QFN)
TOP VIEW
16
15
14
13
12 PVCC
VIN
1
VCC
2
FCCM
3
10 PGND
EN
4
9
11 LG
5
6
7
8
COMP
FB
FSET
VO
GND
ISEN
FN6280.3
November 17, 2014
ISL6269B
Functional Pin Descriptions
GND (Bottom Pad)
Signal common of the IC. Unless otherwise stated, signals are
referenced to the GND pin, not the PGND pin.
VIN (Pin 1)
The VIN pin measures the converter input voltage which is a
required input to the R3™ PWM modulator. Connect across the
drain of the high-side MOSFET to the GND pin.
VCC (Pin 2)
The VCC pin is the input bias voltage for the IC. Connect +5V from
the VCC pin to the GND pin. Decouple with at least 1µF of a MLCC
capacitor from the VCC pin to the GND pin.
FCCM (Pin 3)
The FCCM pin configures the controller to operate in Forced
Continuous Conduction Mode (FCCM) or Diode Emulation Mode
(DEM.) DEM is disabled when the FCCM pin is pulled above the
rising threshold voltage VFCCMTHR, conversely DEM is enabled
when the FCCM pin is pulled below the falling threshold voltage
VFCCMTHF.
EN (Pin 4)
The EN pin is the on/off switch of the IC. The soft-start sequence
begins when the EN pin is pulled above the rising threshold
voltage VENTHR and VVCC is above the power-on reset (POR) rising
threshold voltage VVCC_THR . When the EN pin is pulled below the
falling threshold voltage VENTHF PWM immediately stops.
COMP (Pin 5)
The COMP pin is the output of the control-loop error amplifier.
Compensation components for the control-loop connect across
the COMP and FB pins.
ISEN (Pin 9)
The ISEN pin programs the threshold of the OCP overcurrent fault
protection. Program the desired OCP threshold with a resistor
connected across the ISEN and PHASE pins. The OCP threshold is
programmed to detect the peak current of the output inductor.
The peak current is the sum of the DC and AC components of the
inductor current.
PGND (Pin 10)
The PGND pin conducts the turn-off transient current through the
LG gate driver. The PGND pin must be connected to complete the
pull-down circuit of the LG gate driver. The PGND pin should be
connected to the source of the low-side MOSFET through a low
impedance path, preferably in parallel with the trace connecting
the LG pin to the gate of the low-side MOSFET. The adaptive
shoot-through protection circuit, measures the low-side MOSFET
gate-source voltage from the LG pin to the PGND pin.
LG (Pin 11)
The LG pin is the output of the low-side MOSFET gate driver.
Connect to the gate of the low-side MOSFET.
PVCC (Pin 12)
The PVCC pin is the input voltage bias for the LG low-side
MOSFET gate driver. Connect +5V from the PVCC pin to the PGND
pin. Decouple with at least 1µF of an MLCC capacitor across the
PVCC and PGND pins.
BOOT (Pin 13)
The BOOT pin stores the input voltage for the UG high-side
MOSFET gate driver. Connect an MLCC capacitor across the BOOT
and PHASE pins. The boot capacitor is charged through an
internal boot diode connected from the PVCC pin to the BOOT pin,
each time the PHASE pin drops below PVCC minus the voltage
dropped across the internal boot diode.
UG (Pin 14)
FB (Pin 6)
The FB pin is the inverting input of the control-loop error
amplifier. The converter output voltage regulates to 600mV from
the FB pin to the GND pin. Program the desired output voltage
with a resistor network connected across the VO, FB and GND
pins. Select the resistor values such that FB to GND is 600mV
when the converter output voltage is at the programmed
regulation value.
FSET (Pin 7)
The FSET pin programs the PWM switching frequency. Program
the desired PWM frequency with a resistor and a capacitor
connected across the FSET and GND pins.
VO (Pin 8)
The UG pin is the output of the high-side MOSFET gate driver.
Connect to the gate of the high-side MOSFET.
PHASE (Pin 15)
The PHASE pin detects the voltage polarity of the PHASE node
and is also the current return path for the UG high-side MOSFET
gate driver. Connect the PHASE pin to the node consisting of the
high-side MOSFET source, the low-side MOSFET drain and the
output inductor.
PGOOD (Pin 16)
The PGOOD pin is an open-drain output that indicates when the
converter is able to supply regulated voltage. Connect the PGOOD
pin to +5V through a pull-up resistor.
The VO pin measures the converter output voltage and is used
exclusively as an input to the R3™ PWM modulator. Connect at
the physical location where the best output voltage regulation is
desired.
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FN6280.3
November 17, 2014
VIN
VO
GND
PACKAGE BOTTOM
PWM FREQUENCY
CONTROL
VCC
VREF
FSET
-
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Block Diagram
+
4
+
VW
gmVIN
EN
-
-
+
R
-
PWM
Q
OVP
S
-
VR
+
+
gmVO
VCOMP
+
-
CR
UVP
+
-
+
BOOT
+
EA
FB
DRIVER
-
DIGITAL SOFT-START
PWM CONTROL
POR
COMP
ISEN
OCP
PHASE
SHOOT THROUGH
PROTECTION
PVCC
+
IOC
UG
30Ω
90Ω
60Ω
DRIVER
LG
150°OT
PGOOD
PGND
FN6280.3
November 17, 2014
FCCM
ISL6269B
-
ISL6269B
Typical Application
ISL6269B
VIN
5V TO 25V
PGOOD
VIN
CIN
RPGOOD
QHIGH_SIDE
5V
PVCC
UG
RVCC
VCC
CPVCC
BOOT
CVCC
CBOOT
GND
VOUT
LOUT
0.6V TO 3.3V
PHASE
COUT
RSEN
FCCM
ISEN
QLOW_SIDE
EN
LG
RCOMP
COMP
PGND
CCOMP1
FB
VO
CCOMP2
RFSET
CFSET
RTOP
RBOTTOM
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FSET
5
FN6280.3
November 17, 2014
ISL6269B
Absolute Maximum Ratings
Thermal Information
SEN, VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
VCC, PGOOD to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V to +7.0V
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
GND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
EN, FCCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC +3.3V
VO, FB, COMP, FSET . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC +0.3V
PHASE to GND (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
(<100ns Pulse Width, 10µJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.0V
BOOT to GND, or PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
UG (DC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to PHASE, BOOT +0.3V
(<200ns Pulse Width, 20µJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.0V
LG (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to PGND, PVCC +0.3V
(<100ns Pulse Width, 4µJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V
Thermal Resistance (Typical, Notes 4, 5)
JA (°C/W) JC (°C/W)
QFN Package . . . . . . . . . . . . . . . . . . . . . . . .
48
11.5
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -55C to +150C
Operating Temperature Range
ISL6269BCRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
ISL6269BIRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Recommended Operating Conditions
Ambient Temperature Range
ISL6269BCRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
ISL6269BIRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Supply Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 25V
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications These specifications apply for TA = -40°C to +100°C, unless otherwise stated. All typical specifications
TA = +25°C, VCC = 5V, PVCC = 5V, VIN = 15V
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
6.5
10
µA
VIN
IVIN
VIN Input Bias Current
VIN Shutdown Current
IVIN_SHDN
EN = 5V, VIN = 5V
EN = 5V, VIN = 25V
26
35
µA
EN = GND, VIN = 25V
0.1
1.0
µA
EN = 5V, FCCM = GND, FB = 0.65V
1.7
2.5
mA
EN = GND, VCC = 5V
0.1
1.0
µA
0.1
1.0
µA
4.35
4.45
4.55
V
4.33
4.45
4.55
V
4.10
4.20
4.30
V
4.08
4.20
4.30
V
VCC and PVCC
VCC Input Bias Current
IVCC
VCC Shutdown Current
IVCC_SHDN
PVCC Shutdown Current
IPVCC_SHDN EN = GND, PVCC = 5V
VCC POR THRESHOLD
Rising VCC POR Threshold Voltage
VVCC_THR
V
Falling VCC POR Threshold Voltage
VCC_THF
TA = -10°C to +100°C
TA = -10°C to +100°C
REGULATION
Reference Voltage
VREF
Regulation Accuracy
0.6
FB connected to COMP
V
-1
+1
%
FCCM = 5V
200
600
kHz
FCCM = GND, TA = -10°C to +100°C
19
28
FCCM = GND
18
28
fSW = 300kHz
-12
+12
%
0.60
3.30
V
PWM
Frequency Range
fSW
fAUDIO
Frequency-Set Accuracy
VO Range
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VVO
6
kHz
kHz
FN6280.3
November 17, 2014
ISL6269B
Electrical Specifications These specifications apply for TA = -40°C to +100°C, unless otherwise stated. All typical specifications
TA = +25°C, VCC = 5V, PVCC = 5V, VIN = 15V (Continued)
PARAMETER
SYMBOL
VO Input Leakage
IVO
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO = 0.6V
1.3
µA
VO = 3.30V
7.0
µA
ERROR AMPLIFIER
FB Input Bias Current
IFB
COMP Source Current
ICOMP_SRC
FB = 0.40V, COMP = 3.20V
2.5
mA
COMP Sink Current
ICOMP_SNK
FB = 0.80V, COMP = 0.30V
0.3
mA
COMP High Clamp Voltage
VCOMP_HC
FB = 0.40V, Sink 5µA
3.10
3.40
3.65
V
COMP Low Clamp Voltage
VCOMP_LC
FB = 0.80V, Source 50µA
0.09
0.15
0.21
V
75
95
125
Ω
FB = 0.6V
-0.5
+0.5
µA
POWER-GOOD
PGOOD Pull-down Impedance
RPG_SS
RPG_UV
RPG_OV
RPG_OC
PGOOD Leakage Current
IPGOOD
PGOOD = 5mA Sink, TA = -10°C to +100°C
PGOOD = 5mA Sink
67
95
125
Ω
PGOOD = 5mA Sink, TA = -10°C to +100°C
75
95
125
Ω
PGOOD = 5mA Sink
67
95
125
Ω
PGOOD = 5mA Sink, TA = -10°C to +100°C
50
63
85
Ω
PGOOD = 5mA Sink
45
63
85
Ω
PGOOD = 5mA Sink, TA = -10°C to +100°C
25
32
45
Ω
PGOOD = 5mA Sink
22
32
45
Ω
0.1
1.0
PGOOD = 5V
PGOOD Maximum Sink Current (Note 6)
PGOOD Soft-start Delay
5.0
tSS
µA
mA
EN High to PGOOD High, TA = -10°C to +100°C
2.20
2.75
3.30
ms
EN High to PGOOD High
2.20
2.75
3.50
ms
1.0
1.5
Ω
1.5
Ω
GATE DRIVER
UG Pull-Up Resistance
RUGPU
200mA Source Current
UG Source Current (Note 6)
IUGSRC
UG - PHASE = 2.5V
2.0
UG Sink Resistance
RUGPD
250mA Sink Current
1.0
UG Sink Current (Note 6)
IUGSNK
UG - PHASE = 2.5V
2.0
LG Pull-Up Resistance
RLGPU
250mA Source Current
1.0
A
A
1.5
Ω
0.9
Ω
LG Source Current (Note 6)
ILGSRC
LG - PGND = 2.5V
2.0
LG Sink Resistance
RLGPD
250mA Sink Current
0.5
LG Sink Current (Note 6)
ILGSNK
LG - PGND = 2.5V
4.0
A
UG to LG Deadtime
tUGFLGR
UG falling to LG rising, no load
21
ns
LG to UG Deadtime
tLGFUGR
LG falling to UG rising, no load
14
ns
A
BOOTSTRAP DIODE
Forward Voltage
VF
PVCC = 5V, IF = 2mA
0.58
V
Reverse Leakage
IR
VR = 25V
0.2
µA
CONTROL INPUTS
EN High Threshold
VENTHR
EN Low Threshold
V
VENTHF
FCCM High Threshold
VFCCMTHR
FCCM Low Threshold
VFCCMTHF
EN Leakage
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2.0
7
1.0
2.0
V
V
1.0
V
IENL
EN = 0V
0.1
1.0
µA
IENH
EN = 5V
0.1
1.0
µA
FN6280.3
November 17, 2014
ISL6269B
Electrical Specifications These specifications apply for TA = -40°C to +100°C, unless otherwise stated. All typical specifications
TA = +25°C, VCC = 5V, PVCC = 5V, VIN = 15V (Continued)
PARAMETER
SYMBOL
FCCM Leakage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.0
µA
IFCCML
FCCM = 0V
0.1
IFCCMH
FCCM = 5V
2.0
µA
PROTECTION
ISEN OCP Threshold
IOC
ISEN Short-Circuit Threshold
ISC
ISEN sourcing, TA = -10°C to +100°C
19
26
33
µA
ISEN sourcing
17
26
33
µA
ISEN sourcing
50
µA
UVP Threshold
VUV
81
84
87
%
OVP Rising Threshold
VOVR
113
116
119
%
OVP Falling Threshold
VOVF
100
103
106
%
OTP Rising Threshold (Note 6)
TOTR
150
°C
TOTHYS
25
°C
OTP Hysteresis (Note 6)
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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FN6280.3
November 17, 2014
ISL6269B
Theory of Operation
EN, Soft-Start and PGOOD
Modulator
The ISL6269B is a hybrid of fixed frequency PWM control and
variable frequency hysteretic control. Intersil’s R3™ Technology can
simultaneously affect the PWM switching frequency and PWM duty
cycle in response to input voltage and output load transients. The
term “Ripple” in the name “Robust Ripple Regulator” refers to the
converter output inductor ripple current, not the converter output
ripple voltage. The R3™ Modulator synthesizes an AC signal VR,
which is an ideal representation of the output inductor ripple
current. The duty-cycle of VR is the result of charge and discharge
current through a ripple capacitor CR. The current through CR is
provided by a transconductance amplifier gm that measures the VIN
and VO pin voltages. The positive slope of VR can be written as:
V RPOS =  g m    V IN – V OUT 
The ISL6269B uses a digital soft-start circuit to ramp the output
voltage of the converter to the programmed regulation setpoint
at a predictable slew rate. The slew rate of the soft-start
sequence has been selected to limit the in-rush current through
the output capacitors as they charge to the desired regulation
voltage. When the EN pin is pulled above the rising EN threshold
voltage VENTHR the PGOOD soft-start delay tSS begins and the
output voltage begins to rise. The output voltage enters regulation
in approximately 1.5ms and the PGOOD pin goes to high
impedance once tSS has elapsed.
1.5ms
VOUT
(EQ. 1)
VCC and PVCC
(EQ. 2)
EN
The negative slope of VR can be written as:
V RNEG = g m  V OUT
Where gm is the gain of the transconductance amplifier.
A window voltage VW is referenced with respect to the error
amplifier output voltage VCOMP, creating an envelope into which
the ripple voltage VR is compared. The amplitude of VW is set by
a resistor connected across the FSET and GND pins. The VR,
VCOMP and VW signals feed into a window comparator in which
VCOMP is the lower threshold voltage and VW is the higher
threshold voltage. Figure 1 shows PWM pulses being generated
as VR traverses the VW and VCOMP thresholds. The PWM
switching frequency is proportional to the slew rates of the
positive and negative slopes of VR; the PWM switching frequency
is inversely proportional to the voltage between VW and VCOMP.
Ripple Capacitor Voltage CR
Window Voltage VW
PGOOD
2.75ms
FIGURE 2. SOFT-START SEQUENCE
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The PGOOD pin is an undefined
impedance if VVCC has not reached the rising POR threshold
VVCC_THR, or if VVCC is below the falling POR threshold VVCC_THF.
The ISL6269B features a unique fault-identification capability
that can drastically reduce troubleshooting time and effort. The
pull-down resistance of the PGOOD pin corresponds to the fault
status of the controller. During soft-start or if an undervoltage
fault occurs, the PGOOD pull-down resistance is 95Ω, or 30Ω for
an overcurrent fault, or 60Ω for an overvoltage fault.
TABLE 1. PGOOD PULL-DOWN RESISTANCE
Error Amplifier Voltage VCOMP
CONDITION
PGOOD RESISTANCE
VCC Below POR
Undefined
Soft-start or Undervoltage
95Ω
Overvoltage
60Ω
Overcurrent
30Ω
PWM
FIGURE 1. MODULATOR WAVEFORMS DURING LOAD TRANSIENT
Power-On Reset
The ISL6269B is disabled until the voltage VVCC has increased
above the rising power-on reset (POR) VVCC_THR threshold voltage.
The controller will become once again disabled when the voltage
VVCC decreases below the falling POR VVCC_THF threshold voltage.
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FN6280.3
November 17, 2014
ISL6269B
MOSFET Gate-Drive Outputs LG and UG
The ISL6269B has internal gate-drivers for the high-side and
low-side N-Channel MOSFETs. The LG gate-driver is optimized for
low duty-cycle applications where the low-side MOSFET
conduction losses are dominant, requiring a low rDS(ON) MOSFET.
The LG pull-down resistance is small in order to clamp the gate of
the MOSFET below the VGS(th) at turnoff. The current transient
through the gate at turnoff can be considerable because the
switching charge of a low rDS(ON) MOSFET can be large. Adaptive
shoot-through protection prevents a gate-driver output from
turning on until the opposite gate-driver output has fallen below
approximately 1V. The dead-time shown in Figure 3 is extended
by the additional period that the falling gate voltage stays above
the 1V threshold. The high-side gate-driver output voltage is
measured across the UG and PHASE pins while the low-side
gate-driver output voltage is measured across the LG and PGND
pins. The power for the LG gate-driver is sourced directly from the
PVCC pin. The power for the UG gate-driver is sourced from a
“boot” capacitor connected across the BOOT and PHASE pins.
The boot capacitor is charged from a 5V bias supply through a
“boot diode” each time the low-side MOSFET turns on, pulling the
PHASE pin low. The ISL6269B has an integrated boot diode
connected from the PVCC pin to the BOOT pin.
MOSFET conducts negative inductor current, the phase voltage
will be positive with respect to the GND and PGND pins. Negative
inductor current occurs when the output load current is less than
½ the inductor ripple current. Sinking negative inductor current
through the low-side MOSFET lowers efficiency through
unnecessary conduction losses. Efficiency can be further
improved with a reduction of unnecessary switching losses by
reducing the PWM frequency. It is characteristic of the R3™
architecture for the PWM frequency to decrease while in diode
emulation. The extent of the frequency reduction is proportional
to the reduction of load current. Upon entering DEM, the PWM
frequency makes an initial step-reduction because of a 33%
step-increase of the window voltage V W. The ISL6269B features
an audio filter that clamps the minimum PWM frequency to a
level beyond human hearing when the output load current
becomes low enough.
With FCCM pulled low, the converter will automatically enter DEM
after the PHASE pin has detected positive voltage, while the LG
gate-driver pin is high for eight consecutive PWM pulses. The
converter will return to CCM on the following cycle after the
PHASE pin detects negative voltage, indicating that the body
diode of the low-side MOSFET is conducting positive inductor
current.
Overcurrent and Short-Circuit Protection
tLGFUGR
tUGFLGR
50%
The SCP setpoint is internally set to twice the OCP setpoint. When
an OCP or SCP fault is detected, the PGOOD pin will pull down to
30Ω and latch off the converter. The fault will remain latched
until the EN pin has been pulled below the falling EN threshold
voltage VENTHF or if VVCC has decayed below the falling POR
threshold voltage VVCC_THF.
UG
LG
50%
FIGURE 3. LG AND UG DEAD-TIME
Diode Emulation
The ISL6269B normally operates in Continuous Conduction
Mode (CCM), minimizing conduction losses by forcing the lowside MOSFET to operate as a synchronous rectifier. An
improvement in light-load efficiency is achieved by allowing the
converter to operate in Diode Emulation Mode (DEM), where the
low-side MOSFET behaves as a smart-diode, forcing the device to
block negative inductor current flow. The ISL6269B can be
configured to operate in DEM by setting the FCCM pin low.
Setting the FCCM pin high will disable DEM.
Positive-going inductor current flows from either the source of
the high-side MOSFET, or the drain of the low-side MOSFET.
Negative-going inductor current usually flows into the drain of the
low-side MOSFET. When the low-side MOSFET conducts positive
inductor current, the phase voltage will be negative with respect
to the GND and PGND pins. Conversely, when the low-side
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The overcurrent protection (OCP) and short circuit protection
(SCP) setpoint is programmed with resistor RSEN that is
connected across the ISEN and PHASE pins. The PHASE pin is
connected to the drain terminal of the low-side MOSFET.
10
The OCP circuit does not directly detect the DC load current
leaving the converter. The OCP circuit detects the peak of
positive-flowing output inductor current. The low-side MOSFET
drain current ID is assumed to be equal to the positive output
inductor current when the high-side MOSFET is off. The inductor
current develops a negative voltage across the rDS(ON) of the
low-side MOSFET that is measured shortly after the LG gate
driver output goes high. The ISEN pin sources the OCP sense
current ISEN, through the OCP programming resistor RSEN,
forcing the ISEN pin to zero volts with respect to the GND pin. The
negative voltage across the PHASE and GND pins is nulled by the
voltage dropped across RSEN as ISEN conducts through it. An OCP
fault occurs if ISEN rises above the OCP threshold current IOC
while attempting to null the negative voltage across the PHASE
and GND pins. The ISEN must exceed IOC on all the PWM pulses
that occur within 20µs. If ISEN falls below IOC on a PWM pulse
before 20µs has elapsed, the timer will be reset. An SCP fault will
occur within 10µs when ISEN exceeds twice IOC. The relationship
between ID and ISEN is written as:
I SEN  R SEN = I D  r DS  ON 
(EQ. 3)
FN6280.3
November 17, 2014
ISL6269B
The value of RSEN is then written as:
Programming the Output Voltage
I P-P
 I + ----------  OC SP  r DS  ON 
 FL
2 
R SEN = ------------------------------------------------------------------------------I OC
When the converter is in regulation there will be 600mV from the
FB pin to the GND pin. Connect a two-resistor voltage divider
across the VO pin and the GND pin with the output node
connected to the FB pin. Scale the voltage-divider network such
that the FB pin is 600mV with respect to the GND pin when the
converter is regulating at the desired output voltage. The output
voltage can be programmed from 600mV to 3.3V.
(EQ. 4)
Where:
- RSEN (Ω) is the resistor used to program the overcurrent
setpoint
- ISEN is the current sense current that is sourced from the
ISEN pin
- IOC is the ISEN threshold current sourced from the ISEN pin
that will activate the OCP circuit
- IFL is the maximum continuous DC load current
- IP-P is the inductor peak-to-peak ripple current
- OCSP is the desired overcurrent setpoint expressed as a
multiplier relative to IFL
Overvoltage Protection
When an OVP fault is detected, the PGOOD pin will pull down to
60Ωand latch-off the converter. The OVP fault will remain
latched until VVCC has decayed below the falling POR threshold
voltage VVCC_THF.
The OVP fault detection circuit triggers after the voltage across
the FB and GND pins has increased above the rising overvoltage
threshold VOVR. Although the converter has latched-off in
response to an OVP fault, the LG gate-driver output will retain the
ability to toggle the low-side MOSFET on and off, in response to
the output voltage transversing the VOVR and VOVF thresholds.
Undervoltage Protection
When a UVP fault is detected, the PGOOD pin will pull down to
95Ωand latch-off the converter. The fault will remain latched
until the EN pin has been pulled below the falling EN threshold
voltage VENTHF or if VVCC has decayed below the falling POR
threshold voltage VVCC_THF. The UVP fault detection circuit
triggers after the voltage across the FB and GND pins has fallen
below the undervoltage threshold VUV .
Over-Temperature
When the temperature of the ISL6269B increases above the
rising threshold temperature TOTR, the IC will enter an OTP state
that suspends the PWM, forcing the LG and UG gate-driver
outputs low. The status of the PGOOD pin does not change nor
does the converter latch-off. The PWM remains suspended until
the IC temperature falls below the hysteresis temperature
TOTHYS at which time normal PWM operation resumes. The OTP
state can be reset if the EN pin is pulled below the falling EN
threshold voltage VENTHF or if VVCC decays below the falling POR
threshold voltage VVCC_THF. All other protection circuits function
normally during OTP. It is likely that the IC will detect an UVP fault
because in the absence of PWM, the output voltage immediately
decays below the undervoltage threshold VUV; the PGOOD pin will
pull down to 95Ω and latch-off the converter. The UVP fault will
remain latched until the EN pin has been pulled below the falling
EN threshold voltage VENTHF or if VVCC has decayed below the
falling POR threshold voltage VVCC_THF.
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11
Programming the output voltage is written as:
R BOTTOM
V REF = V OUT  -------------------------------------------------R TOP + R BOTTOM
(EQ. 5)
Where:
- VOUT is the desired output voltage of the converter
- VREF is the voltage that the converter regulates to between
the FB pin and the GND pin
- RTOP is the voltage programming resistor that connects
from the FB pin to the VO pin. In addition to setting the
output voltage, this resistor is part of the loop compensation
network
- RBOTTOM is the voltage programming resistor that connects
from the FB pin to the GND pin
Beginning with RTOP between 1kΩ to 5kΩ calculating RBOTTOM
is written as:
V REF  R
TOP
R BOTTOM = ------------------------------------V OUT – V REF
(EQ. 6)
Programming the PWM Switching Frequency
The ISL6269B does not use a clock signal to produce PWM. The
PWM switching frequency fSW is programmed by the resistor
RFSET that is connected from the FSET pin to the GND pin. The
approximate PWM switching frequency is written as:
1
f SW = -------------------------k  R FSET
(EQ. 7)
Estimating the value of RFSET is written as:
1
R FSET = ----------------k  f SW
(EQ. 8)
Where:
- fSW is the PWM switching frequency
- RFSET is the fSW programming resistor
- k = 75 x 10-12
It is recommended that whenever the control loop compensation
network is modified, fSW should be checked for the correct
frequency and if necessary, adjust RFSET .
Compensation Design
The LC output filter has a double pole at its resonant frequency that
causes the phase to abruptly roll downward. The R3™ Modulator
used in the ISL6269B, makes the LC output filter resemble a first
order system in which the closed loop stability can be achieved with
a Type II compensation network.
FN6280.3
November 17, 2014
ISL6269B
R2
C2
General Application Design
Guide
C1
This design guide is intended to provide a high-level explanation of
the steps necessary to create a single-phase power converter. It is
assumed that the reader is familiar with many of the basic skills
and techniques referenced. In addition to this guide, Intersil
provides complete reference designs that include schematics, bills
of materials and example board layouts.
R1
COMP
FB
EA
Selecting the LC Output Filter
+
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as:
REF
V OUT
D = ---------------V IN
FSET
RFSET
CFSET
R3™ MODULATOR
The output inductor peak-to-peak ripple current is written as:
V OUT   1 – D 
I p-p = -------------------------------------f SW  L OUT
VOUT
VIN
P COPPER = I LOAD
UG
PHASE
DCR
GATE DRIVERS
QLOW_SIDE
COUT
LG
CESR
GND
2

DCR
(EQ. 11)
Where ILOAD is the converter output DC current.
QHIGH_SIDE
LOUT
(EQ. 10)
A typical step-down DC/DC converter will have an IP-P of 20% to
40% of the maximum DC output load current. The value of IP-P is
selected based upon several criteria such as MOSFET switching
loss, inductor core loss and the resistive loss of the inductor
winding. The DC copper loss of the inductor can be estimated by:
VO
VIN
(EQ. 9)
ISL6269B
The copper loss can be significant so attention has to be given to
the DCR selection. Another factor to consider when choosing the
inductor is its saturation characteristics at elevated temperature.
A saturated inductor could cause destruction of circuit
components, as well as nuisance OCP faults.
A DC/DC buck regulator must have output capacitance COUT into
which ripple current IP-P can flow. Current IP-P develops a
corresponding ripple voltage VP-P across COUT, which is the sum
of the voltage drop across the capacitor ESR and of the voltage
change stemming from charge moved in and out of the
capacitor. These two voltages are written as:
V ESR = I P-P  E SR
(EQ. 12)
and
FIGURE 4. COMPENSATION REFERENCE CIRCUIT
Your local Intersil representative can provide a PC-based tool that
can be used to calculate compensation network component
values and help simulate the loop frequency response. The
compensation network consists of the internal error amplifier of the
ISL6269B and the external components R1, R2, C1 and C2 as well
as the frequency setting components RFSET and CFSET, are
identified in the schematic Figure 4.
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12
I P-P
V C = ------------------------------------8  C OUT  f
(EQ. 13)
SW
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled to
reduce the total ESR until the required VP-P is achieved. The
inductance of the capacitor can cause a brief voltage dip if the
load transient has an extremely high slew rate. Low inductance
capacitors constructed with reverse package geometry are
available. A capacitor dissipates heat as a function of RMS current
and frequency. Be sure that IP-P is shared by a sufficient quantity
of paralleled capacitors so that they operate below the maximum
rated RMS current at fSW. Take into account that the rated value of
a capacitor can fade as much as 50% as the DC voltage across it
increases.
FN6280.3
November 17, 2014
ISL6269B
Selection of the Input Capacitor
MOSFET Selection and Considerations
The important parameters for the bulk input capacitance are the
voltage rating and the RMS current rating. For reliable operation,
select bulk capacitors with voltage and current ratings above the
maximum input voltage and capable of supplying the RMS
current required by the switching circuit. Their voltage rating
should be at least 1.25x greater than the maximum input
voltage, while a voltage rating of 1.5x is a preferred rating.
Figure 5 is a graph of the input RMS ripple current, normalized
relative to output load current, as a function of duty cycle that is
adjusted for converter efficiency. The ripple current calculation is
written as shown in Equation 14:
Typically, a MOSFET cannot tolerate even brief excursions beyond
their maximum drain-to-source voltage rating. The MOSFETs used
in the power stage of the converter should have a maximum VDS
rating that exceeds the sum of the upper voltage tolerance of the
input power source and the voltage spike that occurs when the
MOSFET switches off.
2
2 D
2
 I MAX   D – D   +  x  I MAX  ------ 

12 
I IN_RMS = ----------------------------------------------------------------------------------------------------I MAX
(EQ. 14)
Where:
- IMAX is the maximum continuous ILOAD of the converter
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a percentage of
IMAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account the
efficiency of the converter which is written as shown in
Equation 15:
V OUT
D = -------------------------V IN  EFF
(EQ. 15)
NORMALIZED INPUT RMS RIPPLE CURRENT
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain of
the high-side MOSFET and the source of the low-side MOSFET.
0.60
0.50
x=0
0.40
x = 0.50
0.35
0.30
0.25
0.20
0.15
0.1
0.2
0.3
0.4
0.5
0.6
0.7
For the high-side MOSFET, (HS), its conduction loss is written as:
P CON_HS = I LOAD
2

(EQ. 17)
r DS  ON _HS  D
For the high-side MOSFET, its switching loss is written as:
V IN  I PEAK  t OFF  f
V IN  I VALLEY  t ON  f
SW
SW
P SW_HS = ----------------------------------------------------------------- + ------------------------------------------------------------2
2
(EQ. 18)
The selection of the bootstrap capacitor is written as:
0.05
0
(EQ. 16)
Selecting The Bootstrap Capacitor
x = 0.25
0.10
0
2
P CON_LS  I LOAD  r DS  ON _LS   1 – D 
- IVALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- IPEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- tON is the time required to drive the device into saturation
- tOFF is the time required to drive the device into cut-off
x = 0.75
0.45
For the low-side MOSFET, (LS), the power loss can be assumed to
be conductive only and is written as:
Where:
x=1
0.55
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low switch charge so that the
device spends the least amount of time dissipating power in the
linear region. Unlike the low-side MOSFET, which has the drain to
source voltage clamped by its body diode during turn off, the
high-side MOSFET turns off with VIN - VOUT - VLacross it. The
preferred low-side MOSFET emphasizes low rDS(ON) when fully
saturated to minimize conduction loss.
0.8
0.9
DUTY CYCLE
FIGURE 5. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
1.0
Qg
C BOOT = -----------------------V BOOT
(EQ. 19)
Where:
- Qg is the total gate charge required to turn on the high-side
MOSFET
- VBOOT, is the maximum allowed voltage decay across the
boot capacitor each time the high-side MOSFET is switched
on
As an example, suppose the high-side MOSFET has a total gate
charge Qg, of 25nC at VGS = 5V and a VBOOT of 200mV. The
calculated bootstrap capacitance is 0.125µF. For a comfortable
margin select a capacitor that is double the calculated
capacitance, in this example 0.22µF will suffice. Use an X7R or
X5R ceramic capacitor.
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13
FN6280.3
November 17, 2014
ISL6269B
Layout Considerations
As a general rule, power should be on the bottom layer of the
PCB and weak analog or logic signals are on the top layer of the
PCB. The ground-plane layer should be adjacent to the top layer
to provide shielding. The ground plane layer should have an
island located under the IC, the compensation components and
the FSET components. The island should be connected to the rest
of the ground plane layer at one point.
VIAS TO
GROUND
PLANE
GND
VOUT
INDUCTOR
HIGH-SIDE
MOSFETS
PHASE
NODE
VIN
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
FIGURE 6. TYPICAL POWER COMPONENT PLACEMENT
Signal Ground and Power Ground
The bottom of the ISL6269B QFN package is the signal ground
(GND) terminal for analog and logic signals of the IC. Connect the
GND pad of the ISL6269B to the island of ground plane under the
top layer using several vias, for a robust thermal and electrical
conduction path. Connect the input capacitors, the output
capacitors and the source of the lower MOSFETs to the power
ground plane.
PGND (Pin 10)
This is the return path for the pull-down of the LG low-side
MOSFET gate driver. Ideally, PGND should be connected to the
source of the low-side MOSFET with a low resistance, low
inductance path.
VIN (PIN 1)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low inductance
path.
VCC (PIN 2)
For best performance, place the decoupling capacitor very close
to the VCC and GND pins.
FCCM (PIN 3), EN (PIN 4), PGOOD (PIN 16)
These are logic inputs that are referenced to the GND pin. Treat
as a typical logic signal.
COMP (PIN 5), FB (PIN 6) AND VO (PIN 8)
For best results, use an isolated sense line from the output load
to the VO pin. The input impedance of the FB pin is high, so place
the voltage programming and loop compensation components
close to the VO, FB and GND pins keeping the high impedance
trace short.
FSET (PIN 7)
This pin requires a quiet environment. The resistor RFSET and
capacitor CFSET should be placed directly adjacent to this pin.
Keep fast moving nodes away from this pin.
ISEN (PIN 9)
Route the connection to the ISEN pin away from the traces and
components connected to the FB pin, COMP pin and FSET pin.
LG (PIN 11)
The signal going through this trace is both high dv/dt and high
di/dt with high peak charging and discharging current. Route this
trace in parallel with the trace from the PGND pin. These two
traces should be short, wide and away from other traces. There
should be no other weak signal traces in proximity with these
traces on any layer.
BOOT (PIN 13), UG (PIN 14), PHASE (PIN 15)
The signals going through these traces are both high dv/dt and
high di/dt, with high peak charging and discharging current.
Route the UG and PHASE pins in parallel with short and wide
traces. There should be no other weak signal traces in proximity
with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the phase
node should be kept very low to minimize ringing. It is best to
limit the size of the PHASE node copper in strict accordance with
the current and thermal management of the application. An
MLCC should be connected directly across the drain of the upper
MOSFET and the source of the lower MOSFET to suppress the
turn-off voltage spike.
PVCC (PIN 12)
For best performance, place the decoupling capacitor very close
to the PVCC and PGND pins, preferably on the same side of the
PCB as the ISL6269B IC.
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FN6280.3
November 17, 2014
ISL6269B
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
November 17, 2014
FN6280.3
CHANGE
-Updated Template.
-Updated intersil trademark statement at the bottom of page one.
-Ordering information table on page 2, updated Note 1 from "*Add"-T" suffix for tape and reel" to “Add “-T*”
suffix for tape and reel. Please refer to TB347 for details on reel specifications."
-Ordering information table on page 2: Added MSL Note 3.
-On page 6, updated Caution statement per legal's new verbiage.
-On page 8, updated Note 6 from "Guaranteed by characterization." to "Compliance to limits is assured by
characterization and design."
-Added revision history and about Intersil verbiage.
-Updated L16.4x4 to new POD format by removing table listing dimensions and moving dimensions onto
drawing.
-Added Typical Recommended Land Pattern.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN6280.3
November 17, 2014
ISL6269B
Package Outline Drawing
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 6, 02/08
4X 1.95
4.00
12X 0.65
A
B
13
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
16
1
4.00
12
2 . 10 ± 0 . 15
9
4
0.15
(4X)
5
8
TOP VIEW
0.10 M C A B
+0.15
16X 0 . 60
-0.10
4 0.28 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
1.00 MAX
C
BASE PLANE
( 3 . 6 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
(
2 . 10 )
( 12X 0 . 65 )
( 16X 0 . 28 )
C
0 . 2 REF
5
( 16 X 0 . 8 )
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
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FN6280.3
November 17, 2014
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