DATASHEET

ISL6312A
Data Sheet
Four-Phase Buck PWM Controller with
Integrated MOSFET Drivers for Intel VR10,
VR11, and AMD Applications
The ISL6312A four-phase PWM control IC provides a
precision voltage regulation system for advanced
microprocessors. The integration of power MOSFET drivers
into the controller IC marks a departure from the separate
PWM controller and driver configuration of previous
multiphase product families. By reducing the number of
external parts, this integration is optimized for a cost and
space saving power management solution.
One outstanding feature of this controller IC is its
multi-processor compatibility, allowing it to work with both
Intel and AMD microprocessors. Included are programmable
VID codes for Intel VR10, VR11, as-well-as AMD DAC
tables. A unity gain, differential amplifier is provided for
remote voltage sensing, compensating for any potential
difference between remote and local grounds. The output
voltage can also be positively or negatively offset through
the use of a single external resistor.
The ISL6312A also includes advanced control loop features
for optimal transient response to load apply and removal.
One of these features is highly accurate, fully differential,
continuous DCR current sensing for load-line programming
and channel current balance. Active pulse positioning (APP)
modulation is another unique feature, allowing for quicker
initial response to high di/dt load transients.
January 22, 2015
FN9290.6
Features
• Integrated multiphase power conversion
- 2-phase or 3-phase operation with internal drivers
- 4-phase operation with external PWM driver signal
• Precision core voltage regulation
- Differential remote voltage sensing
- 0.5% system accuracy over-temperature
- Adjustable reference-voltage offset
• Optimal transient response
- Active pulse positioning (APP) modulation
- Adaptive phase alignment (APA)
• Fully differential, continuous DCR current sensing
- Accurate load-line programming
- Precision channel current balancing
• User selectable adaptive deadtime scheme
- PHASE detect or LGATE detect for application flexibility
• Variable gate drive bias: 5V to 12V
• Multi-processor compatible
- Intel VR10 and VR11 modes of operation
- AMD mode of operation
• Microprocessor voltage identification inputs
- 8-bit DAC
- Selectable between intel’s extended VR10, VR11, AMD
5-bit, and AMD 6-bit DAC tables
- Dynamic VID technology
This controller also allows the user the flexibility to choose
between PHASE detect or LGATE detect adaptive deadtime
schemes. This ability allows the ISL6312A to be used in a
multitude of applications where either scheme is required.
• Overcurrent protection
Protection features of this controller IC include a set of
sophisticated overvoltage, undervoltage, and overcurrent
protection. Furthermore, the ISL6312A includes protection
against an open circuit on the remote sensing inputs.
Combined, these features provide advanced protection for
the microprocessor and power system.
• Selectable operation frequency up to 1.5MHz per phase
1
• Load current indicator
• Multi-tiered overvoltage protection
• Digital soft-start
• Pb-free (RoHS compliant)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2006, 2007, 2010, 2011, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6312A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP.
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6312ACRZ
ISL6312 ACRZ
0 to +70
48 Ld 7x7 QFN
L48.7x7
ISL6312AIRZ
ISL6312 AIRZ
-40 to +85
48 Ld 7x7 QFN
L48.7x7
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL6312A. For more information on MSL, please see tech brief
TB363.
2
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January 22, 2015
ISL6312A
Pinout
VID5
VID6
VID7
FS
ISEN3+
ISEN3-
PVCC3
LGATE3
BOOT3
UGATE3
PHASE3
PGOOD
ISL6312A
(48 LD QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
VID4
1
36
EN
VID3
2
35
ISEN1+
VID2
3
34
ISEN1-
VID1
4
33
PHASE1
32
UGATE1
31
BOOT1
30
LGATE1
VID0
5
VRSEL
6
DRSEL
7
OVPSEL
8
29
PVCC1_2
49
GND
OFS
12
25
PHASE2
COMP
13
14
15
16
17
18
19
20
21
22
23
24
PWM4
UGATE2
ISEN4-
26
EN_PH4
11
ISEN4+
REF
ISEN2-
BOOT2
VSEN
27
ISEN2+
10
RGND
LGATE2
VDIFF
28
FB
9
IOUT
SS
VCC
ISL6312A Integrated Driver Block Diagram
PVCC
DRSEL
BOOT
UGATE
20k
PWM
GATE
CONTROL
LOGIC
SOFT-START
SHOOTPHASE
THROUGH
PROTECTION
10k
AND
FAULT LOGIC
LGATE
3
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ISL6312A
Block Diagram
PGOOD
EN
SS
OPEN SENSE
LINE PREVENTION
0.85V
VSEN
x1
RGND
VCC
POWER-ON
RESET
VDIFF
PVCC1_2
SOFT-START
AND
UNDERVOLTAGE
DETECTION
LOGIC
FAULT LOGIC
BOOT1
MOSFET
DRIVER
OVERVOLTAGE
DETECTION
LOGIC
UGATE1
PHASE1
0.2V
LGATE1
OVPSEL
LOAD APPLY
TRANSIENT
ENHANCEMENT
DRSEL
CLOCK AND
MODULATOR
WAVEFORM
GENERATOR
VRSEL
FS
MODE / DAC
SELECT
BOOT2
MOSFET
DRIVER
PWM1

VID7
VID6
OC
VID5
VID4
VID3
PHASE2
LGATE2
PWM2
DYNAMIC
VID
D/A
UGATE2

VID2
I_TRIP
PWM3
VID1

VID0
PH4 POR/
DETECT
PVCC3
PWM4
REF
E/A
FB
EN_PH4
CHANNEL
DETECT

BOOT3
COMP
OFS
IOUT
OFFSET
I_AVG
x1
CHANNEL
CURRENT
BALANCE
I_AVG
MOSFET
DRIVER
1
N
LGATE3
PWM4
SIGNAL
LOGIC
VOCP
CH1
CURRENT
SENSE
CH2
CURRENT
SENSE
CH3
CURRENT
SENSE
PWM4
CH4
CURRENT
SENSE
ISEN1- ISEN1+ ISEN2- ISEN2+ ISEN3- ISEN3+ ISEN4- ISEN4+
4
PHASE3

OCP
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UGATE3
GND
FN9290.6
January 22, 2015
ISL6312A
Typical Application - ISL6312A (4-Phase)
+12V
VDIFF
FB
COMP
VSEN
BOOT1
RGND
UGATE1
+5V
PHASE1
VCC
LGATE1
ISEN1ISEN1+
OFS
FS
+12V
REF
PVCC1_2
BOOT2
SS
UGATE2
PHASE2
OVPSEL
LGATE2
ISL6312A
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
LOAD
ISEN2ISEN2+
+12V
PVCC3
BOOT3
UGATE3
VRSEL
PHASE3
PGOOD
+12V
LGATE3
ISEN3ISEN3+
EN
+12V
+12V
IOUT
EN_PH4
DRSEL
BOOT
VCC UGATE
PVCC
PHASE
ISL6612
LGATE
PWM4
GND
GND
ISEN4ISEN4+
5
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PWM
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January 22, 2015
ISL6312A
Typical Application - ISL6312A with NTC Thermal Compensation (4-Phase)
+12V
VDIFF
FB
COMP
VSEN
BOOT1
RGND
NTC
UGATE1
+5V
PLACE IN
CLOSE
PROXIMITY
PHASE1
VCC
LGATE1
ISEN1ISEN1+
OFS
FS
+12V
REF
PVCC1_2
BOOT2
SS
UGATE2
PHASE2
OVPSEL
LGATE2
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
ISL6312A
LOAD
ISEN2ISEN2+
+12V
PVCC3
BOOT3
VRSEL
UGATE3
PGOOD
PHASE3
+12V
LGATE3
ISEN3ISEN3+
EN
+12V
+12V
IOUT
EN_PH4
DRSEL
BOOT
VCC UGATE
PVCC
PHASE
ISL6612
LGATE
PWM4
PWM
GND
GND
ISEN4ISEN4+
6
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ISL6312A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to + 6V
Supply Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V
BOOT Voltage, VBOOT . . . . . . . . . . . . . . GND - 0.3V to GND + 36V
BOOT to PHASE Voltage, VBOOT-PHASE . . . . . . -0.3V to 15V (DC)
-0.3V to 16V (<10ns, 10µJ)
PHASE Voltage, VPHASE . . . . . . . GND - 0.3V to 15V (PVCC = 12)
GND - 8V (<400ns, 20µJ) to 24V (<200ns, VBOOT - PHASE = 12V)
UGATE Voltage, VUGATE. . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE Voltage, VLGATE . . . . . . . . . . . GND - 0.3V to PVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to PVCC + 0.3V
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Resistance
JA (°C/W)
JC (°C/W)
27
2
QFN Package (Notes 4, 5) . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%
PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5%
Ambient Temperature
(ISL6312ACRZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
(ISL6312AIRZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7) UNITS
BIAS SUPPLIES
Input Bias Supply Current
IVCC; EN = high
15
20
25
mA
Gate Drive Bias Current - PVCC1_2 Pin
IPVCC1_2; EN = high
2
4.3
6
mA
Gate Drive Bias Current - PVCC3 Pin
IPVCC3; EN = high
VCC POR (Power-On Reset) Threshold
VCC rising
VCC falling
3.75
3.88
4.00
V
PVCC POR (Power-On Reset) Threshold
PVCC rising
4.25
4.38
4.50
V
PVCC falling
3.60
3.88
4.00
V
1
2.1
3
mA
4.25
4.38
4.50
V
PWM MODULATOR
Oscillator Frequency Accuracy, fSW
RT = 100k(±0.1%)
225
250
275
kHz
Adjustment Range of Switching Frequency
(Note 6)
0.08
-
1.0
MHz
Oscillator Ramp Amplitude, VPP
(Note 6)
-
1.50
-
V
0.81
0.85
0.91
V
80
110
140
mV
EN_PH4 Rising Threshold
1.160
1.210
1.250
V
EN_PH4 Falling Threshold
1.00
1.06
1.10
V
0.1
0.2
0.3
V
System Accuracy (1.000V to 1.600V)
-0.5
-
0.5
%
System Accuracy (0.600V to 1.000V)
-1.0
-
1.0
%
System Accuracy (0.375V - 0.600V)
CONTROL THRESHOLDS
EN Rising Threshold
EN Hysteresis
COMP Shutdown Threshold
COMP falling
REFERENCE AND DAC
-2.0
-
2.0
%
DAC Input Low Voltage (VR10, VR11)
-
-
0.4
V
DAC Input High Voltage (VR10, VR11)
0.8
-
-
V
DAC Input Low Voltage (AMD)
-
-
0.6
V
DAC Input High Voltage (AMD)
1.0
-
-
V
7
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ISL6312A
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7) UNITS
PIN-ADJUSTABLE OFFSET
OFS Sink Current Accuracy (Negative Offset)
ROFS = 10kfrom OFS to GND
37.0
40.0
43.0
A
OFS Source Current Accuracy (Positive Offset)
ROFS = 30kfrom OFS to VCC
50.5
53.5
56.5
A
ERROR AMPLIFIER
DC Gain
RL = 10k to ground, (Note 6)
-
96
-
dB
Gain-Bandwidth Product
CL = 100pF, RL = 10k to ground, (Note 6)
-
20
-
MHz
Slew Rate
CL = 100pF, load = ±400µA, (Note 6)
-
8
-
V/s
Maximum Output Voltage
Load = 1mA
3.90
4.20
-
V
Minimum Output Voltage
Load = -1mA
-
1.30
1.5
V
VR10/VR11, RS = 100k
-
1.563
-
mV/µs
SOFT-START RAMP
Soft-Start Ramp Rate
AMD
Adjustment Range of Soft-Start Ramp Rate (Note 6)
-
2.063
-
mV/µs
0.625
-
6.25
mV/µs
PWM OUTPUT
PWM Output Voltage LOW Threshold
Iload = ±500A
-
-
0.5
V
PWM Output Voltage HIGH Threshold
Iload = ±500A
4.5
-
-
V
Current Sense Resistance, RISEN
T = +25°C
297
300
303

Sensed Current Tolerance
ISEN1+ = ISEN2+ = ISEN3+ = ISEN4+ = 80µA
76
80
84
µA
Overcurrent Trip Level - Average Channel
Normal operation
110
125
140
µA
Dynamic VID change
143
163
183
µA
Overcurrent Trip Level - Individual Channel
Normal operation
150
177
204
µA
Dynamic VID change (Note 6)
209.4
238
266.6
µA
Overcurrent Protection Voltage Threshold (IOUT)
VIOUT driven to VOCP.
1.97
2.02
2.07
V
55
60
65
%VID
CURRENT SENSING
OVERCURRENT PROTECTION
PROTECTION
Undervoltage Threshold
VSEN falling
Undervoltage Hysteresis
VSEN rising
-
10
-
%VID
Overvoltage Threshold During Soft-Start
VR10 to VR11
1.24
1.28
1.32
V
AMD
2.13
2.20
2.27
V
VR10 to VR11, OVPSEL tied to ground, VSEN rising VDAC +
150mV
VDAC +
175mV
VDAC +
200mV
V
AMD, OVPSEL tied to ground, VSEN rising
VDAC +
225mV
VDAC +
250mV
VDAC +
275mV
V
Overvoltage Threshold (Alternate)
OVPSEL tied to +5V, VSEN rising
VDAC +
325mV
VDAC +
350mV
VDAC +
375mV
V
Overvoltage Hysteresis
VSEN falling
-
100
-
mV
Overvoltage Threshold (Default)
8
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ISL6312A
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7) UNITS
SWITCHING TIME (Note 6)
UGATE Rise Time
tRUGATE; VPVCC = 12V, 3nF load, 10% to 90%
-
26
-
ns
LGATE Rise Time
tRLGATE; VPVCC = 12V, 3nF load, 10% to 90%
-
18
-
ns
UGATE Fall Time
tFUGATE; VPVCC = 12V, 3nF load, 90% to 10%
-
18
-
ns
LGATE Fall Time
tFLGATE; VPVCC = 12V, 3nF load, 90% to 10%
-
12
-
ns
UGATE Turn-On Non-Overlap
tPDHUGATE; VPVCC = 12V, 3nF load, adaptive
-
10
-
ns
LGATE Turn-On Non-Overlap
tPDHLGATE; VPVCC = 12V, 3nF load, adaptive
-
10
-
ns
1.25
2.0
3.0

GATE DRIVE RESISTANCE (Note 6))
Upper Drive Source Resistance
VPVCC = 12V, 15mA source current
Upper Drive Sink Resistance
VPVCC = 12V, 15mA sink current
0.9
1.65
3.0

Lower Drive Source Resistance
VPVCC = 12V, 15mA source current
0.85
1.25
2.2

Lower Drive Sink Resistance
VPVCC = 12V, 15mA sink current
0.60
0.80
1.35

Thermal Shutdown Setpoint
-
160
-
°C
Thermal Recovery Setpoint
-
100
-
°C
OVER-TEMPERATURE SHUTDOWN (Note 6))
NOTES:
6. Limits established by characterization and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Timing Diagram
tPDHUGATE
tRUGATE
tFUGATE
UGATE
LGATE
tFLGATE
tRLGATE
tPDHLGATE
9
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ISL6312A
Functional Pin Description
VCC
VCC is the bias supply for the ICs small-signal circuitry.
Connect this pin to a +5V supply and decouple using a
quality 0.1F ceramic capacitor.
PVCC1_2 and PVCC3
These pins are the power supply pins for the corresponding
channel MOSFET drive, and can be connected to any
voltage from +5V to +12V depending on the desired
MOSFET gate-drive level. Decouple these pins with a quality
1.0F ceramic capacitor.
Leaving PVCC3 unconnected or grounded programs the
controller for 2-phase operation.
GND
GND is the bias and reference ground for the IC.
EN
This pin is a threshold-sensitive (approximately 0.85V) enable
input for the controller. Held low, this pin disables controller
operation. Pulled high, the pin enables the controller for
operation.
FS
A resistor, placed from FS to ground, sets the switching
frequency of the controller.
VID0, VID1, VID2, VID3, VID4, VID5, VID6, and VID7
These are the inputs for the internal DAC that provides the
reference voltage for output regulation. These pins respond to
TTL logic thresholds. These pins are internally pulled high, to
approximately 1.2V, by 40µA internal current sources for Intel
modes of operation, and pulled low by 20µA internal current
sources for AMD modes of operation. The internal pull-up
current decreases to 0 as the VID voltage approaches the
internal pull-up voltage. All VID pins are compatible with
external pull-up voltages not exceeding the IC’s bias voltage
(VCC).
FB and COMP
These pins are the internal error amplifier inverting input and
output respectively. FB, VDIFF, and COMP are tied together
through external R-C networks to compensate the regulator.
IOUT
The IOUT pin is the average channel-current sense output.
Connecting this pin through a resistor to ground allows the
controller to set the overcurrent protection trip level. This pin
pin can also be used as a load current indicator to monitor
what the output load current is.
REF
The REF input pin is the positive input of the error amplifier. It is
internally connected to the DAC output through a 1k resistor.
A capacitor is used between the REF pin and ground to smooth
the voltage transition during Dynamic VID operations.
OFS
The OFS pin provides a means to program a DC current for
generating an offset voltage across the resistor between FB
and VDIFF. The offset current is generated via an external
resistor and precision internal voltage references. The polarity
of the offset is selected by connecting the resistor to GND or
VCC. For no offset, the OFS pin should be left unconnected.
ISEN1-, ISEN1+, ISEN2-, ISEN2+, ISEN3-, ISEN3+,
ISEN4- and ISEN4+
These pins are used for differentially sensing the corresponding
channel output currents. The sensed currents are used for
channel balancing, protection, and load-line regulation.
Connect ISEN1-, ISEN2-, ISEN3-, and ISEN4- to the node
between the RC sense elements surrounding the inductor of
their respective channel. Tie the ISEN+ pins to the VCORE
side of their corresponding channel’s sense capacitor.
UGATE1, UGATE2, and UGATE3
Connect these pins to the corresponding upper MOSFET
gates. These pins are used to control the upper MOSFETs
and are monitored for shoot-through prevention purposes.
VRSEL
BOOT1, BOOT2 and BOOT3
The state of this pin selects which of the available DAC tables
will be used to decode the VID inputs and puts the controller
into the corresponding mode of operation. Refer to Table 1 for
available options and details of implementation.
These pins provide the bias voltage for the corresponding
upper MOSFET drives. Connect these pins to appropriatelychosen external bootstrap capacitors. Internal bootstrap
diodes connected to the PVCC pins provide the necessary
bootstrap charge.
VSEN and RGND
VSEN and RGND are inputs to the precision differential
remote-sense amplifier and should be connected to the sense
pins of the remote load.
VDIFF
VDIFF is the output of the differential remote-sense amplifier.
The voltage on this pin is equal to the difference between
VSEN and RGND.
10
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PHASE1, PHASE2 and PHASE3
Connect these pins to the sources of the corresponding
upper MOSFETs. These pins are the return path for the
upper MOSFET drives.
LGATE1, LGATE2 and LGATE3
These pins are used to control the lower MOSFETs. Connect
these pins to the corresponding lower MOSFETs’ gates.
FN9290.6
January 22, 2015
ISL6312A
PWM4
Pulse-width modulation output. Connect this pin to the PWM
input pin of an Intersil driver IC if 4-phase operation is
desired.
IL1 + IL2 + IL3, 7A/DIV
EN_PH4
IL3, 7A/DIV
This pin has two functions. First, a resistor divider connected
to this pin will provide a POR power up synch between the
on-chip and external driver. The resistor divider should be
designed so that when the POR-trip point of the external
driver is reached the voltage on this pin should be 1.21V.
The second function of this pin is disabling PWM4 for
3-phase operation. This can be accomplished by connecting
this pin to a +5V supply.
SS
A resistor, placed from SS to ground, will set the soft-start
ramp slope for the Intel DAC modes of operation. Refer to
Equations 18 and 19 for proper resistor calculation.
For AMD modes of operation, the soft-start ramp frequency
is preset, so this pin can be left unconnected.
OVPSEL
This pin selects the OVP trip point during normal operation.
Leaving it unconnected or tieing it to ground selects the
default setting of VDAC+175mV for Intel Modes of operation
and VDAC+250mV for AMD modes of operation. Connecting
this pin to VCC will select an OVP trip setting of VID+350mV
for all modes of operation.
DRSEL
This pin selects the adaptive deadtime scheme the internal
drivers will use. If driving MOSFETs, tie this pin to ground to
select the PHASE detect scheme or to a +5V supply through
a 50k resistor to select the LGATE detect scheme.
PGOOD
During normal operation PGOOD indicates whether the
output voltage is within specified overvoltage and
undervoltage limits. If the output voltage exceeds these limits
or a reset event occurs (such as an overcurrent event),
PGOOD is pulled low. PGOOD is always low prior to the end
of soft-start.
Operation
Multiphase Power Conversion
Microprocessor load current profiles have changed to the
point that using single-phase regulators is no longer a viable
solution. Designing a regulator that is cost-effective,
thermally sound, and efficient has become a challenge that
only multiphase converters can accomplish. The ISL6312A
controller helps simplify implementation by integrating vital
functions and requiring minimal external components. The
“Block Diagram” on page 4 provides a top level view of
multiphase power conversion using the ISL6312A controller.
11
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PWM3, 5V/DIV
IL2, 7A/DIV
PWM2, 5V/DIV
IL1, 7A/DIV
PWM1, 5V/DIV
1s/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
Interleaving
The switching of each channel in a multiphase converter is
timed to be symmetrically out of phase with each of the other
channels. In a 3-phase converter, each channel switches 1/3
cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has a
combined ripple frequency three times greater than the ripple
frequency of any one phase. In addition, the peak-to-peak
amplitude of the combined inductor currents is reduced in
proportion to the number of phases (Equations 1 and 2).
Increased ripple frequency and lower ripple amplitude mean
that the designer can use less per-channel inductance and
lower total output capacitance for any performance
specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
pulse is terminated 1/3 of a cycle after the PWM pulse of the
previous phase. The peak-to-peak current for each phase is
about 7A, and the DC components of the inductor currents
combine to feed the load.
To understand the reduction of ripple current amplitude in the
multiphase circuit, examine the equation representing an
individual channel peak-to-peak inductor current.
 V IN – V OUT   V OUT
I  P – P  = --------------------------------------------------------L  fS  V
(EQ. 1)
IN
In Equation 1, VIN and VOUT are the input and output
voltages respectively, L is the single-channel inductor value,
and fS is the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
FN9290.6
January 22, 2015
ISL6312A
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
 V IN – N  V OUT   V OUT
I C,  P-P  = ------------------------------------------------------------------L  fS  V
(EQ. 2)
IN
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multiphase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 2 delivers 1.5V to a 36A load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has 11.9A
RMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent three-phase converter.
INPUT-CAPACITOR CURRENT, 10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
transitioned high. This is important because is allows the
controller to quickly respond to output voltage drops
associated with current load spikes, while avoiding the ring
back affects associated with other modulation schemes.
The PWM output state is driven by the position of the error
amplifier output signal, VCOMP, minus the current correction
signal relative to the proprietary modulator ramp waveform
as illustrated in Figure 3. At the beginning of each PWM time
interval, this modified VCOMP signal is compared to the
internal modulator waveform. As-long-as the modified
VCOMP voltage is lower then the modulator waveform
voltage, the PWM signal is commanded low. The internal
MOSFET driver detects the low state of the PWM signal and
turns off the upper MOSFET and turns on the lower
synchronous MOSFET. When the modified VCOMP voltage
crosses the modulator ramp, the PWM output transitions
high, turning off the synchronous MOSFET and turning on
the upper MOSFET. The PWM signal will remain high until
the modified VCOMP voltage crosses the modulator ramp
again. When this occurs the PWM signal will transition low
again.
During each PWM time interval the PWM signal can only
transition high once. Once PWM transitions high it can not
transition high again until the beginning of the next PWM
time interval. This prevents the occurrence of double PWM
pulses occurring during a single period.
To further improve the transient response, the ISL6312A
also implements Intersil’s proprietary Adaptive Phase
Alignment (APA) technique, which turns on all phases
together under transient events with large step current. With
both APP and APA control, the ISL6312A can achieve
excellent transient performance and reduce the demand on
the output capacitors.
Channel-Current Balance
CHANNEL 1
INPUT CURRENT
10A/DIV
1s/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND
INPUT-CAPACITOR RMS CURRENT FOR
3-PHASE CONVERTER
Active Pulse Positioning (APP) Modulated PWM
Operation
The ISL6312A uses a proprietary Active Pulse Positioning
(APP) modulation scheme to control the internal PWM
signals that command each channel’s driver to turn their
upper and lower MOSFETs on and off. The time interval in
which a PWM signal can occur is generated by an internal
clock, whose cycle time is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. The advantage of Intersil’s proprietary Active Pulse
Positioning (APP) modulator is that the PWM signal has the
ability to turn on at any point during this PWM time interval,
and turn off immediately after the PWM signal has
12
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One important benefit of multiphase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multiphase converter be controlled to
carry equal amounts of current at any load level. To achieve
this, the currents through each channel must be sampled
every switching cycle. The sampled currents, In, from each
active channel are summed together and divided by the
number of active channels. The resulting cycle average
current, IAVG, provides a measure of the total load-current
demand on the converter during each switching cycle.
Channel-current balance is achieved by comparing the
sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented current
FN9290.6
January 22, 2015
ISL6312A
-
L
MOSFET
DRIVER
LGATE(n)
f(s)
IAVG
-
+
VL(s)
R1
I4
IER
S
¸N
I3
DCR
VOUT
INDUCTOR
TO GATE
CONTROL
LOGIC
+
PWM1
L
+
MODULATOR
RAMP
WAVEFORM
FILTER
+
I
UGATE(n)
COUT
VC(s)
-
+
VCOMP
VIN
-
balance method is illustrated in Figure 3, with error
correction for Channel 1 represented. The cycle average
current, IAVG, is compared with the Channel 1 sample, I1 , to
create an error signal IER (see Figure 3).
C1
R2*
ISL6312A INTERNAL CIRCUIT
I2
In
I1
SAMPLE
FIGURE 3. CHANNEL-1 PWM FUNCTION AND CURRENT
BALANCE ADJUSTMENT
The filtered error signal modifies the pulse width
commanded by VCOMP to correct any unbalance and force
IER toward zero. The same method for error signal
correction is applied to each active channel.
+
+
-
VC(s)
RISEN
ISEN
-
NOTE: Channel 3 and 4 are optional.
ISEN-(n)
ISEN+(n)
*R2 is OPTIONAL
FIGURE 5. INDUCTOR DCR CURRENT SENSING
CONFIGURATION
PWM
SWITCHING PERIOD
IL
Inductor windings have a characteristic distributed
resistance or DCR (Direct Current Resistance). For
simplicity, the inductor DCR is considered as a separate
lumped quantity, as shown in Figure 5. The channel current
IL, flowing through the inductor, passes through the DCR.
Equation 3 shows the s-domain equivalent voltage, VL,
across the inductor.
V L  s  = I L   s  L + DCR 
ISEN
TIME
FIGURE 4. CONTINUOUS CURRENT SAMPLING
(EQ. 3)
A simple R-C network across the inductor (R1 and C)
extracts the DCR voltage, as shown in Figure 5. The voltage
across the sense capacitor, VC, can be shown to be
proportional to the channel current IL, shown in Equation 4.
sL
 ------------+ 1
 DCR

V C  s  = --------------------------------------  DCR  I L
 s  R1  C + 1 
(EQ. 4)
Continuous Current Sampling
In order to realize proper current balance, the currents in
each channel are sensed continuously every switching
cycle. During this time the current sense amplifier uses the
ISEN inputs to reproduce a signal proportional to the
inductor current, IL. This sensed current, ISEN, is simply a
scaled version of the inductor current.
In some cases it may be necessary to use a resistor divider
R-C network to sense the current through the inductor. This
can be accomplished by placing a second resistor, R2,
across the sense capacitor. In these cases the voltage
across the sense capacitor, VC, becomes proportional to the
channel current IL, and the resistor divider ratio, K.
The ISL6312A supports inductor DCR current sensing to
continuously sense each channel’s current for channel current
balance. The internal circuitry, shown in Figure 5 represents
Channel N of an N-channel converter. This circuitry is repeated
for each channel in the converter, but may not be active
depending on how many channels are operating.
13
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FN9290.6
January 22, 2015
ISL6312A
sL
 ------------+ 1
 DCR

V C  s  = --------------------------------------------------------  K  DCR  I L
  R1  R2 

 s  ------------------------  C + 1
+
R
R


1
2
(EQ. 5)
R2
K = --------------------R2 + R1
(EQ. 6)
If the R-C network components are selected such that the
RC time constant matches the inductor L/DCR time
constant, then VC is equal to the voltage drop across the
DCR multiplied by the ratio of the resistor divider, K. If a
resistor divider is not being used, the value for K is 1.
The capacitor voltage VC, is then replicated across the
sense resistor RISEN. The current through RISEN is
proportional to the inductor current. Equation 7 shows that
the proportion between the channel current and the sensed
current (ISEN) is driven by the value of the sense resistor,
the resistor divider ratio, and the DCR of the inductor.
DCR
I SEN = K  I L  -----------------R ISEN
(EQ. 7)
Output Voltage Setting
The ISL6312A uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at
the VID pins. The DAC decodes the logic signals into one of
the discrete voltages shown in Tables 2, 3, 4 and 5. In Intel
modes of operation, each VID pin is pulled up to an internal
1.2V voltage by a weak current source (40µA), which
decreases to 0A as the voltage at the VID pin varies from 0
to the internal 1.2V pull-up voltage. In AMD modes of
operation the VID pins are pulled low by a weak 20µA
current source. External pull-up resistors or active-high
output stages can augment the pull-up current sources, up to
a voltage of 5V.
The ISL6312A accommodates four different DAC ranges:
Intel VR10 (Extended), Intel VR11, AMD K8/K9 5-bit, and
AMD 6-bit. The state of the VRSEL and VID7 pins decide
which DAC version is active. Refer to Table 1 for a description
of how to select the desired DAC version. For VR11 setting,
tie the VRSEL pin to the midpoint of a 10k(or other suitable
value) resistor divider connected from VCC to GND.
TABLE 1. ISL6312A DAC SELECT TABLE
DAC VERSION
VRSEL PIN
VID7 PIN
VR10(Extended)
VRSEL = GND
-
VR11
VRSEL = VCC/2
-
AMD 5-Bit
VRSEL = VCC
LOW
AMD 6-Bit
VRSEL = VCC
HIGH
14
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TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION
CODES
VID4
VID3
VID2
VID1
VID0
VID5
VID6
VDAC
0
1
0
1
0
1
1
1.60000
0
1
0
1
0
1
0
1.59375
0
1
0
1
1
0
1
1.58750
0
1
0
1
1
0
0
1.58125
0
1
0
1
1
1
1
1.57500
0
1
0
1
1
1
0
1.56875
0
1
1
0
0
0
1
1.56250
0
1
1
0
0
0
0
1.55625
0
1
1
0
0
1
1
1.55000
0
1
1
0
0
1
0
1.54375
0
1
1
0
1
0
1
1.53750
0
1
1
0
1
0
0
1.53125
0
1
1
0
1
1
1
1.52500
0
1
1
0
1
1
0
1.51875
0
1
1
1
0
0
1
1.51250
0
1
1
1
0
0
0
1.50625
0
1
1
1
0
1
1
1.50000
0
1
1
1
0
1
0
1.49375
0
1
1
1
1
0
1
1.48750
0
1
1
1
1
0
0
1.48125
0
1
1
1
1
1
1
1.47500
0
1
1
1
1
1
0
1.46875
1
0
0
0
0
0
1
1.46250
1
0
0
0
0
0
0
1.45625
1
0
0
0
0
1
1
1.45000
1
0
0
0
0
1
0
1.44375
1
0
0
0
1
0
1
1.43750
1
0
0
0
1
0
0
1.43125
1
0
0
0
1
1
1
1.42500
1
0
0
0
1
1
0
1.41875
1
0
0
1
0
0
1
1.41250
1
0
0
1
0
0
0
1.40625
1
0
0
1
0
1
1
1.40000
1
0
0
1
0
1
0
1.39375
1
0
0
1
1
0
1
1.38750
1
0
0
1
1
0
0
1.38125
1
0
0
1
1
1
1
1.37500
1
0
0
1
1
1
0
1.36875
1
0
1
0
0
0
1
1.36250
FN9290.6
January 22, 2015
ISL6312A
TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION
CODES (Continued)
TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION
CODES (Continued)
VID4
VID3
VID2
VID1
VID0
VID5
VID6
VDAC
VID4
VID3
VID2
VID1
VID0
VID5
VID6
VDAC
1
0
1
0
0
0
0
1.35625
1
1
1
1
0
0
1
1.11250
1
0
1
0
0
1
1
1.35000
1
1
1
1
0
0
0
1.10625
1
0
1
0
0
1
0
1.34375
1
1
1
1
0
1
1
1.10000
1
0
1
0
1
0
1
1.33750
1
1
1
1
0
1
0
1.09375
1
0
1
0
1
0
0
1.33125
1
1
1
1
1
0
1
OFF
1
0
1
0
1
1
1
1.32500
1
1
1
1
1
0
0
OFF
1
0
1
0
1
1
0
1.31875
1
1
1
1
1
1
1
OFF
1
0
1
1
0
0
1
1.31250
1
1
1
1
1
1
0
OFF
1
0
1
1
0
0
0
1.30625
0
0
0
0
0
0
1
1.08750
1
0
1
1
0
1
1
1.30000
0
0
0
0
0
0
0
1.08125
1
0
1
1
0
1
0
1.29375
0
0
0
0
0
1
1
1.07500
1
0
1
1
1
0
1
1.28750
0
0
0
0
0
1
0
1.06875
1
0
1
1
1
0
0
1.28125
0
0
0
0
1
0
1
1.06250
1
0
1
1
1
1
1
1.27500
0
0
0
0
1
0
0
1.05625
1
0
1
1
1
1
0
1.26875
0
0
0
0
1
1
1
1.05000
1
1
0
0
0
0
1
1.26250
0
0
0
0
1
1
0
1.04375
1
1
0
0
0
0
0
1.25625
0
0
0
1
0
0
1
1.03750
1
1
0
0
0
1
1
1.25000
0
0
0
1
0
0
0
1.03125
1
1
0
0
0
1
0
1.24375
0
0
0
1
0
1
1
1.02500
1
1
0
0
1
0
1
1.23750
0
0
0
1
0
1
0
1.01875
1
1
0
0
1
0
0
1.23125
0
0
0
1
1
0
1
1.01250
1
1
0
0
1
1
1
1.22500
0
0
0
1
1
0
0
1.00625
1
1
0
0
1
1
0
1.21875
0
0
0
1
1
1
1
1.00000
1
1
0
1
0
0
1
1.21250
0
0
0
1
1
1
0
0.99375
1
1
0
1
0
0
0
1.20625
0
0
1
0
0
0
1
0.98750
1
1
0
1
0
1
1
1.20000
0
0
1
0
0
0
0
0.98125
1
1
0
1
0
1
0
1.19375
0
0
1
0
0
1
1
0.97500
1
1
0
1
1
0
1
1.18750
0
0
1
0
0
1
0
0.96875
1
1
0
1
1
0
0
1.18125
0
0
1
0
1
0
1
0.96250
1
1
0
1
1
1
1
1.17500
0
0
1
0
1
0
0
0.95625
1
1
0
1
1
1
0
1.16875
0
0
1
0
1
1
1
0.95000
1
1
1
0
0
0
1
1.16250
0
0
1
0
1
1
0
0.94375
1
1
1
0
0
0
0
1.15625
0
0
1
1
0
0
1
0.93750
1
1
1
0
0
1
1
1.15000
0
0
1
1
0
0
0
0.93125
1
1
1
0
0
1
0
1.14375
0
0
1
1
0
1
1
0.92500
1
1
1
0
1
0
1
1.13750
0
0
1
1
0
1
0
0.91875
1
1
1
0
1
0
0
1.13125
0
0
1
1
1
0
1
0.91250
1
1
1
0
1
1
1
1.12500
0
0
1
1
1
0
0
0.90625
1
1
1
0
1
1
0
1.11875
0
0
1
1
1
1
1
0.90000
15
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FN9290.6
January 22, 2015
ISL6312A
TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION
CODES (Continued)
TABLE 3. VR11 VOLTAGE IDENTIFICATION
CODES (Continued)
VID4
VID3
VID2
VID1
VID0
VID5
VID6
VDAC
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
0
0
1
1
1
1
0
0.89375
0
0
0
1
1
0
0
1
1.45625
0
1
0
0
0
0
1
0.88750
0
0
0
1
1
0
1
0
1.45000
0
1
0
0
0
0
0
0.88125
0
0
0
1
1
0
1
1
1.44375
0
1
0
0
0
1
1
0.87500
0
0
0
1
1
1
0
0
1.43750
0
1
0
0
0
1
0
0.86875
0
0
0
1
1
1
0
1
1.43125
0
1
0
0
1
0
1
0.86250
0
0
0
1
1
1
1
0
1.42500
0
1
0
0
1
0
0
0.85625
0
0
0
1
1
1
1
1
1.41875
0
1
0
0
1
1
1
0.85000
0
0
1
0
0
0
0
0
1.41250
0
1
0
0
1
1
0
0.84375
0
0
1
0
0
0
0
1
1.40625
0
1
0
1
0
0
1
0.83750
0
0
1
0
0
0
1
0
1.40000
0
1
0
1
0
0
0
0.83125
0
0
1
0
0
0
1
1
1.39375
0
0
1
0
0
1
0
0
1.38750
0
0
1
0
0
1
0
1
1.38125
TABLE 3. VR11 VOLTAGE IDENTIFICATION
CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
0
0
1
0
0
1
1
0
1.37500
0
0
0
0
0
0
0
0
OFF
0
0
1
0
0
1
1
1
1.36875
0
0
0
0
0
0
0
1
OFF
0
0
1
0
1
0
0
0
1.36250
0
0
0
0
0
0
1
0
1.60000
0
0
1
0
1
0
0
1
1.35625
0
0
0
0
0
0
1
1
1.59375
0
0
1
0
1
0
1
0
1.35000
0
0
0
0
0
1
0
0
1.58750
0
0
1
0
1
0
1
1
1.34375
0
0
0
0
0
1
0
1
1.58125
0
0
1
0
1
1
0
0
1.33750
0
0
0
0
0
1
1
0
1.57500
0
0
1
0
1
1
0
1
1.33125
0
0
0
0
0
1
1
1
1.56875
0
0
1
0
1
1
1
0
1.32500
0
0
0
0
1
0
0
0
1.56250
0
0
1
0
1
1
1
1
1.31875
0
0
0
0
1
0
0
1
1.55625
0
0
1
1
0
0
0
0
1.31250
0
0
0
0
1
0
1
0
1.55000
0
0
1
1
0
0
0
1
1.30625
0
0
0
0
1
0
1
1
1.54375
0
0
1
1
0
0
1
0
1.30000
0
0
0
0
1
1
0
0
1.53750
0
0
1
1
0
0
1
1
1.29375
0
0
0
0
1
1
0
1
1.53125
0
0
1
1
0
1
0
0
1.28750
0
0
0
0
1
1
1
0
1.52500
0
0
1
1
0
1
0
1
1.28125
0
0
0
0
1
1
1
1
1.51875
0
0
1
1
0
1
1
0
1.27500
0
0
0
1
0
0
0
0
1.51250
0
0
1
1
0
1
1
1
1.26875
0
0
0
1
0
0
0
1
1.50625
0
0
1
1
1
0
0
0
1.26250
0
0
0
1
0
0
1
0
1.50000
0
0
1
1
1
0
0
1
1.25625
0
0
0
1
0
0
1
1
1.49375
0
0
1
1
1
0
1
0
1.25000
0
0
0
1
0
1
0
0
1.48750
0
0
1
1
1
0
1
1
1.24375
0
0
0
1
0
1
0
1
1.48125
0
0
1
1
1
1
0
0
1.23750
0
0
0
1
0
1
1
0
1.47500
0
0
1
1
1
1
0
1
1.23125
0
0
0
1
0
1
1
1
1.46875
0
0
1
1
1
1
1
0
1.22500
0
0
0
1
1
0
0
0
1.46250
0
0
1
1
1
1
1
1
1.21875
16
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FN9290.6
January 22, 2015
ISL6312A
TABLE 3. VR11 VOLTAGE IDENTIFICATION
CODES (Continued)
TABLE 3. VR11 VOLTAGE IDENTIFICATION
CODES (Continued)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
0
1
0
0
0
0
0
0
1.21250
0
1
1
0
0
1
1
1
0.96875
0
1
0
0
0
0
0
1
1.20625
0
1
1
0
1
0
0
0
0.96250
0
1
0
0
0
0
1
0
1.20000
0
1
1
0
1
0
0
1
0.95625
0
1
0
0
0
0
1
1
1.19375
0
1
1
0
1
0
1
0
0.95000
0
1
0
0
0
1
0
0
1.18750
0
1
1
0
1
0
1
1
0.94375
0
1
0
0
0
1
0
1
1.18125
0
1
1
0
1
1
0
0
0.93750
0
1
0
0
0
1
1
0
1.17500
0
1
1
0
1
1
0
1
0.93125
0
1
0
0
0
1
1
1
1.16875
0
1
1
0
1
1
1
0
0.92500
0
1
0
0
1
0
0
0
1.16250
0
1
1
0
1
1
1
1
0.91875
0
1
0
0
1
0
0
1
1.15625
0
1
1
1
0
0
0
0
0.91250
0
1
0
0
1
0
1
0
1.15000
0
1
1
1
0
0
0
1
0.90625
0
1
0
0
1
0
1
1
1.14375
0
1
1
1
0
0
1
0
0.90000
0
1
0
0
1
1
0
0
1.13750
0
1
1
1
0
0
1
1
0.89375
0
1
0
0
1
1
0
1
1.13125
0
1
1
1
0
1
0
0
0.88750
0
1
0
0
1
1
1
0
1.12500
0
1
1
1
0
1
0
1
0.88125
0
1
0
0
1
1
1
1
1.11875
0
1
1
1
0
1
1
0
0.87500
0
1
0
1
0
0
0
0
1.11250
0
1
1
1
0
1
1
1
0.86875
0
1
0
1
0
0
0
1
1.10625
0
1
1
1
1
0
0
0
0.86250
0
1
0
1
0
0
1
0
1.10000
0
1
1
1
1
0
0
1
0.85625
0
1
0
1
0
0
1
1
1.09375
0
1
1
1
1
0
1
0
0.85000
0
1
0
1
0
1
0
0
1.08750
0
1
1
1
1
0
1
1
0.84375
0
1
0
1
0
1
0
1
1.08125
0
1
1
1
1
1
0
0
0.83750
0
1
0
1
0
1
1
0
1.07500
0
1
1
1
1
1
0
1
0.83125
0
1
0
1
0
1
1
1
1.06875
0
1
1
1
1
1
1
0
0.82500
0
1
0
1
1
0
0
0
1.06250
0
1
1
1
1
1
1
1
0.81875
0
1
0
1
1
0
0
1
1.05625
1
0
0
0
0
0
0
0
0.81250
0
1
0
1
1
0
1
0
1.05000
1
0
0
0
0
0
0
1
0.80625
0
1
0
1
1
0
1
1
1.04375
1
0
0
0
0
0
1
0
0.80000
0
1
0
1
1
1
0
0
1.03750
1
0
0
0
0
0
1
1
0.79375
0
1
0
1
1
1
0
1
1.03125
1
0
0
0
0
1
0
0
0.78750
0
1
0
1
1
1
1
0
1.02500
1
0
0
0
0
1
0
1
0.78125
0
1
0
1
1
1
1
1
1.01875
1
0
0
0
0
1
1
0
0.77500
0
1
1
0
0
0
0
0
1.01250
1
0
0
0
0
1
1
1
0.76875
0
1
1
0
0
0
0
1
1.00625
1
0
0
0
1
0
0
0
0.76250
0
1
1
0
0
0
1
0
1.00000
1
0
0
0
1
0
0
1
0.75625
0
1
1
0
0
0
1
1
0.99375
1
0
0
0
1
0
1
0
0.75000
0
1
1
0
0
1
0
0
0.98750
1
0
0
0
1
0
1
1
0.74375
0
1
1
0
0
1
0
1
0.98125
1
0
0
0
1
1
0
0
0.73750
0
1
1
0
0
1
1
0
0.97500
1
0
0
0
1
1
0
1
0.73125
17
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FN9290.6
January 22, 2015
ISL6312A
TABLE 3. VR11 VOLTAGE IDENTIFICATION
CODES (Continued)
TABLE 4. AMD 5-BIT VOLTAGE IDENTIFICATION
CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
VID4
VID3
VID2
VID1
VID0
VDAC
1
0
0
0
1
1
1
0
0.72500
1
1
1
1
1
Off
1
0
0
0
1
1
1
1
0.71875
1
1
1
1
0
0.800
1
0
0
1
0
0
0
0
0.71250
1
1
1
0
1
0.825
1
0
0
1
0
0
0
1
0.70625
1
1
1
0
0
0.850
1
0
0
1
0
0
1
0
0.70000
1
1
0
1
1
0.875
1
0
0
1
0
0
1
1
0.69375
1
1
0
1
0
0.900
1
0
0
1
0
1
0
0
0.68750
1
1
0
0
1
0.925
1
0
0
1
0
1
0
1
0.68125
1
1
0
0
0
0.950
1
0
0
1
0
1
1
0
0.67500
1
0
1
1
1
0.975
1
0
0
1
0
1
1
1
0.66875
1
0
1
1
0
1.000
1
0
0
1
1
0
0
0
0.66250
1
0
1
0
1
1.025
1
0
0
1
1
0
0
1
0.65625
1
0
1
0
0
1.050
1
0
0
1
1
0
1
0
0.65000
1
0
0
1
1
1.075
1
0
0
1
1
0
1
1
0.64375
1
0
0
1
0
1.100
1
0
0
1
1
1
0
0
0.63750
1
0
0
0
1
1.125
1
0
0
1
1
1
0
1
0.63125
1
0
0
0
0
1.150
1
0
0
1
1
1
1
0
0.62500
0
1
1
1
1
1.175
1
0
0
1
1
1
1
1
0.61875
0
1
1
1
0
1.200
1
0
1
0
0
0
0
0
0.61250
0
1
1
0
1
1.225
1
0
1
0
0
0
0
1
0.60625
0
1
1
0
0
1.250
1
0
1
0
0
0
1
0
0.60000
0
1
0
1
1
1.275
1
0
1
0
0
0
1
1
0.59375
0
1
0
1
0
1.300
1
0
1
0
0
1
0
0
0.58750
0
1
0
0
1
1.325
1
0
1
0
0
1
0
1
0.58125
0
1
0
0
0
1.350
1
0
1
0
0
1
1
0
0.57500
0
0
1
1
1
1.375
1
0
1
0
0
1
1
1
0.56875
0
0
1
1
0
1.400
1
0
1
0
1
0
0
0
0.56250
0
0
1
0
1
1.425
1
0
1
0
1
0
0
1
0.55625
0
0
1
0
0
1.450
1
0
1
0
1
0
1
0
0.55000
0
0
0
1
1
1.475
1
0
1
0
1
0
1
1
0.54375
0
0
0
1
0
1.500
1
0
1
0
1
1
0
0
0.53750
0
0
0
0
1
1.525
1
0
1
0
1
1
0
1
0.53125
0
0
0
0
0
1.550
1
0
1
0
1
1
1
0
0.52500
1
0
1
0
1
1
1
1
0.51875
1
0
1
1
0
0
0
0
0.51250
1
0
1
1
0
0
0
1
0.50625
1
0
1
1
0
0
1
0
0.50000
1
1
1
1
1
1
1
0
OFF
1
1
1
1
1
1
1
1
OFF
18
Submit Document Feedback
FN9290.6
January 22, 2015
ISL6312A
TABLE 5. AMD 6-BIT VOLTAGE IDENTIFICATION
CODES (Continued)
TABLE 5. AMD 6-BIT VOLTAGE IDENTIFICATION
CODES
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
0
0
0
0
0
0
1.5500
1
0
0
1
1
1
0.6750
0
0
0
0
0
1
1.5250
1
0
1
0
0
0
0.6625
0
0
0
0
1
0
1.5000
1
0
1
0
0
1
0.6500
0
0
0
0
1
1
1.4750
1
0
1
0
1
0
0.6375
0
0
0
1
0
0
1.4500
1
0
1
0
1
1
0.6250
0
0
0
1
0
1
1.4250
1
0
1
1
0
0
0.6125
0
0
0
1
1
0
1.4000
1
0
1
1
0
1
0.6000
0
0
0
1
1
1
1.3750
1
0
1
1
1
0
0.5875
0
0
1
0
0
0
1.3500
1
0
1
1
1
1
0.5750
0
0
1
0
0
1
1.3250
1
1
0
0
0
0
0.5625
0
0
1
0
1
0
1.3000
1
1
0
0
0
1
0.5500
0
0
1
0
1
1
1.2750
1
1
0
0
1
0
0.5375
0
0
1
1
0
0
1.2500
1
1
0
0
1
1
0.5250
0
0
1
1
0
1
1.2250
1
1
0
1
0
0
0.5125
0
0
1
1
1
0
1.2000
1
1
0
1
0
1
0.5000
0
0
1
1
1
1
1.1750
1
1
0
1
1
0
0.4875
0
1
0
0
0
0
1.1500
1
1
0
1
1
1
0.4750
0
1
0
0
0
1
1.1250
1
1
1
0
0
0
0.4625
0
1
0
0
1
0
1.1000
1
1
1
0
0
1
0.4500
0
1
0
0
1
1
1.0750
1
1
1
0
1
0
0.4375
0
1
0
1
0
0
1.0500
1
1
1
0
1
1
0.4250
0
1
0
1
0
1
1.0250
1
1
1
1
0
0
0.4125
0
1
0
1
1
0
1.0000
1
1
1
1
0
1
0.4000
0
1
0
1
1
1
0.9750
1
1
1
1
1
0
0.3875
0
1
1
0
0
0
0.9500
1
1
1
1
1
1
0.3750
0
1
1
0
0
1
0.9250
0
1
1
0
1
0
0.9000
0
1
1
0
1
1
0.8750
0
1
1
1
0
0
0.8500
0
1
1
1
0
1
0.8250
0
1
1
1
1
0
0.8000
0
1
1
1
1
1
0.7750
1
0
0
0
0
0
0.7625
1
0
0
0
0
1
0.7500
1
0
0
0
1
0
0.7375
1
0
0
0
1
1
0.7250
1
0
0
1
0
0
0.7125
1
0
0
1
0
1
0.7000
1
0
0
1
1
0
0.6875
19
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Voltage Regulation
The integrating compensation network shown in Figure 6
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6312A to include the
combined tolerances of each of these elements.
The output of the error amplifier, VCOMP, is compared to the
triangle waveform to generate the PWM signals. The PWM
signals control the timing of the Internal MOSFET drivers
and regulate the converter output so that the voltage at FB is
equal to the voltage at REF. This will regulate the output
voltage to be equal to Equation 8. The internal and external
circuitry that controls voltage regulation is illustrated in
Figure 6.
FN9290.6
January 22, 2015
ISL6312A
.
(EQ. 8)
V OUT = V REF – V OFS – V DROOP
The ISL6312A incorporates an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered, when measuring the
output voltage relative to the controller ground reference
point resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the
non-inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, VDIFF, is
connected to the inverting input of the error amplifier through
an external resistor.
EXTERNAL CIRCUIT
ISL6312A INTERNAL CIRCUIT
COMP
1k
CREF
FB
ERROR
AMPLIFIER
+
-
VCOMP
IOFS
RFB
+
(VDROOP + VOFS)
-
IAVG
VOUT-
VSEN
+
-
RGND
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
Load-Line (Droop) Regulation
Some microprocessor manufacturers require a precisely
controlled output resistance. This dependence of output
voltage on load current is often termed “droop” or “load-line”
regulation. By adding a well controlled output impedance,
the output voltage can effectively be level shifted in a
direction which works to achieve the load-line regulation
required by these manufacturers.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
20
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(EQ. 9)
(EQ. 10)
In Equation 10, VREF is the reference voltage, VOFS is the
programmed offset voltage, IOUT is the total output current
of the converter, RISEN is the internal sense resistor
connected to the ISEN+ pin, RFB is the feedback resistor, N
is the active channel number, and DCR is the Inductor DCR
value. Therefore the equivalent loadline impedance, i.e.
droop impedance, is equal to Equation 11:
R FB DCR
R LL = ------------  -----------------N
R ISEN
VDIFF
VOUT+
V DROOP = I AVG  R FB
 I OUT DCR

V OUT = V REF – V OFS –  -------------  ------------------  R FB
N
R


ISEN
REF
RC
As shown in Figure 6, a current proportional to the average
current of all active channels, IAVG, flows from FB through a
load-line regulation resistor RFB. The resulting voltage drop
across RFB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as:
The regulated output voltage is reduced by the droop voltage
VDROOP. The output voltage as a function of load current is
derived by combining Equations 7, 8 and 9.
VID DAC
CC
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
(EQ. 11)
Output Voltage Offset Programming
The ISL6312A allows the designer to accurately adjust the
offset voltage by connecting a resistor, ROFS, from the OFS
pin to VCC or GND. When ROFS is connected between OFS
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (IOFS) to flow into the FB pin.
If ROFS is connected to ground, the voltage across it is
regulated to 0.4V, and IOFS flows out of the FB pin. The
offset current flowing through the resistor between VDIFF
and FB will generate the desired offset voltage, which is
equal to the product (IOFS x RFB). These functions are
shown in Figures 7 and 8.
Once the desired output offset voltage has been determined,
use the following formulas to set ROFS:
For Negative Offset (connect ROFS to GND):
0.4  R FB
R OFS = -------------------------V OFFSET
(EQ. 12)
For Positive Offset (connect ROFS to VCC):
1.6  R FB
R OFS = -------------------------V OFFSET
(EQ. 13)
FN9290.6
January 22, 2015
ISL6312A
INTEL DYNAMIC VID TRANSITIONS
FB
-
VOFS
+
RFB
E/A
IOFS
REF
1:1
CURRENT
MIRROR
VDIFF
IOFS
VCC
1.6V
+
ROFS
OFS
ISL6312A
VCC
FIGURE 7. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
FB
+
VOFS
-
IOFS
REF
VDIFF
C REF = 0.001  S   T VID
VCC
1:1
CURRENT
MIRROR
IOFS
AMD DYNAMIC VID TRANSITIONS
OFS
ISL6312A
GND
GND
FIGURE 8. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the ISL6312A
to do this by making changes to the VID inputs. The ISL6312A
is required to monitor the DAC inputs and respond to
on-the-fly VID changes in a controlled manner, supervising a
safe output voltage transition without discontinuity or
disruption. The DAC mode for the ISL6312A is operating in
determines how the controller responds to a dynamic VID
change.
21
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(EQ. 14)
As an example, for a VID step change rate of 5s per bit, the
value of CREF is 5600pF based on Equation 14.
+
0.4V
ROFS
In order to ensure the smooth transition of output voltage
during a VR10 or VR11 VID change, a VID step change
smoothing network is required. This network is composed of
an internal 1k resistor between the DAC and the REF pin,
and the external capacitor CREF, between the REF pin and
ground. The selection of CREF is based on the time duration
for 1-bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1-bit every TVID, the relationship between CREF and TVID is
given by Equation 14.
E/A
RFB
When in Intel VR10 or VR11 mode the ISL6312A checks the
VID inputs on the positive edge of an internal 3MHz clock. If a
new code is established and it remains stable for 3 consecutive
readings (1µs to 1.33µs), the ISL6312A recognizes the new
code and changes the internal DAC reference directly to the
new level. The Intel processor controls the VID transitions and
is responsible for incrementing or decrementing one VID step
at a time. In VR10 and VR11 settings, the ISL6312A will
immediately change the internal DAC reference to the new
requested value as-soon-as the request is validated, which
means the fastest recommended rate at which a bit change can
occur once every 2µs. In cases where the reference step is too
large, the sudden change can trigger overcurrent or
overvoltage events.
When running in AMD 5-bit or 6-bit modes of operation, the
ISL6312A responds differently to a dynamic VID change when
is in Intel VR10 or VR11 mode. In the AMD modes the
ISL6312A still checks the VID inputs on the positive edge of
an internal 3MHz clock. In these modes the VID code can be
changed by more than a 1-bit step at a time. If a new code is
established and it remains stable for 3 consecutive readings
(1s to 1.33s), the ISL6312A recognizes the change and
begins slewing the DAC in 6.25mV steps at a stepping
frequency of 330kHz until the VID and DAC are equal. Thus,
the total time required for a VID change, tDVID, is dependent
only on the size of the VID change (VVID).
The time required for a ISL6312A based converter in AMD 5-bit
DAC configuration to make a 1.1V to 1.5V reference voltage
change is about 194µs, as calculated using Equation 15.
V VID
1
t DVID = --------------------------   ---------------------
3  0.00625
330  10
(EQ. 15)
FN9290.6
January 22, 2015
ISL6312A
In order to ensure the smooth transition of output voltage
during an AMD VID change, a VID step change smoothing
network is required. This network is composed of an internal
1k resistor between the DAC and the REF pin, and the
external capacitor CREF, between the REF pin and ground.
For AMD VID transitions CREF should be a 1000pF capacitor.
LGATE DETECT
User Selectable Adaptive Deadtime Control
Techniques
Once the PHASE is high, the advanced adaptive
shoot-through circuitry monitors the PHASE and UGATE
voltages during a PWM falling edge and the subsequent
UGATE turn-off. If either the UGATE falls to less than 1.75V
above the PHASE or the PHASE falls to less than +0.8V, the
LGATE is released to turn on.
The difference between the two adaptive deadtime control
techniques is the method in which they detect that the lower
MOSFET has transitioned off in order to turn on the upper
MOSFET. The state of the DRSEL pin chooses, which of the
two control techniques is active. By tying the DRSEL pin
directly to ground, the PHASE Detect Scheme is chosen,
which monitors the voltage on the PHASE pin to determine if
the lower MOSFET has transitioned off or not. Tying the
DRSEL pin to VCC though a 50k resistor selects the
LGATE Detect Scheme, which monitors the voltage on the
LGATE pin to determine if the lower MOSFET has turned off
or not. For both schemes, the method for determining
whether the upper MOSFET has transitioned off in order to
signal to turn on the lower MOSFET is the same.
PHASE DETECT
All three integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
1.6
1.4
1.2
1.0
0.8
0.6
QGATE = 100nC
0.4
50nC
0.2
If the DRSEL pin is tied directly to ground, the PHASE Detect
adaptive deadtime control technique is selected. For the
PHASE detect scheme, during turn-off of the lower MOSFET,
the PHASE voltage is monitored until it reaches a -0.3V to
+0.8V (forward/reverse inductor current). At this time the
UGATE is released to rise. An auto-zero comparator is used to
correct the rDS(ON) drop in the phase voltage preventing false
detection of the -0.3V phase level during rDS(ON) conduction
period. In the case of zero current, the UGATE is released after
35ns delay of the LGATE dropping below 0.5V. When LGATE
first begins to transition low, this quick transition can disturb the
PHASE node and cause a false trip, so there is 20ns of
blanking time once LGATE falls until PHASE is monitored.
Once the PHASE is high, the advanced adaptive
shoot-through circuitry monitors the PHASE and UGATE
voltages during a PWM falling edge and the subsequent
UGATE turn-off. If either the UGATE falls to less than 1.75V
above the PHASE or the PHASE falls to less than +0.8V, the
LGATE is released to turn-on.
22
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Internal Bootstrap Device
CBOOT_CAP (µF)
The ISL6312A integrated drivers incorporate two different
adaptive deadtime control techniques, which the user can
choose between. Both of these control techniques help to
minimize deadtime, resulting in high efficiency from the
reduced freewheeling time of the lower MOSFET body-diode
conduction, and both help to prevent the upper and lower
MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other
has turned off.
If the DRSEL pin is tied to VCC through a 50k resistor, the
LGATE Detect adaptive deadtime control technique is selected.
For the LGATE detect scheme, during turn-off of the lower
MOSFET, the LGATE voltage is monitored until it reaches
1.75V. At this time the UGATE is released to rise.
20nC
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VBOOT_CAP (V)
FIGURE 9. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 4V and its capacitance value can be
chosen from Equation 16:
Q GATE
C BOOT_CAP  -------------------------------------V BOOT_CAP
(EQ. 16)
Q G1  PVCC
Q GATE = ----------------------------------  N Q1
V GS1
where QG1 is the amount of gate charge per upper MOSFET
at VGS1 gate-source voltage and NQ1 is the number of
control MOSFETs. The VBOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive.
FN9290.6
January 22, 2015
ISL6312A
Gate Drive Voltage Versatility
The ISL6312A provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
Initialization
Prior to initialization, proper conditions must exist on the EN,
VCC, PVCC and the VID pins. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, the controller asserts
PGOOD.
ISL6312A INTERNAL CIRCUIT
EXTERNAL CIRCUIT
VCC
PVCC1
+12V
POR
CIRCUIT
ENABLE
COMPARATOR
-
SOFT-START
AND
FAULT LOGIC
Once all of these conditions are met the controller will begin
the soft-start sequence and will ramp the output voltage up
to the user designated level.
EN_PH4
-
1.21V
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met, for both Intel and
AMD modes of operation, before the ISL6312A is released
from shutdown mode to begin the soft-start and start-up
sequence:
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6312A is guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the ISL6312A will not inadvertently turn off unless the
bias voltage drops substantially (see “Electrical
Specifications” on page 7).
2. The voltage on EN must be above 0.85V. The EN input
allows for power sequencing between the controller bias
voltage and another voltage rail. The enable comparator
holds the ISL6312A in shutdown until the voltage at EN
23
For Intel VR10, VR11 and AMD 6-bit modes of operation
these are the only conditions that must be met for the
controller to immediately begin the soft-start sequence. If
running in AMD 5-bit mode of operation there is one more
condition that must be met:
1.40k
FIGURE 10. POWER SEQUENCING USING
THRESHOLD-SENSITIVE ENABLE (EN)
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4. The driver bias voltage applied at the PVCC pins must
reach the internal power-on reset (POR) rising threshold.
In order for the ISL6312A to begin operation, PVCC1 is
the only pin that is required to have a voltage applied that
exceeds POR. However, for 2- or 3-phase operation
PVCC2 and PVCC3 must also exceed the POR
threshold. Hysteresis between the rising and falling
thresholds assure that once enabled, the ISL6312A will
not inadvertently turn off unless the PVCC bias voltage
drops substantially (see “Electrical Spaecifications” on
page 7).
5. The VID code must not be 11111 in AMD 5-bit mode. This
code signals the controller that no load is present. The
controller will not allow soft-start to begin if this VID code
is present on the VID pins.
0.85V
+
3. The voltage on the EN_PH4 pin must be above 1.21V.
The EN_PH4 input allows for power sequencing between
the controller and the external driver.
10.7k
EN
+
rises above 0.85V. The enable comparator has 110mV of
hysteresis to prevent bounce.
Intel Soft-Start
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. The soft-start sequence for the Intel modes of
operation is slightly different then the AMD soft-start
sequence.
For the Intel VR10 and VR11 modes of operation, the
soft-start sequence if composed of four periods, as shown in
Figure 6 on page 20. Once the ISL6312A is released from
shutdown and soft-start begins (as described in “Enable and
Disable” on page 23), the controller will have fixed delay
period TD1. After this delay period, the VR will begin first
soft-start ramp until the output voltage reaches 1.1V VBOOT
voltage. Then, the controller will regulate the VR voltage at
1.1V for another fixed period TD3. At the end of TD3 period,
ISL6312A will read the VID signals. If the VID code is valid,
ISL6312A will initiate the second soft-start ramp until the
output voltage reaches the VID voltage plus/minus any offset
or droop voltage.
The soft-start time is the sum of the 4 periods as shown in
Equation 17.
T SS = TD1 + TD2 + TD3 + TD4
(EQ. 17)
FN9290.6
January 22, 2015
ISL6312A
V VID
1
TDB = --------------------------   ---------------------

3 0.00625
330  10
VOUT, 500mV/DIV
TD1
TD2
(EQ. 20)
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay TDC. The typical value
for TDC can range between 1.5ms and 3.0ms.
TD3 TD4
TD5
VOUT, 500mV/DIV
EN_VTT
PGOOD
TDB
TDA
500µs/DIV
FIGURE 11. SOFT-START WAVEFORMS
EN_VTT
TD1 is a fixed delay with the typical value as 1.40ms. TD3 is
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum TD3 is about 86µs.
During TD2 and TD4, ISL6312A digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor RSS from SS pin to GND. The
second soft-start ramp time TD2 and TD4 can be calculated
based on Equations 18 and 19:
1.1  R SS
TD2 = ------------------------  s 
6.25  25
(EQ. 18)
 V VID – 1.1   R SS
TD4 = ----------------------------------------------------  s 
6.25  25
(EQ. 19)
PGOOD
500µs/DIV
FIGURE 12. SOFT-START WAVEFORMS
Pre-Biased Soft-Start
The ISL6312A also has the ability to start up into a
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
For example, when VID is set to 1.5V and the RSS is set at
100k, the first soft-start ramp time TD2 will be 704µs and
the second soft-start ramp time TD4 will be 256µs.
OUTPUT PRECHARGED
BELOW DAC LEVEL
NOTE: If the SS pin is grounded, the soft-start ramp in TD2
and TD4 will be defaulted to a 6.25mV step frequency of
330kHz.
GND>
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay TD5. The typical value
for TD5 is 440µs.
GND>
VOUT (0.5V/DIV)
EN (5V/DIV)
T1 T2
AMD Soft-Start
For the AMD 5-bit and 6-bit modes of operation, the
soft-start sequence is composed of three periods, as shown
in Figure 12. At the beginning of soft-start, the VID code is
immediately obtained from the VID pins, followed by a fixed
delay period TDA. After this delay period the ISL6312A will
begin ramping the output voltage to the desired DAC level at
a fixed rate of 6.25mV per step, with a stepping frequency of
330kHz. The amount of time required to ramp the output
voltage to the final DAC voltage is referred to as TDB, and
can be calculated as shown in Equation 20.
24
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TDC
T3
FIGURE 13. SOFT-START WAVEFORMS FOR ISL6312A
BASED MULTIPHASE CONVERTER
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output to
ramp from the pre-charged level to the final level dictated by
the DAC setting. Should the output be pre-charged to a level
exceeding the DAC setting, the output drives are enabled at
the end of the soft-start period, leading to an abrupt correction
in the output voltage down to the DAC-set level.
FN9290.6
January 22, 2015
ISL6312A
Fault Monitoring and Protection
Overvoltage Protection
The ISL6312A actively monitors output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power-good indicator is provided for linking to
external system monitors. The schematic in Figure 14
outlines the interaction between the fault monitors and the
power-good signal.
The ISL6312A constantly monitors the sensed output voltage
on the VDIFF pin to detect if an overvoltage event occurs.
When the output voltage rises above the OVP trip level actions
are taken by the ISL6312A to protect the microprocessor load.
The overvoltage protection trip level changes depending on
what mode of operation the controller is in and what state the
OVPSEL and VRSEL pins are in. Tables 6 and 7 list what the
OVP trip levels are under all conditions.
125µA
-
-
OCP
OCL
+
IAVG
170µA
+
I1
REPEAT FOR
EACH CHANNEL
VDAC
VRSEL
+
+175mV,
+250mV,
+350mV
IOUT
OCP
-
OVPSEL
VOCP
SOFT-START, FAULT
AND CONTROL LOGIC
VOVP
TABLE 6. INTEL VR10 AND VR11 OVP THRESHOLDS
MODE OF
OPERATION
VSEN
+
At the inception of an overvoltage event, LGATE1, LGATE2
and LGATE3 are commanded high, PWM4 is commanded
low, and the PGOOD signal is driven low. This turns on the
all of the lower MOSFETs and pulls the output voltage below
a level that might cause damage to the load. The LGATE
outputs remain high and PWM4 remains low until VDIFF falls
100mV below the OVP threshold that tripped the overvoltage
protection circuitry. The ISL6312A will continue to protect the
load in this fashion as long as the overvoltage condition
recurs. Once an overvoltage condition ends the ISL6312A
latches off, and must be reset by toggling EN, or through
POR, before a soft-start can be reinitiated.
+
OV
PGOOD
x1
-
-
RGND
+
UV
OVPSEL PIN OPEN
OR TIED TO GND
OVPSEL PIN TIED
TO VCC
Soft-Start
(TD1 and TD2)
1.280V and
VDAC + 175mV
(higher of the two)
1.280V and
VDAC + 350mV
(higher of the two)
Soft-Start
(TD3 and TD4)
VDAC + 175mV
VDAC + 350mV
Normal Operation
VDAC + 175mV
VDAC + 350mV
VDIFF
0.60 x DAC
FIGURE 14. POWER-GOOD AND PROTECTION CIRCUITRY
MODE OF
OPERATION
Soft-Start
Power-Good Signal
The power-good pin (PGOOD) is an open-drain logic output
that signals whether or not the ISL6312A is regulating the
output voltage within the proper levels, and whether any fault
conditions exist.This pin should be tied to a +5V source
through a resistor.
During shutdown and soft-start PGOOD pulls low and
releases high after a successful soft-start and the output
voltage is operating between the undervoltage and
overvoltage limits. PGOOD transitions low when an
undervoltage, overvoltage, or overcurrent condition is
detected or when the controller is disabled by a reset from
EN, EN_PH4, POR, or one of the no-CPU VID codes. In the
event of an overvoltage or overcurrent condition, the
controller latches off and PGOOD will not return high until
after a successful soft-start. In the case of an undervoltage
event, PGOOD will return high when the output voltage
returns to within the undervoltage.
25
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TABLE 7. AMD OVP THRESHOLDS
ISL6312A INTERNAL CIRCUITRY
Normal Operation
OVPSEL PIN OPEN
OR TIED TO GND
OVPSEL PIN TIED
TO VCC
2.200V and
VDAC + 250mV
(higher of the two)
2.200V and
VDAC + 350mV
(higher of the two)
VDAC + 250mV
VDAC + 350mV
One exception that overrides the overvoltage protection
circuitry is a dynamic VID transition in AMD modes of operation.
If a new VID code is detected during normal operation, the OVP
protection circuitry is disabled from the beginning of the
dynamic VID transition, until 50µs after the internal DAC
reaches the final VID setting. This is the only time during
operation of the ISL6312A that the OVP circuitry is not active.
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6312A is designed to protect the load from any
overvoltage events that may occur. This is accomplished by
means of an internal 10k resistor tied from PHASE to
LGATE, which turns on the lower MOSFET to control the
output voltage until the overvoltage event ceases or the input
FN9290.6
January 22, 2015
ISL6312A
power supply cuts off. For complete protection, the low side
MOSFET should have a gate threshold well below the
maximum voltage rating of the load/microprocessor.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from
any more pre-POR overvoltage events.
Undervoltage Detection
The undervoltage threshold is set at 60% of the VID code.
When the output voltage (VSEN-RGND) is below the
undervoltage threshold, PGOOD gets pulled low. No other
action is taken by the controller. PGOOD will return high if
the output voltage rises above 70% of the VID code.
Open Sense Line Prevention
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL6312A is designed to prevent
the controller from regulating. This is accomplished by
means of a small 5µA pull-up current on VSEN, and a
pull-down current on RGND. If the sense lines are opened at
any time, the voltage difference between VSEN and RGND
will increase until an overvoltage event occurs, at which
point overvoltage protection activates and the controller
stops regulating. The ISL6312A will be latched off and cannot
be restarted until the controller is reset.
Overcurrent Protection
The ISL6312A takes advantage of the proportionality
between the load current and the average current, IAVG, to
detect an overcurrent condition. Two different methods of
detecting overcurrent events are available on the ISL6312A.
The first method continually compares the average sense
current with a constant 125µA OCP reference current as
shown in Figure 14. Once the average sense current
exceeds the OCP reference current, a comparator triggers
the converter to begin overcurrent protection procedures.
This first method for detecting overcurrent events limits the
minimum overcurrent trip threshold because of the fact the
ISL6312A uses set internal RISEN current sense resistors.
For this first method the minimum overcurrent trip threshold
is dictated by the DCR of the inductors and the number of
active channels. To calculate the minimum overcurrent trip
level, IOCP,(min), use Equation 21, where N is the number of
active channels, DCR is the individual inductor’s DCR, and
RISEN is the 300 internal current sense resistor.
–6
 125  10  R ISEN  N  R 1 + R 2
I OCP =  ----------------------------------------------------------   ---------------------
DCR

  R2 
I OCP  I OCP  min 
If an overcurrent trip level lower then IOCP,(min) is desired,
then a second method for setting the OCP trip level is
available.
The second method for detecting overcurrent events
continuously compares the voltage on the IOUT pin, VIOUT,
to the overcurrent protection voltage, VOCP, as shown in
Figure 14. The average channel sense current flows out the
IOUT pin and through RIOUT, creating the IOUT pin voltage
which is proportional to the output current. When the IOUT
pin voltage exceeds the VOCP voltage of 2.0V, the
overcurrent protection circuitry activates. Since the IOUT pin
voltage is proportional to the output current, the overcurrent
trip level, IOCP, can be set by selecting the proper value for
RIOUT, as shown in Equation 23.
V OCP  R ISEN  n
I OCP = ---------------------------------------------DCR  R IOUT
At the beginning of an overcurrent shutdown, the controller
turns off both upper and lower MOSFETs. The system
remains in this state for fixed period of 12ms. If the controller
is still enabled at the end of this wait period, it will attempt a
soft-start. If the fault remains, the trip-retry cycles will
continue indefinitely until either the controller is disabled or
the fault is cleared. Note that the energy delivered during
trip-retry cycling is much less than during full-load operation,
so there is no thermal hazard.
OUTPUT CURRENT, 50A/DIV
0A
OUTPUT VOLTAGE,
500mV/DIV
(EQ. 21)
If the desired overcurrent trip level is greater then the
minimum overcurrent trip level, IOCP,min, then the resistor
divider R-C circuit around the inductor shown in Figure 5
should be used to set the desired trip level.
26
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I OCP  I OCP  min   (EQ. 23)
Once the output current exceeds the overcurrent trip level,
VIOUT will exceed VOCP and a comparator will trigger the
converter to begin overcurrent protection procedures.
–6
125  10  R ISEN  N
I OCP  min  = --------------------------------------------------------DCR
(EQ. 22)
0V
3ms/DIV
FIGURE 15. OVERCURRENT BEHAVIOR IN HICCUP MODE
FN9290.6
January 22, 2015
ISL6312A
Individual Channel Overcurrent Limiting
The ISL6312A has the ability to limit the current in each
individual channel without shutting down the entire regulator.
This is accomplished by continuously comparing the sensed
currents of each channel with a constant 170µA OCL reference
current as shown in Figure 14. If a channel’s individual sensed
current exceeds this OCL limit, the UGATE signal of that
channel is immediately forced low, and the LGATE signal is
forced high. This turns off the upper MOSFET(s), turns on the
lower MOSFET(s), and stops the rise of current in that channel,
forcing the current in the channel to decrease. That channel’s
UGATE signal will not be able to return high until the sensed
channel current falls back below the 170µA reference.
2
 I L P-P    1 – d 
 I M 2
P LOW 1 = r DS  ON    -----   1 – d  + ---------------------------------------------- (EQ. 24)
12
 N
An additional term can be added to the lower MOSFET loss
equation to account for additional loss accrued during the
deadtime, when inductor current is flowing through the lower
MOSFET body diode. This term is dependent on the diode
forward voltage at IM, VD(ON), the switching frequency, fS, and
the length of dead times, td1 and td2, at the beginning and the
end of the lower MOSFET conduction interval respectively.
P
LOW 2
= V
D  ON 
f
S
I

I


M I P-P  t
M I----------  -----+  -----+ ----------– P-P  t d2
d1

2 
N
2 
N
(EQ. 25)
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and example
board layouts for all common microprocessor applications.
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination depends
heavily on the cost analysis which in turn depends on system
constraints that differ from one design to the next. Principally,
the designer will be concerned with whether components can
be mounted on both sides of the circuit board, whether
through-hole components are permitted, the total board space
available for power supply circuitry, and the maximum amount
of load current. Generally speaking, the most economical
solutions are those in which each phase handles between 25A
and 30A. All surface mount designs will tend toward the lower
end of this current range. If through hole MOSFETs and
inductors can be used, higher per-phase currents are possible.
In cases where board space is the limiting constraint, current
can be pushed as high as 40A per phase, but these designs
require heat sinks and forced air to cool the MOSFETs,
inductors and heat-dissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
the capability of the MOSFETs to dissipate heat, and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for power loss in the lower MOSFET is simple,
since virtually all of the loss in the lower MOSFET is due to
current conducted through the channel resistance (rDS(ON)). In
Equation 24, IM is the maximum continuous output current,
IP-P is the peak-to-peak inductor current (see Equation 1), and
d is the duty cycle (VOUT/VIN).
27
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The total maximum power dissipated in each lower MOSFET
is approximated by the summation of PLOW,1 and PLOW,2.
UPPER MOSFET POWER CALCULATION
In addition to rDS(ON) losses, a large portion of the upper
MOSFET losses are due to currents conducted across the
input voltage (VIN) during switching. Since a substantially
higher portion of the upper MOSFET losses are dependent on
switching frequency, the power calculation is more complex.
Upper MOSFET losses can be divided into separate
components involving the upper MOSFET switching times,
the lower MOSFET body-diode reverse-recovery charge, Qrr,
and the upper MOSFET rDS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 26,
the required time for this commutation is t1 and the
approximated associated power loss is PUP,1.
I M I P-P
P UP,1  V IN   ---- N- + --------2 
t 
  ----1   f S
 2
(EQ. 26)
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t2. In Equation 27, the
approximate power loss is PUP,2.
 I M I P-P  t 2 
P UP, 2  V IN   ----- – ----------   ----   f S
2   2
N
(EQ. 27)
A third component involves the lower MOSFET
reverse-recovery charge, Qrr. Since the inductor current has
fully commutated to the upper MOSFET before the lower
MOSFET body diode can recover all of Qrr, it is conducted
through the upper MOSFET across VIN. The power
dissipated as a result is PUP,3.
P UP,3 = V IN  Q rr  f S
(EQ. 28)
FN9290.6
January 22, 2015
ISL6312A
Finally, the resistive part of the upper MOSFET is given in
Equation 29 as PUP,4:
2
2
I P-P
 I M
P UP,4  r DS  ON   d   ----- + ------------12
 N
respectively; NPHASE is the number of active phases. The
IQ*VCC product is the quiescent power of the controller
without capacitive load and is typically 75mW at 300kHz.
(EQ. 29)
PVCC
D
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 26, 27, 28 and 29. Since the power equations
depend on MOSFET parameters, choosing the correct
MOSFETs can be an iterative process involving repetitive
solutions to the loss equations for different MOSFETs and
different switching frequencies.
CGD
RHI1
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W
at room temperature. See “Layout Considerations” on
page 33 for thermal transfer improvement suggestions.
When designing the ISL6312A into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses, PQg_TOT, due to
the gate charge of MOSFETs and the integrated driver’s
internal circuitry and their corresponding average driver current
can be estimated with Equations 30 and 31, respectively.
(EQ. 30)
3
P Qg_Q1 = ---  Q G1  PVCC  F SW  N Q1  N PHASE
2
CDS
RGI1
CGS
Q1
S
FIGURE 16. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
CGD
RHI2
RLO2
LGATE
G
RG2
CDS
RGI2
CGS
Q2
S
FIGURE 17. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, PDR_UP, the lower drive path resistance,
PDR_UP, and in the boot strap diode, PBOOT. The rest of the
power will be dissipated by the external gate resistors (RG1
and RG2) and the internal gate resistors (RGI1 and RGI2) of
the MOSFETs. Figures 16 and 17 show the typical upper and
lower gate drives turn-on transition path. The total power
dissipation in the controller itself, PDR, can be roughly
estimated as:
P DR = P DR_UP + P DR_LOW + P BOOT +  I Q  VCC 
P Qg_Q2 = Q G2  PVCC  F SW  N Q2  N PHASE
(EQ. 31)
3
I DR =  ---  Q G1  N
+ Q G2  N Q2  N PHASE  F SW + I Q
2

Q1
In Equations 30 and 31, PQg_Q1 is the total upper gate drive
power loss and PQg_Q2 is the total lower gate drive power
loss; the gate charge (QG1 and QG2) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; IQ is the driver total
quiescent current with no load at both drive outputs; NQ1 and
NQ2 are the number of upper and lower MOSFETs per phase,
28
RG1
PHASE
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
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G
UGATE
RLO1
Package Power Dissipation
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q  VCC
BOOT
(EQ. 32)
P Qg_Q1
P BOOT = --------------------3
R LO1
R HI1

 P Qg_Q1
P DR_UP =  -------------------------------------- + ----------------------------------------  --------------------3
 R HI1 + R EXT1 R LO1 + R EXT1
R HI2
R LO2

 P Qg_Q2
P DR_LOW =  -------------------------------------- + ----------------------------------------  --------------------R
+
R
R
+
R
2
 HI2
EXT2
LO2
EXT2
R GI1
R EXT1 = R G1 + ------------N Q1
R GI2
R EXT2 = R G2 + ------------N Q2
FN9290.6
January 22, 2015
ISL6312A
Inductor DCR Current Sensing Component
Selection
.
The ISL6312A senses each individual channel’s inductor
current by detecting the voltage across the output inductor
DCR of that channel (As described in the “Continuous
Current Sampling” on page 13). As shown in Figure 18
illustrates, an R-C network is required to accurately sense the
inductor DCR voltage and convert this information into a
current, which is proportional to the total output current. The
time constant of this R-C network must match the time
constant of the inductor L/DCR.
VIN
I
UGATE(n)
L
L
LGATE(n)
DCR
+
VL(s)
R1
COUT
VC(s)
-
+
INDUCTOR
VOUT
-
MOSFET
DRIVER
SAMPLE
+
VC(s)
RISEN
-
-
ISEN-(n)
ISEN+(n)
*R2 is OPTIONAL
ISEN
FIGURE 18. DCR SENSING CONFIGURATION
The R-C network across the inductor also sets the
overcurrent trip threshold for the regulator. Before the R-C
components can be selected, the desired overcurrent
protection level should be chosen. The minimum overcurrent
trip threshold the controller can support is dictated by the
DCR of the inductors and the number of active channels. To
calculate the minimum overcurrent trip level, IOCP,min, use
Equation 33, where N is the number of active channels, and
DCR is the individual inductor’s DCR.
0.0375  N
I OCP min = --------------------------DCR
3. Resistor R2 should be left unpopulated.
If the desired overcurrent trip level is greater then the
minimum overcurrent trip level, IOCP,(min), then a resistor
divider R-C circuit should be used to set the desired trip
level. Follow the steps below to choose the component
values for the resistor divider R-C current sensing network:
1. Choose an arbitrary value for C1. The recommended
value is 0.1µF.
2. Plug the inductor L and DCR component values, the
value for C1 chosen in step 1, the number of active
channels N, and the desired overcurrent protection level
IOCP into Equations 35 and 36 to calculate the values for
R1 and R2.
L  I OCP
R 1 = -------------------------------------C 1  0.0375  N
I OCP  I OCP  min  (EQ. 35)
(EQ. 36)
Due to errors in the inductance or DCR it may be necessary
to adjust the value of R1 and R2 to match the time constants
correctly. The effects of time constant mismatch can be seen
in the form of droop overshoot or undershoot during the
initial load transient spike, as shown in Figure 19. Follow the
steps below to ensure the R-C and inductor L/DCR time
constants are matched accurately.
In
+
I OCP  I OCP  min  (EQ. 34)
L  I OCP
R 2 = --------------------------------------------------------------------------------C 1   I OCP  DCR – 0.0375  N 
C1
R2*
ISL6312A INTERNAL CIRCUIT
L
R 1 = ------------------------DCR  C 1
1. Capture a transient event with the oscilloscope set to
about L/DCR/2 (sec/div). For example, with L = 1µH and
DCR = 1m, set the oscilloscope to 500µs/div.
2. Record V1 and V2 as shown in Figure 19.
3. Select new values, R1,NEW and R2,NEW, for the time
constant resistors based on the original values, R1,OLD
and R2,OLD, using Equations 37 and 38.
V 1
R 1 NEW = R 1 OLD  ---------V
(EQ. 37)
V 1
R 2 NEW = R 2 OLD  ---------V
(EQ. 38)
2
2
4. Replace R1 and R2 with the new values and check to see
that the error is corrected. Repeat the procedure if
necessary.
(EQ. 33)
If the desired overcurrent trip level is equal to or less then
the minimum overcurrent trip level, follow the steps below to
choose the component values for the R-C current sensing
network:
1. Choose an arbitrary value for C1. The recommended
value is 0.1µF.
2. Plug the inductor L and DCR component values, and the
value for C1 chosen in step 1, into Equation 34 to
calculate the value for R1
29
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FN9290.6
January 22, 2015
ISL6312A
R-C sense circuit consisting of R1, R2, and C1 is being used,
use Equation 43.
600  N
R IOUT = -------------------------------DCR  I OCP
I OCP  I OCP min
(EQ. 42)
VOUT
 R 1 + R 2
600  N
R IOUT = --------------------------------   ---------------------
DCR  I OCP  R 2 
I OCP  I OCP min
(EQ. 43)
ITRAN
Compensation
V2
V1
The two opposing goals of compensating the voltage
regulator are stability and speed.
I
FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR
Loadline Regulation Resistor
For loadline regulation a copy of the internal average sense
current flows out of the FB pin across the loadline
regulation resistor, labeled RFB in Figure 6. This resistor’s
value sets the desired loadline required for the application.
The desired loadline, RLL, can be calculated by the following
Equation 39 where VDROOP is the desired droop voltage at
the full load current IFL.
V DROOP
R LL = -----------------------I FL
C2 (OPTIONAL)
RC
CC
COMP
(EQ. 39)
FB
Based on the desired loadline, the loadline regulation
resistor, RFB, can be calculated from Equation 40 or
Equation 41, depending on the R-C current sense circuitry
being employed. If a basic R-C sense circuit consisting of C1
and R1 is being used, use Equation 40. If a resistor divider
R-C sense circuit consisting of R1, R2, and C1 is being used,
use Equation 41.
R LL  N  300
R FB = --------------------------------DCR
(EQ. 40)
R LL  N  300   R 1 + R 2 
R FB = ---------------------------------------------------------------DCR  R 2
(EQ. 41)
In Equations 40 and 41, RLL is the loadline resistance; N is
the number of active channels; DCR is the DCR of the
individual output inductors; and R1 and R2 are the current
sense R-C resistors.
IOUT Pin Resistor
A copy of the average sense current flows out of the IOUT
pin, and a resistor, RIOUT, placed from this pin to ground can
be used to set the overcurrent protection trip level. Based on
the desired overcurrent trip threshold, IOCP, the IOUT pin
resistor, RIOUT, can be calculated from Equation 42 or
Equation 43, depending on the R-C current sense circuitry
being employed. If a basic R-C sense circuit consisting of C1
and R1 is being used, use Equation 42. If a resistor divider
30
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The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, RC and CC.
ISL6312A
RFB
VDIFF
FIGURE 20. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6312A CIRCUIT
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
Select a target bandwidth for the compensated system, f0.
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f0
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
FN9290.6
January 22, 2015
ISL6312A
Case 1:
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, I,
the load-current slew rate, di/dt, and the maximum allowable
output voltage deviation under transient loading, VMAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
1
-------------------------------- > f 0
2 LC
2    f 0  V P-P  L  C
R C = R FB  ---------------------------------------------------------0.66  V
IN
0.66  V IN
C C = --------------------------------------------------2    V PP  R FB  f 0
Case 2:
1
1
--------------------------------  f 0 < -----------------------------------2    C  ESR
2 LC
V P-P   2    2  f 02  L  C
R C = R FB  -----------------------------------------------------------------0.66  V
(EQ. 44)
IN
0.66  V IN
C C = -------------------------------------------------------------------------------------2
2
 2     f 0  V P-P  R FB  L  C
Case 3:
1
f 0 > ------------------------------------2    C  ESR
2    f 0  V P-P  L
R C = R FB  ---------------------------------------------0.66  V IN  ESR
0.66  V IN  ESR  C
C C = ----------------------------------------------------------------2    V P-P  R FB  f 0  L
In Equation 44, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent series resistance of
the bulk output filter capacitance; and VP-P is the
peak-to-peak sawtooth signal amplitude as described in the
“Electrical Specifications” on page 7.
Once selected, the compensation values in Equation 44
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to RC. Slowly increase the
value of RC while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
CC will not need adjustment. Keep the value of CC from
Equation 44 unless some performance issue is noted.
The optional capacitor C2, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 20).
Keep a position available for C2, and be prepared to install a
high frequency capacitor of between 22pF and 150pF in
case any leading edge jitter problem is noted.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
31
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At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by showing an
amount on Equation 45:
di
V  ESL  ----- + ESR  I
dt
(EQ. 45)
The filter capacitor must have sufficiently low ESL and ESR
so that V < VMAX.
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited high
frequency performance. Minimizing the ESL of the high
frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Interleaving” on
page 11 and Equation 2), a voltage develops across the bulk
capacitor ESR equal to IC,PP (ESR). Thus, once the output
capacitors are selected, the maximum allowable ripple
voltage, VPP(MAX), determines the lower limit on the
inductance.
V – N  V

OUT  V OUT
 IN
L  ESR  -------------------------------------------------------------------f S  V IN  V PP MAX 
(EQ. 46)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
VMAX. This places an upper limit on inductance.
Equation 47 gives the upper limit on L for the cases, when
the trailing edge of the current transient causes a greater
FN9290.6
January 22, 2015
ISL6312A
2  N  C  VO
L  ---------------------------------  V MAX –  I  ESR 
 I  2
(EQ. 47)
1.25  N  C-  V


L  ---------------------------MAX –  I  ESR    V IN – V O
 I  2
(EQ. 48)
0.3
INPUT-CAPACITOR CURRENT (IRMS/IO)
output voltage deviation than the leading edge. Equation 47
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
There are a number of variables to consider when choosing the
switching frequency, as there are considerable effects on the
upper MOSFET loss calculation. These effects are outlined in
MOSFETs, and they establish the upper limit for the switching
frequency. The lower limit is established by the requirement for
fast transient response and small output-voltage ripple. Choose
the lowest switching frequency that allows the regulator to meet
the transient-response requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, RT. Figure 21 and Equation 49
are provided to assist in selecting the correct value for RT.
R T = 10
10.61 –  1.035  log  f S   
(EQ. 49)
1000
0.1
0
100
1k
10k
SWITCHING FREQUENCY (Hz)
FIGURE 21. RT vs SWITCHING FREQUENCY
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
32
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0.4
0.6
0.8
1.0
FIGURE 22. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 4-PHASE CONVERTER
For a four-phase design, use Figure 22 to determine the
input-capacitor RMS current requirement set by the duty
cycle, maximum sustained output current (IO), and the ratio
of the peak-to-peak inductor current (IL,P-P) to IO. Select a
bulk capacitor with a ripple current rating which will minimize
the total number of input capacitors required to support the
RMS current calculated.
The voltage rating of the capacitors should also be at least
1.25x greater than the maximum input voltage. Figures 23
and 24 provide the same input RMS current information for
three-phase and two-phase designs respectively. Use the
same approach for selecting the bulk capacitor type and
number.
INPUT-CAPACITOR CURRENT (IRMS/IO)
RT (k)
10
10
0.2
DUTY CYCLE (VO/VIN)
0.3
100
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0.2
0
Switching Frequency
IL(P-P) = 0
IL(P-P) = 0.25 IO
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.25 IO
IL(P-P) = 0.75 IO
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VIN/VO)
FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 3-PHASE CONVERTER
FN9290.6
January 22, 2015
ISL6312A
Low capacitance, high frequency ceramic capacitors are
needed in addition to the input bulk capacitors to suppress
leading and falling edge voltage spikes. The spikes result from
the high current slew rate produced by the upper MOSFET
turn on and off. Select low ESL ceramic capacitors and place
one as close as possible to each upper MOSFET drain to
minimize board parasitics and maximize suppression.
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.3
0.2
0.1
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VIN/VO)
FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 2-PHASE CONVERTER
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit
and lead to device overvoltage stress. Careful component
selection, layout, and placement minimizes these voltage
spikes. Consider, as an example, the turn off transition of the
upper PWM MOSFET. Prior to turnoff, the upper MOSFET
was carrying channel current. During the turn off, current
stops flowing in the upper MOSFET and is picked up by the
lower MOSFET. Any inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes.
There are two sets of critical components in a DC/DC
converter using a ISL6312A controller. The power
components are the most critical because they switch large
amounts of energy. Next are small signal components that
connect to sensitive nodes or supply critical bypassing
current and signal coupling.
The power components should be placed first, which include
the MOSFETs, input and output capacitors, and the inductors. It
is important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each.
Symmetrical layout allows heat to be dissipated equally
33
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across all power trains. Equidistant placement of the controller
to the first three power trains it controls through the integrated
drivers helps keep the gate drive traces equally short,
resulting in equal trace impedances and similar drive
capability of all sets of MOSFETs.
When placing the MOSFETs try to keep the source of the
upper FETs and the drain of the lower FETs as-close-as
thermally possible. Input Bulk capacitors should be placed
close to the drain of the upper FETs and the source of the lower
FETs. Locate the output inductors and output capacitors
between the MOSFETs and the load. The high frequency input
and output decoupling capacitors (ceramic) should be placed
as close as practicable to the decoupling target, making use of
the shortest connection paths to any internal planes, such as
vias to GND next or on the capacitor solder pad.
The critical small components include the bypass capacitors
for VCC and PVCC, and many of the components
surrounding the controller including the feedback network
and current sense components. Locate the VCC/PVCC
bypass capacitors as close to the ISL6312A as possible. It is
especially important to locate the components associated
with the feedback circuit close to their respective controller
pins, since they belong to a high-impedance circuit loop,
sensitive to EMI pick-up.
A multi-layer printed circuit board is recommended. A shows
the connections of the critical components for the converter.
Note that capacitors CxxIN and CxxOUT could each represent
numerous physical capacitors. Dedicate one solid layer, usually
the one underneath the component side of the board, for a
ground plane and make all critical component ground
connections with vias to this layer.
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. Keep the
metal runs from the PHASE terminal to output inductors short.
The power plane should support the input power and output
power nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring.
Routing UGATE, LGATE, and PHASE Traces
Great attention should be paid to routing the UGATE, LGATE,
and PHASE traces since they drive the power train MOSFETs
using short, high current pulses. It is important to size them as
large and as short as possible to reduce their overall
impedance and inductance. They should be sized to carry at
least one ampere of current (0.02” to 0.05”). Going between
layers with vias should also be avoided, but if so, use two vias
for interconnection when possible.
Extra care should be given to the LGATE traces in particular
since keeping their impedance and inductance low helps to
significantly reduce the possibility of shoot-through. It is also
important to route each channels UGATE and PHASE traces
in as close proximity as possible to reduce their inductances.
FN9290.6
January 22, 2015
ISL6312A
C2
RFB
LOCATE CLOSE TO IC
(MINIMIZE CONNECTION PATH)
C1
R1
KEY
HEAVY TRACE ON CIRCUIT PLANE LAYER
ISLAND ON POWER PLANE LAYER
+12V
ISLAND ON CIRCUIT PLANE LAYER
VDIFF
FB
COMP
CBIN1
VIA CONNECTION TO GROUND PLANE
CBOOT1
VSEN
BOOT1
RGND
LOCATE NEAR SWITCHING TRANSISTORS;
(MINIMIZE CONNECTION PATH)
UGATE1
+5V
PHASE1
VCC
(CF1)
ROFS
C1
R1
C1
ISEN1ISEN1+
OFS
FS
+12V
REF
RT
R1
LGATE1
PVCC1_2
CREF
BOOT2
SS
CBIN2
(CF2)
CBOOT2
UGATE2
RSS
PHASE2
LGATE2
(CHFOUT)
CBOUT
OVPSEL
ISL6312A
LOAD
ISEN2ISEN2+
+12V
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
PVCC3
BOOT3
CBIN3
(CF2)
LOCATE NEAR LOAD;
(MINIMIZE CONNECTION
PATH)
CBOOT3
UGATE3
PHASE3
VRSEL
PGOOD
R1
LGATE3
C1
+12V
ISEN3ISEN3+
REN1
+12V
+12V
EN
CBIN4
REN2
EN_PH4
DRSEL
BOOT
VCC UGATE
PVCCPHASE
ISL6612
RDR
PWM4
IOUT
RIOUT
LGATE
PWM
R1
C1
GND
ISEN4ISEN4+
GND
FIGURE 25. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
34
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FN9290.6
January 22, 2015
ISL6312A
Current Sense Component Placement and Trace
Routing
One of the most critical aspects of the ISL6312A regulator
layout is the placement of the inductor DCR current sense
components and traces. The R-C current sense components
must be placed as close to their respective ISEN+ and
ISEN- pins on the ISL6312A as possible.
The sense traces that connect the R-C sense components to
each side of the output inductors should be routed on the
bottom of the board, away from the noisy switching
components located on the top of the board. These traces
should be routed side by side, and they should be very thin
traces. It’s important to route these traces as far away from
any other noisy traces or planes as possible. These traces
should pick up as little noise as possible.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal
GND pad of the ISL6312A to the ground plane with multiple
vias is recommended. This heat spreading allows the part to
achieve its full thermal potential. It is also recommended
that the controller be placed in a direct path of airflow if
possible to help thermally manage the part.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN9290.6
January 22, 2015
ISL6312A
Package Outline Drawing
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 4/10
4X 5.5
7.00
A
44X 0.50
B
37
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
1
7.00
36
4. 30 ± 0 . 15
12
25
(4X)
0.15
13
24
0.10 M C A B
48X 0 . 40± 0 . 1
TOP VIEW
4 0.23 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
( 6 . 80 TYP )
(
0.10 C
BASE PLANE
0 . 90 ± 0 . 1
4 . 30 )
C
SEATING PLANE
0.08 C
SIDE VIEW
( 44X 0 . 5 )
C
0 . 2 REF
5
( 48X 0 . 23 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
36
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FN9290.6
January 22, 2015
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