an1268

ISL6327EVAL5: Voltage Regulator Coupled
Inductor Solution using the ISL6327 and ISL6609
®
Application Note
October 26, 2010
AN1268.0
Author: Jason Houston
Introduction
ISL6327EVAL5 VRD Reference Design
Today’s microprocessors are continuing towards higher
power consumption and functionality. Vcore regulators have
the burden of increasing load demands coupled with tighter
voltage regulation requirements. Power designers are
challenged with the design of high performance regulators
that can meet tight load regulation windows with increasing
maximum load and transient requirements and falling output
voltages. Add to that the push for higher efficiency solutions
and decreasing PCB real estate; meeting today’s
microprocessor power requirements is no simple task.
The evaluation kit consists of the ISL6327EVAL5 evaluation
board, the ISL6327 datasheet, and this application note. The
evaluation board is designed to meet the output voltage and
current specifications shown in Table 1, with the VID DIP
switches, SW2, set to 00101010 (1.35V).
Intersil ISL6327 With Coupled Inductors
Load Line Slope
To help meet these design challenges Intersil offers a
complete reference design and evaluation package that
takes advantage of the features of the ISL6327 controller
and an output filter topology using coupled inductors and
fewer output capacitors.
Continuous Load Current
130A
Load Current Step
100A
The ISL6327 controls a microprocessor core voltage,
balances channel currents, and provides protective features
for up to 6 synchronous buck channels in parallel. The
controller uses a 8-bit DAC giving the user a digital interface
to select the output voltage, which is precisely regulated to
±0.5% accuracy using differential remote voltage sensing.
The DAC can be set up to read VR10 or VR11 VID codes.
Other features of the controller include overcurrent,
overvoltage, and undervoltage protection, internal over
temperature protection, programmable output voltage offset,
dynamic VID circuitry, and an IOUT pin that provides a
voltage proportional to the load current.
To meet the extremely fast load transients of
microprocessors the ISL6327 utilizes Intersil’s proprietary
Active Pulse Positioning (APATM) and Adaptive Phase
Alignment (APATM) modulation scheme and continuous
current sensing to achieve extremely fast load transient
response with fewer output capacitors.
‘Coupled’ with the fast control scheme a new approach to
the output filter can be implement using coupled inductors.
Coupling of two phases on one core allows the use of a
small output inductance for fast transient response without
taking the hit in efficiency due to higher individual phase
peak-to-peak current for an equivalent standard inductance.
The ISL6327 and ISL6609 datasheets along with the latest
documentation can be found on our website:
www.intersil.com.
1
TABLE 1. ISL6327EVAL5 DESIGN PARAMETERS
PARAMETER
MAX
TYPICAL
MIN
No Load VCORE Regulation
1.35V
1.33V
1.31V
VCORE Tolerance
+20mV
Load Current Transient
-20mV
1.25mΩ
1200A/μs
The board is configured for down conversion from 12V to the
DAC setting. The evaluation board provides many test
points, two types of power supply connectors, an on-board
LGA775/771 socket for transient response evaluation and
terminal connectors for DC load testing. An on-board LED is
present to indicate the status of the PGOOD signal.
The printed circuit board is implemented in 6-layer, 1-ounce
copper. The layout and stackup are designed to emulate a
real world CPU/VCORE implementation. The board
schematic and BOM is provided at the end of the application
note.
Quick Start Evaluation
The ISL6327EVAL5 is designed for quick start-up and
evaluation. All that is required is a single ATX power supply.
To begin evaluating the ISL6327EVAL5 follow the steps
below.
1. Before doing anything to the evaluation board, make sure
the “Enable” switch (EN1) is in the OFF position.
2. Using an ATX power supply, connect the 24-pin main
power supply header to the “5V Power” connector
(5V_PWR1) on the board. Next connect the 4-pin 12V
header to the “12V Power” connector (12V_PWR1) on
the board.
3. Set the “Static VID” DIP switch (SW2) to 00101010
(VID7:0 as printed on the silkscreen).Set SW1 to 0001.
4. Move the “Enable” switch (S1) to the ON position to begin
regulation.
After step 4, the ISL6327EVAL5 should be regulating the
output voltage. The test points “TPVCORE1” and “TPGND1”
can be used to monitor the output voltage initially to verify
regulation.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1268
ISL6327EVAL5 Board Features
Input Power Connections
The ISL6327EVAL5 includes two different methods for
powering up the board. The first method allows for the use of
an ATX power supply. The 24-pin header, 5V_PWR1, allows
for the connection of the main ATX power connector, while
the 4-pin header, 12V_PWR1, connects the 12V AUX power.
It is very important that both connections are secure and the
EN1 switch is in the OFF position before switching on the
ATX supply.
The second method of powering the ISL6327EVAL5 board is
with bench power supplies. Four female banana jacks are
provided for connecting bench-top supplies. A +5V, 1A and
+12V, 20A supply will be needed for full evaluation. Connect
the +5V terminal to the 5V1 jack and the +5V GND terminal
to 5V_GND1. Connect the +12V terminal to 12V1 and the
+12V GND terminal to 12V_GND1. Voltage sequencing is
not required when powering the evaluation board.
The VTT must also be powered with +5V and +12V at the
4-pin power input connector. Refer to your VTT users guide
and software for details on exact test setup and software
use.
VID Setting
The VID input on the ISL6327EVAL5 can be set by using the
on board SW2 DIP switch. The switches are labeled VID7 to
VID0. Or the VID can be controlled through the VTT
software. To select which method controls the VID pins of
the ISL6327 the jumpers J_VID7 to J_VID0 need to be
placed accordingly.
For VTT control of the VID, place the jumper hats on pins 1
and 2 of the 3-pin connector for J_VID7 - J_VID0. The 4th
switch on SW1 should also be switched to VTT (labeled on
the PCB silk-screen).
To allow the DIP switches to control the VID move switch 4
of SW1 DIP switch to DEMO and move the jumper hats to
pins 2 and 3 of J_VID7 to JVID_0.
Once power is applied to the board, the PGOOD LED
indicator will illuminate red. With EN1 in the OFF position,
the ENABLE input of the ISL6327 is held low and the startup sequence is inhibited.
The VID DIP switches should be preset to 00101010 (1.35V
with 20mV offset). If another output voltage level is desired,
refer to the ISL6327 datasheet for the complete DAC table
and change the VID switches accordingly.
Output DC Power Connections
Both VR10 and VR11 VID codes can be used with the
ISL6327EVAL5. To use VR11 move switch 1 of SW1 DIP
switch towards VR11. To use VR10 move switch 1 of SW1
towards VR10.
The ISL6327EVAL5 output can be exercised using a DC
electronic load through the output terminal lugs labeled
VCORE1 and GND1. Tie the positive load connection to
VCORE1 and the negative load connection to GND1. A
shielded scope probe test point, TP1, allows for inspection of
the output voltage, VCORE. This probe is connected to
VSENSE through 0Ω resistors on the back of the PCB
labeled VTT_R1 and VTT_R2.
LGA775/771 VTT Evaluation
To fully exercise the regulation of the ISL6327EVAL5 a
LGA775/771 VTT is needed. A LGA775/771 VTT socket is
populated on the PCB. To ensure the ISL6327 regulates to
the die sense location on the VTT, 0Ω resistors are
populated on the back side of the PCB labeled R40 and
R42. These must be populated for correct voltage
measurements when using the VTT.
After inserting the interposer and VTT in the LGA775/771
socket a differential voltage probe should be connected to
the VCC-REG-N/VSS-REG-N connector for voltage
monitoring and the AMP and GND connector for load
measurements.
Enabling the Controller
In order to enable the controller, the board must be powered
and a VID code must be set. If these steps have been
properly followed, the regulator is enabled by toggling the
“ENABLE” switch (EN1) to the ON position. When EN1 is
switched, the voltage on the EN pin of the ISL6327 will rise
above the ENLL threshold and the controller will begin the
soft start sequence. The output voltage ramps up to the
programmed VID setting, at which time the PGOOD
indicator will switch from red to green.
Signal Test Points
There are many test points available on the ISL6327EVAL5
for monitoring of key signals. Monitoring test points include,
VR_HOT and VR_RDY for monitoring the temperature
FAULT outputs, OFS, IOUT, DAC, REF, COMP, EN, and
DAC for monitoring control waveforms. There are also test
points for monitoring VIN (VIN1 and VIN2) and VOUT
(TPVCORE1 and TPGND1).
For accurate measurements with the differential probes you
must make sure that the ground terminal of your
oscilloscope is connected to the ground plane of the
ISL6327EVAL5. An easy way to do this is use a wire to
connect the GND terminal of the scope to one of the GND
test points on the ISL6327EVAL5 (TP10 for example).
2
AN1268.0
October 26, 2010
Application Note 1268
Component Selection With Coupled
Inductors
There are many parameters of the operation of the ISL6327
that can be modified and tested using the ISL6327EVAL5
evaluation board. Many control signals can also be
monitored through on-board test points. For detailed theory
of operation and component selection guidelines for the
ISL6327 please refer to the ISL6327 datasheet available on
the web at www.intersil.com.
Key parameters that will be selected differently or otherwise
impacted in the case where coupled inductors are used in
the output filter are feedback compensation, DCR sense
time constant, current sense resistor, droop control, and
overcurrent set point. How to select these components will
be covered in this section.
PWM Modulation Scheme and Continuous Current
Sense
The ISL6327 adopts Intersil's proprietary Active Pulse
Positioning (APP) modulation scheme to improve transient
performance. APP control is a unique dual-edge PWM
modulation scheme with both PWM leading and trailing
edges being independently moved to provide the best
response to transient loads. The PWM frequency, however,
is constant and set by the external resistor between the FS
pin and GND.
To further improve the transient response, the ISL6327 also
implements Intersil's proprietary Adaptive Phase Alignment
(APA) technique. APA, with sufficiently large load step
currents, can turn on all phases simultaneously.
With both APP and APA control, ISL6327 can achieve
excellent transient performance and reduce the demand on
the output capacitors.
Under steady state conditions the operation of the ISL6327
PWM modulator appears to be that of a conventional trailing
edge modulator. Conventional analysis and design methods
can therefore be used for steady state and small signal
operation.
The ISL6327 senses current continuously (no sample-andhold) on each channel for fast response to changes in
inductor current.
Continuous current sensing, APA and APP allow for very
high bandwidth response to a load transient events.
Coupled Inductor Details
To further take advantage of the control and sensing features
of the ISL6327 the use of coupled inductors in the output
filter can be implemented. Coupling 2 phases on a single
inductor core allows a reduction in phase inductance for fast
transient response without the hit in efficiency due to larger
phase ripple currents with an equivalent standard inductor.
3
With a standard single winding inductor the current
waveform is dependant on the voltage at the two terminals of
the inductor. The peak-to-peak ripple current in a
synchronous buck application is determined by Equation 1.
( V IN – V OUT ) V OUT
I PPsi = --------------------------------------------------------L fS V
IN
(EQ. 1)
where VIN is the input voltage, VOUT is the output voltage, L
is the standard inductance value, and fS is the switching
frequency.
The total output ripple current is determined by the sum of all
of the phase currents and its magnitude is reduced by the
interleaving of N number of phases.
( V IN – N V OUT ) V OUT
I TotalPPsi = ---------------------------------------------------------------L fS V
IN
(EQ. 2)
For a given Vin, Vout and fs, both the channel and total
ripple current are determined by L, the standard inductance
of each phase.
For the case where there are two inductors coupled on one
core, each providing the inductance for one phase in a
synchronous buck converter, the ripple current for a single
phase is now dependant on the voltages across both
inductors as well as the magnetic properties of the coupled
inductor.
Consider the two phase coupled inductor drawn in Figure 1.
L1
Iphase1
PHASE1
Iphase2
IOUT
VOUT
PHASE2
IOUT
IPhase2
IPhase1
PHASE2
PHASE1
FIGURE 1. TWO PHASE COUPLED INDUCTOR RIPPLE
CURRENT WAVEFORMS
Note the dot convention. If positive current flows into the dot
connected to PHASE1 then current will flow out of the dot
connected to PHASE2. This means when one PHASE has a
positive current slew rate so will the coupled PHASE. Figure 1
shows example waveforms for a simplified 2 phase case.
AN1268.0
October 26, 2010
Application Note 1268
The equation for peak-to-peak ripple current and total output
ripple current are dependent on the magnetic properties of
the coupled inductor.
With these equations it can be determined that the output
current waveform and therefore the transient response is
determined by:
The two winding coupled inductor is essentially a transformer.
Like any transformer it will have a specified winding ratio,
winding inductance (or self inductance, L), and mutual
inductance (LM). Parasitics will include leakage inductance
(LLK) and winding resistance (DCR). All these parameters
must be considered in optimizing the coupled inductor
performance for a given application.
L Tr = ( L – ( n ci – 1 )L M ) = L – L M
An equivalent circuit for the two phase coupled inductor is
shown in Figure 2. For the coupled inductor used in this
reference design the windings are symmetrical and the turns
ratio is 1:1.
N=1
This term is the leakage inductance, LLK, of the two winding
coupled inductor. The phase ripple current waveform, or
steady state phase ripple current, is determined by the
equivalent inductance in Equation 6:
2
2
( V IN – V OUT ) ⎛ L – L M ⎞
⎝
⎠
L SS = ---------------------------------------------------------------------------( V IN – V OUT )L – L M V OUT
(EQ. 6)
Equations 5 and 6 will be used when selecting components
in a two phase coupled inductor application.
Current Sensing
DCR
L - LM
DCR
L - LM
ISL6327 senses phase current continuously for fast
response. ISL6327 supports inductor DCR sensing, or
resistive sensing techniques. For more detail on the ISL6327
theory of operation please refer to the ISL6327 datasheet.
FIGURE 2. TWO PHASE COUPLED INDUCTOR
INDUCTOR DCR SENSING
Each winding has a self inductance which is the total
inductance that magnetizes the core. In an imperfect
transformer some of the flux generated by the current
through the winding will not couple through the core to the
other winding. The mutual inductance is the portion of the
winding inductance that is coupled with the other windings.
Choosing the DCR current sense circuitry is straight forward
when using standard inductors but a little more complicated
when using coupled inductors. Consider the inductor DCR
as shown in Figure 3. The channel current IL flowing through
the inductor will also pass through the DCR. A simple R-C
network across the inductor extracts the DCR voltage.
VIN
The leakage inductance is a measure of how much of the
total flux does not couple to the other winding. A system of
equations can be used to determine the phase peak-to-peak
ripple current equation and total output peak-to-peak ripple
current equation.
LM
DCR
LLK
DCR
LLK
VOUT
ISL6609
+
COUT
For the two phase coupled inductor case the phase ripple
current is shown in Equation 3:
⎛
⎞
⎜ ( V IN – V OUT )L – L M V OUT V OUT⎟
I PPci = ⎜ --------------------------------------------------------------------------- ⋅ -----------------⎟
V IN ⎟
⎜
⎛ L 2 – L 2⎞ ( f )
⎝
⎠
M ⎠ S
⎝
COUPLED INDUCTOR
IL
R
VC(s)
-
LM
(EQ. 5)
C
PWM(n)
(EQ. 3)
ISL6327 INTERNAL CIRCUIT
RISEN(n)
The total ripple current will be the sum of the phase currents
and can be calculated using Equation 4:
( V IN – N V OUT ) V OUT
I TotalPPci = ---------------------------------------------------------------( L – ( n ci – 1 )L M )f S V
IN
In
CURRENT
(EQ. 4)
Where N is the number of phases in the multiphase
converter, and nci is the number of inductors coupled on a
single core, in this case nci = 2.
ISEN-(n)
SENSE
+
-
ISEN+(n)
CT
DCR
I SEN = I ----------------LR
ISEN
FIGURE 3. DCR CURRENT SENSING
4
AN1268.0
October 26, 2010
Application Note 1268
If the R-C network components are selected such that the RC time constant (= R*C) matches the inductor time constant
(= L/DCR), the voltage across the capacitor VC is equal to
the voltage drop across the DCR, i.e., proportional to the
channel current.
transformer since the leakage inductance is typically small
compared to the self inductance.The coupled inductor in a
multiphase application will have a higher percentage of
leakage vs. self inductance so additional steps are needed
to calculate the actual leakage inductance.
With the internal low-offset current amplifier, the capacitor
voltage VC is replicated across the sense resistor RISEN.
Therefore the current out of ISEN+ pin, ISEN, is proportional
to the inductor current.
A calibrated bench RLC meter can be used for accurately
measuring leakage.
Equation 7 shows that the ratio of the channel current to the
sensed current ISEN is driven by the value of the sense
resistor and the DCR of the inductor.
DCR
I SEN = I L ⋅ ------------------R ISEN
(EQ. 7)
But how is the RC time constant selected in the coupled
inductor case? The leakage inductance of the coupled
inductor should be used as the inductance in the time
constant calculation. The leakage inductance for the two
phase coupled inductor is L - Lm.
Because of the internal filter at ISEN- pin, one capacitor CT
is needed to match the time delay between the ISEN- and
ISEN+ signals. Select the proper CT to keep the time
constant of RISEN and CT (RISEN x CT) close to 27ns.
Determining The Leakage Inductance of a Coupled
Inductor
The leakage inductance of the CI must be determined to
design and model with CI's, including using Equations 3-8.
There are several methods for accurately determining the
leakage inductance per phase of the coupled inductor; two
methods are outlined here. Figure 4 depicts an equivalent
magnetic circuit for the coupled inductor.
LLK1
RLC
METER
LLK2
2
2
L LK = L – ⎛ L – ( L ⋅ L S )⎞
⎝
⎠
(EQ. 9)
5. Repeat the above steps to obtain the winding inductance
and leakage of the secondary.
Method 2
1. Short pins 4 and 3. The measured inductance will be the
sum of the primary and secondary leakages. In the
symmetrical, 1:1 winding ratio of the multiphase buck
coupled inductor this will be 2*LLK. The average leakage for
each winding can be determined by dividing by 2.
IN06006 Specification Using Method 1
The coupled inductor used on the evaluation board is the
IN06006. To use this inductor as an example to illustrate
method 1 above refer to the IN06006 datasheet for the
following steps:
1. The winding inductance listed in the IN06006 datasheet
shows 315nH. So, L = 315nH.
2. Shorting the secondary and measuring the primary gives
150nH. Ls = 150nH.
3. The IN06006 winding ratio is 1:1.
4. The leakage inductance of this inductor can be calculated
using Equation 9.
LM
4
2. Short circuit the secondary winding, pins 2 and 3 in
Figure 4. The measured inductance from pins 1 to 4 is the
leakage inductance of the primary plus the reflected leakage
from the secondary. Call this Ls.
4. The leakage can be calculated using Equation 9:
(EQ. 8)
1
1. Leave the secondary winding, pins 2 and 3 in Figure 4,
open circuit. The measured inductance from pins 1 to 4 is the
primary winding inductance or self inductance. Call this L.
3. For this application the turns ratio is 1:1.
An equation for selecting the resistor of the RC time constant
for a two winding coupled inductor and a given C value is
shown in Equation 8. Refer the ISL6327 datasheet for
additional component selection guidelines.:
L LK
R = ---------------------DCR ⋅ C
Method 1
3
TWO PHASE COUPLED INDUCTOR
FIGURE 4. EQUIVALENT MAGNETIC CIRCUIT OF THE
COUPLED INDUCTOR
2
L LK = 315 – ( 315 – ( 315 ⋅ 150 ) ) = 87nH
So, the leakage inductance for the IN06006 is 87nH. The
mutual inductance can be determined by Equation 5.
Lm = L - LLK = 228nH.
A conventional method for measuring leakage inductance in
a transformer is to short the secondary and measure the
inductance of the primary. This is a good approximation for a
5
AN1268.0
October 26, 2010
Application Note 1268
What Inductor Parameters Do I Use?
The 87nH leakage inductance can be used in Equation 8 to
calculate the required RC time constant match for DCR
current sensing.
As shown in Equation 5, the leakage inductance determines
the total current waveform and therefore the small signal
transient response. Use LLK as the phase inductance when
calculating the regulator feedback compensation and small
signal transient response.
For steady state phase current calculations, use Equation 4.
This equation will give the peak-to-peak inductor current
waveforms for input ripple calculations, MOSFET selection,
and efficiency estimates.
The above analysis shows that a given transient inductance
can be used while reducing the phase ripple current vs. an
equivalent standard inductor.
Load-Line Regulation and Component Selection
EXTERNAL CIRCUIT
CC
RC
COMP
ISL6327 INTERNAL CIRCUIT
DAC
RREF
+
-
FB
RFB
IDROOP
+
VDROOP
VDIFF
VOUT+
IAVG
VCOMP
ERROR AMPLIFIER
VSEN
+
VOUT-
-
RGND
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 5. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION
Figure 5 shows that the average current of all active
channels, IAVG flows from FB through a load-line regulation
resistor, RFB.
(EQ. 10)
V DROOP = I AVG R FB
The regulated output voltage is reduced by the droop voltage
VDROOP. The output voltage as a function of the load current
is derived by combining Equation 10 with the sensed current
expression defined by the current sense method employed.
⎛ I OUT R X
⎞
V OUT = V REF – V OFS – ⎜ --------------- ------------------- R FB⎟
N
R
⎝
⎠
ISEN
6
Therefore, the equivalent load-line impedance (i.e., droop
impedance) is:
R FB R X
R LL = ------------- ------------------N R ISEN
(EQ. 12)
Overcurrent Protection
ISL6327 has two levels of overcurrent protection. Each
phase is protected from a sustained overcurrent condition by
limiting its peak current, while the combined phase currents
are protected on an instantaneous basis.
In instantaneous protection mode, the ISL6327 utilizes the
sensed average current IAVG to detect an overcurrent
condition. The average current magnitude can be
approximated using Equation 7, the sensed current signal
for an individual phase. The average current is continuously
compared with a constant 85µA. Once the average current
exceeds the reference current, a comparator triggers the
converter to shut-down.
For details on how the ISL6327 behaves in reaction to an
overcurrent event refer to the ISL6327 datasheet.
REF
CREF
Where VREF is the reference voltage, VOFS is the
programmed offset voltage, IOUT is the total output current of
the converter, RISEN is the sense resistor connected to the
ISEN+ pin, RFB is the feedback resistor, N is the number of
active channels, and RX is the DCR, or sense resistor,
depending on the sensing method.
For the individual channel overcurrent protection, the
ISL6327 continuously compares the sensed current signal of
each channel with the 120µA reference current. If one
channel current exceeds the reference current, ISL6327 will
pull PWM signal of this channel to low for the rest of the
switching cycle. This PWM signal can be turned on next
cycle if the sensed channel current is less than the 120µA
reference current. The peak current limit of individual
channel will not trigger the converter to shut-down.
The overcurrent protection level for the above two OCP
modes can be adjusted by changing the value of current
sensing resistors. In addition, ISL6327 can also adjust the
average OCP threshold level by adjusting the value of the
resistor from IOUT to GND, R17 on the evaluation board. An
overcurrent response will be initiated when the voltage on
IOUT reaches 2V. Use Equation 7 to approximate the
average current value.
Equation 13 can be used to calculate the value of the resistor
RIOUT based on the desired OCP level IAVG, OCP2.
2V
R IOUT = -----------------------------------I AVG, OCP2
(EQ. 13)
(EQ. 11)
AN1268.0
October 26, 2010
Application Note 1268
Which Phases Should Be Coupled?
Figure 1 has been duplicated in Figure 6 with some changes
to the spacing of the PWMs modified to show the effect on
the ripple current waveforms.
The bold red and blue waveforms in Figure 6 show an
example of how the phase current waveforms will change if
the PWM spacing is changed. Best ripple reduction
performance is achieved when the two coupled phases are
180 degrees phase-shifted.
The ISL6327 in 6-phase mode fires phases sequentially,
PWM1, PWM2, PWM3, PWM4, PWM5, PWM6. So, for
optimal phase ripple current reduction PWM1-PWM4,
PWM2-PWM5, and PWM3-PWM6 should be coupled.
For optimal layout placement two sequential PWMs should
not be placed next to one another. So, from left to right on a
PCB, an example placement can be PWM1,PWM4,PWM2,
PWM5, PWM3, PWM6.
L1
Iphase1
PHASE1
Iphase2
IOUT
Modifying the Board For Other
Applications
As shipped, the ISL6327EVAL5 is configured for 6 phase
operation, a VR11 VID of 1.35V, and designed for operation
up to 130A with a loadline of 1.25mΩ. The coupled inductors
on board are IN06006.
The inductor footprints on the board are large enough to
accommodate the footprints of other coupled inductors for
evaluation purposes.
The following procedure can be used to modify the board for
4 phase evaluation.
Four Phase VR11 05A Configuration, LL = 1mΩ
1. Change Feedback Compensation: R4 = 2.32k, R7 = 100,
C6 = 390pF, C5 = 330pF, R5 = 9.09k, C7 = 33pF
2. Change the IOUT resistor to decrease the overcurrent set
point: R17 = 36.5k which will give IOC = 120A
3. Change the DCR sense resistors: R22, R24, R26, R28,
R30, R32 = 1.3k
VOUT
4. Move jumper hats on PWM5 and PWM6 pouts: Move hats
on JP_4P_SEL1 and JP_5P_SEL2 from pins 2 and 3 to
short pins 1 and 2. This will disable PWM5 and PWM6
PHASE2
IPhase1
5. The 6 phase board is configured with (40) 10µF ceramic
capacitors in the output filter. For 4 phases 05A configuration
add 10 to 20 additional 10µF ceramic capacitors to the
output filter. There are plenty of additional 1206 footprints
around the socket to do this.
PHASE2
6. Remove unused power stage: Remove INDUCTORS L3,
MOSFETS Q3L1, Q3U1, Q6L1, Q6U1, DRIVERSU4, and U7.
PHASE1
7. Remove R79 which is connecting PWM5 to DRIVER U6
IOUT
IPhase2
FIGURE 6. COUPLED INDUCTOR CURRENT WAVEFORMS
8. Place a 0Ω resistor on R80 to connect PWM3 to DRIVER
U6.
9. On the back of the PCB remove R84 and R85. Place 0Ω
resistors on R90 and R91.
10. Follow the Quick Start Evaluation procedure on page 1 to
power up the board.
7
AN1268.0
October 26, 2010
Application Note 1268
ISL6327EVAL5 Six Phase Performance
EN
5V/DIV
EN
5V/DIV
VR_RDY
5V/DIV
VR_RDY
5V/DIV
VCORE
0.5V/DIV
VCORE
0.5V/DIV
50µs/DIV
0.5ms/DIV
FIGURE 7. START-UP SEQUENCE
FIGURE 8. SHUT-DOWN SEQUENCE
VCORE
20mV/DIV
VCORE
20mV/DIV
5µs/DIV
5µs/DIV
FIGURE 9. NO LOAD RIPPLE ~10mV
FIGURE 10. 130A RIPPLE ~12mV
VCORE
50mV/DIV
VCORE
50mV/DIV
ILOAD
1V/DIV
ILOAD
1V/DIV
10µs/DIV
FIGURE 11. TRANSIENT RESPONSE 20A to 120A IN 1200A/µs
8
10µs/DIV
FIGURE 12. TRANSIENT RESPONSE 120A to 20A IN 1200A/µs
AN1268.0
October 26, 2010
Application Note 1268
ISL6327EVAL5 Six Phase Performance
(Continued)
1.35
90
88
1.30
86
1.25
VMAX
VOUT (V)
EFFICIENCY (%)
92
84
82
VOUT
1.20
80
VMIN
78
1.15
76
74
72
1.10
0
10
30
50
70
90
IOUT (A)
110
130
150
0
20
40
60
80
100
120
140
160
IOUT (A)
FIGURE 13. VR EFFICIENCY VIN = 12V, VID = 1.35V,
LL = 1.25mΩ, VOUT MEASURED AT INDUCTOR
FIGURE 14. VCORE LOADLINE REGULATION FROM 0A TO
150A
VCORE
0.5V/DIV
.5ms/DIV
FIGURE 15. VID-ON-THE-FLY OPERATION 0.6V to 1.55V
9
AN1268.0
October 26, 2010
Application Note 1268
ISL6327EVAL5 Four Phase Performance
EN
5V/DIV
EN
5V/DIV
VR_RDY
5V/DIV
VR_RDY
5V/DIV
VCORE
0.5V/DIV
VCORE
0.5V/DIV
50µs/DIV
0.5ms/DIV
FIGURE 16. START-UP SEQUENCE
FIGURE 17. SHUT-DOWN SEQUENCE
VCORE
20mV/DIV
VCORE
20mV/DIV
5µs/DIV
5µs/DIV
FIGURE 18. NO LOAD RIPPLE ~6mV
FIGURE 19. 130A RIPPLE ~11mV
VCORE
50mV/DIV
VCORE
50mV/DIV
ILOAD
1V/DIV
ILOAD
1V/DIV
10µs/DIV
FIGURE 20. TRANSIENT RESPONSE 35A to 100A IN 50ns
10
10µs/DIV
FIGURE 21. TRANSIENT RESPONSE 100A to 35A IN 50ns
AN1268.0
October 26, 2010
Application Note 1268
ISL6327EVAL5 Four Phase Performance
(Continued)
92
1.40
VMAX
86
84
1.35
VOUT
VOUT (V)
EFFICIENCY (%)
90
88
82
80
78
1.30
VMIN
76
74
72
1.25
0
10
20
30
40
50
60
IOUT (A)
70
80
90
100 110
FIGURE 22. VR EFFICIENCY VIN = 12V, VID = 1.4V,
LL = 1.0mΩ, VOUT MEASURED AT INDUCTOR
0
20
40
60
80
100
120
IOUT (A)
FIGURE 23. VCORE LOADLINE REGULATION FROM 0A TO
100A
Summary
References
The ISL6327EVAL5 evaluation board provides a high
performance VRD solution highlighting the ISL6327
advanced multiphase controller with the use of a coupled
inductor and low capacitance output filter.
Intersil documents are available on the web at
www.intersil.com.
[1] ISL6327 Data Sheet, Intersil Corporation, File No.
FN9276
For detailed theory of operation, component selection and
layout guidelines refer to the ISL6327 datasheet.
[2] ISL6609 Data Sheet, Intersil Corporation, File No.
FN9221
The following pages provide a board schematic and bill of
materials to support implementation of this and similar
solutions.
[3] IN06006 Coupled Inductor Datasheet ICE Components,
www.icecomponents.com
11
AN1268.0
October 26, 2010
Controller Circuit
ntroller circuit
VCC5
R22
1.21k
VCC5
R21
R34
1.5k
C12
0.1u
R24
1.21k
R8
2.2
1
ISL6327
U1
Vc5
R56
DNS
2
TP14
VR_RDY
12
21
R1
10
C8
1u
C2
DNS
C3
DNS
R2
10
VSEN
C4
DNS
R36
R53
DNS
C5
330pF
C7
33p
C9
10n
R9
1k
25
27
26
PWM3
ISEN3ISEN3+
36
34
35
PWM4
ISEN4ISEN4+
30
28
29
VDIFF
IDROOP
PWM5
ISEN5ISEN5+
24
22
23
15
FB
14
COMP
PWM6
ISEN6ISEN6+
37
39
38
13
REF
OVP
44
TP5
DAC 12
DAC
IOUT
11
10
42
R11
41.2k
PWM2
ISEN2ISEN2+
16
R5
12.1k
R10
20k
31
33
32
RGND
VSEN
0
TP18
OFS
PWM1
ISEN1ISEN1+
17
TP4
REF
Vc5
41
VR_RDY
R4
4.32k
C6
390pF
EN_VTT
18
19
0
R7
100
40
45
R35
C1
DNS
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VRSEL
EN_PWR
R12
100k
OFS
46
VR_HOT
47
TM
48
FS
43
SS
20
TCOMP
49
VR_FAN
R25
Vc5
R55
Thermistor
C14
0.1u
402
R27
402
R29
TP11
GND1
TP12
GND1
RC1
100K
R28
1.21k
ISEN4-
C17
0.1u
ISEN4+
C18
0.1u
R30
1.21k
402
ISEN5-
C19
0.1u
ISEN5+
C20
0.1u
CF5
68p
R32
1.21k
R31
402
C21
0.1u
VCC5
CF6
68p
C22
0.1u
R18
1K
TP15
VR_FAN
PWM1
VCC5
PWM2
JP_2P_SEL1
TP7
TM
1
2
R16
1K
3
TP3
IOUT
R17
C48
41.2k 100p
R54
10K
1
3
PWM4
JP_3P_SEL3
C10
DNS
PWM3
For 6phase operation
place all 4 PWM jumpers
on pins 2 and 3
jumper_3pin
2
TP16
VR_HOT
jumper_3pin
JP_4P_SEL1
TP10
GND1
ISEN3-
C15
0.1u
C16
0.1u
CF4
68p
10k
TP9
GND1
R26
1.21k
ISEN3+
CF3
68p
VCC5
RN2
6.8k
ISEN2-
C13
0.1u
ISEN2+
CF2
68p
TP13
EN
R15
1k
GND
402
1
IOC target 169A
Vc5
2
3
PWM5
jumper_3pin
JP_5P_SEL2
1
2
3
jumper_3pin
PWM6
ISEN6ISEN6+
Application Note 1268
TP6
VDIFF
1
2
3
4
5
6
7
8
9
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VTTVRSEL
RGND
VCC
R14
1k
R23
3
2
Q24
2N7002
R3
10
6
1
2
3 4
R13
10k
VCC12
VCC5
RED
4
EN1
GREEN
TP8
GND1
ISEN1-
C11
0.1u
ISEN1+
CF1
68p
CR2
VR_RDY
TP17
COMP
402
VCC12
1
3
R33
1k
AN1268.0
October 26, 2010
Output Capacitors and LGA775 VID Connections
U100
VTTVID0
AM2
VTTVID1
AL5
VTTVID2
AM3
VTTVID3
AL6
VTTVID4
AK4
AN5
AN6
VCC_DIE
AN3
VTTVID5
AL4
VTTVID6
AM5
VCC
VTTVID7
AM7
VSS
0
R40
0
VSEN
Install R40, R42 for Die
Sensing connection
RGND
VCORE
BNC1
DNS
1
2
3
AN7
Place those resistors and caps close to test point
C66
DNS
4
5
13
VTTVRSEL
R42
VSS_DIE
AN4
R_SEL2 DNS
R41
0
R74
DNS
VOUT2
Vout-
VOUT1
Vout+
R43
DNS
TP1
VCORE
VSEN
VTT_R1
Install R39, R41 for Socket
Sensing connection
0
CT1
1u
CT2
2.2n
CT3
2.2n
R39
CO1
560u
CO2
560u
CO3
560u
CO4
560u
CO5
560u
CO6
560u
CO7
560u
CO8
560u
CO9
560u
CO10
560u
CO11
560u
CO12
560u
VTT_R2
0
Those caps are for Low frequency operation only. Do not install for high frequncy operation.
CO13
100u
CO14
100u
CO15
100u
CO16
100u
CO17
100u
CO18
100u
CO19
100u
CO20
100u
CO21
100u
CO22
100u
Place those 10 caps on top side
CO23
10u
CO24
10u
CO25
10u
CO26
10u
CO27
10u
CO28
10u
CO29
10u
CO30
10u
CO31
10u
CO56
10u
CO57
10u
CO58
10u
CO59
10u
Place those 9 caps inside of CPU carvity on top side
CO32
10u
CO33
10u
CO34
10u
CO35
10u
CO36
10u
CO37
10u
CO38
10u
CO39
10u
Place those 15 caps on bottom side
1
1
VCORE1
GND1
V_CORE
GND
CO40
10u
CO50
10u
CO60
10u
CO61
10u
CO62
10u
CO63
10u
CO64
10u
CO65
10u
CO66
10u
CO67
10u
CO68
10u
CO69
10u
CO70
10u
CO71
10u
CO72
10u
CO73
10u
CO74
10u
CO75
10u
CO76
10u
CO78
10u
CO77
10u
CO80
10u
CO79
10u
Place those 25 caps on top side
CO51
10u
CO52
10u
CO53
10u
CO54
10u
CO55
10u
CO41
10u
CO42
10u
CO43
10u
\CO44
10u
CO45 CO46
10u
10u
CO47
10u
CO48
10u
CO49
10u
CO83
330u
Place those 9 caps inside CPU Carvity area on bottom side
CO81
330u
CO82
330u
Optional SP caps
For 6phase operation and 100A load step;
board is populated with 40*10uF 1206
capacitors
Intersil Corporation
Intersil RTP
Size
B
D t
Title
ISL6327 CI EVALUATION 5 BOARD
F id
J l 28 2006
Sh
t
2
f
5
Rev
A
Application Note 1268
RGND
0
VCORE
AN1268.0
October 26, 2010
Power Stage
Power Stage
VIN1
Vin+
VINF
VIN2
Vin-
Put those 2 test points close to input inductor
VCC12
L_IN1
150n
TPVCORE1
VCORE
VCC5
D
BT
2
PWM
7
C26
10u
Q1U1
HAT2168H
EN
6
VCC
5
CI_1
470u
(OSCON)
Q1L1
HAT2165H
4
9
3
1
RS1
LG
GL
GND
PWM1
1
C25
10u
C24
0.22u
U2
isl6609
PH
UG
8
RV1
0
TPGND1
GND
3.3
4
2
CS1
2200p
14
C23
1u
L1
L1 is used
for 6-phase or
4-phase mode
3
VINF
UG
PWM
6
VCC
5
0
0
Q4L1
HAT2165H
ISEN1+
R59
ISEN1-
R77
0
3.3
7
8
PWM
6
5
Q2L1
HAT2165H
4
9
3
1
RS2
LG
EN
VCC
3.3
4
2
CS2
2200p
C27
1u
L2
L2 is only used
for 6-phase
3
VINF
BT
2
PWM
C59
10u
Q5U1
HAT2168H
EN
6
VCC
5
C61
10u
R60
0
ISEN2+
R61
0
ISEN2-
LG
RS5
Q5L1
HAT2165H
4
R80
DNS
C55
0.22u
PH
UG
1
GL
GND
R79
0
U6
isl6609
7
8
IN06006
9
3
PWM3
ISEN2-
C30
10u
Q2U1
HAT2168H
PH
UG
BT
2
GL
GND
1
C29
10u
C28
0.22u
U3
isl6609
ISEN2+
R93
DNS
R84
0
3.3
CS5
2200p
B
C64
1u
ISEN5+
R85
0
ISEN5-
R90
DNS
VINF
ISEN3+
BT
2
PWM
C33
10u
Q3U1
HAT2168H
6
5
3.3
Q3L1
HAT2165H
4
9
3
1
RS3
LG
EN
VCC
4
2
CS3
2200p
L3 is only used
for 6-phase
IN06006
7
PWM
AN1268.0
October 26, 2010
GL
GND
C60
10u
Q6U1
HAT2168H
C62
10u
R62
0
ISEN3+
R63
0
ISEN3-
EN
6
VCC
5
BT
9
3
C56
0.22u
RS6
LG
2
4
1
U7
isl6609
PH
UG
8
VINF
PWM6
L3
3
C31
1u
A
ISEN3-
C34
10u
PH
UG
1
GL
GND
R89
0
C32
0.22u
U4
isl6609
7
8
R91
DNS
PWM3
Application Note 1268
VINF
C
PWM5
ISEN4-
R92
DNS
C63
1u
R82
0
ISEN4+
R78
0
CS4
2200p
PWM2
VCORE
R58
RS4
LG
R81
DNS
C57
10u
PH
EN
BT
GL
GND
2
C58
10u
Q4U1
HAT2168H
4
PWM2
1
R88
0
9
3
PWM4
U5
isl6609
7
8
IN06006
C54
0.22u
Q6L1
HAT2165H
3.3
CS6
2200p
R86
0
R87
0
ISEN6+
Intersil Co
ISEN6-
Intersil RTP
C65
1u
Size
C
Title
ISL6327 CI EVALUATION
VID Generator and Input Power Connectors
or and Input power connectors
5V
+5V
R48
10k
SW1
SW DIP-4
R49
10k
R50
10k
R51
10k
RVID0
2k
R52
10k
VR11/VR10
IPF/IA32
Repetitious/Manual
DEMO/VTT
J_VID0
jumper_3pin
1
VTTVID0
U8
PIC16F874A-PT
+5V
15
SW2
SW DIP-8
VID Code
+5V
+5V
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
8
9
10
11
14
15
16
17
38
39
40
41
2
3
4
5
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RA0
RA1
RA2
RA3
RA4
RA5
19
20
21
22
23
24
OSC1
30
25
26
27
RE0
RE1
RE2
OSC2
31
SW3
VID Load
3
4
R46
10k
7
28
VCC
VCC1
C50
0.01u
29
6
GND
GND1
2
VID1
2
VID2
2
VID3
2
VID4
2
VID5
2
VID6
2
VID7
1
VTTVID1
3
2k
J_VID2
jumper_3pin
RVID2
1
VTTVID2
TP2
TP
3
2k
STEP1
Step
J_VID3
jumper_3pin
RVID3
1
VTTVID3
3
2k
Y1
NC
NC1
NC2
NC3
12
13
33
34
MCLR
18
J_VID4
jumper_3pin
RVID4
C52
33p
1
VTTVID4
C53
33p
3
2k
J_VID5
jumper_3pin
RVID5
1
VTTVID5
3
2k
J_VID6
jumper_3pin
RVID6
1
VTTVID6
3
C51
1u
2k
J_VID7
jumper_3pin
RVID7
1
VTTVID7
3
5V1
5V
+5V
5V_GND1
VCC5
5V_PWR1
24 PIN POWER
12V1
R83
0
R44
0
R45
0
5V_6P
VCC12
12V_PWR1
2
GND
GND0
+12V
5
1
12V
+3.3V
+3.3VA
+3.3VB
+3.3VC
4
6
21
22
23
+5V
+5VA
+5VB
+5VC
+5VD PWR_OK
3
4
ATX 12V AUX POWER
C47
10u
C49
10u
9
+5VSB
10
11
+12V1A
+12V1B
14
-12V
16
PS_ON#
GND
GND0
GND1
GND2
GND3
GND4
GND5
GND6
NC
0
3
5
7
15
17
18
19
24
VTTVRSEL
R_SEL1
8
20
Intersil Corporation
Intersil RTP
25
5
1
2
12
13
25
12V_GND1
Size
B
Title
ISL6327 CI EVALUATION 5 BOAR
Application Note 1268
1
2
RC0
RC1
RC2
RC3/SCL
RC4/SDA
RC5
RC6/TX
RC7/RX
VID0
J_VID1
jumper_3pin
RVID1
32
35
36
37
42
43
44
1
2
3
4
5
6
7
8
9
1
10
R47
10k
2
3
2k
AN1268.0
October 26, 2010
Application Note 1268
Bill of Materials
QTY
REF DESIGNATOR
3
C52, C53, C7
33pF, 50V COG 0603 Cap
Various
REEL
1
C48
100pF, 50V COG 0603 Cap
Various
REEL
6
CF1, CF2, CF3, CF4, CF5, CF6
68pF, 50V X7R 0805 Cap
Various
REEL
1
C5
330pF, 50V X7R 0603 Cap
Various
BAG
1
C6
390pF 50V COG 0603 Cap
Various
BAG
4
C3, C2, CT2, CT3
2.2nF, 50V X7R 0603 Cap
NIC
NMC0603X7R222K
REEL
2
C9, C50
10nF, 50V X7R 0603 Cap
NIC
NMC0603X7R103K
REEL
12
C12, C14, C16, C18, C20, C22, C11,
C13, C15, C17, C19, C21
6
C24, C28, C32, C54, C55, C56
8
DESCRIPTION
VENDOR
0.1µF, 16V X7R 0603 Capacitor
MURATA
0.22µF, 50V Y5V 0603 Cap
MURATA
C8, C23, C27, C31, C51, C63, C64, C65 1µF, 16V X5R 0603 Cap
VENDOR P/N
PKG
BAG
GRM188F51H224Z
BAG
MURATA
GRM188R61C105K
BAG
1
CT1
1µF, 16V X7R 1206 Cap
MURATA
GRM319R71C105K
BAG
1
C49
10µF, 16V Y5V 0805 Cap
MURATA
GRM21BF51C106Z
BAG
58
CO23, CO24, CO25, CO26, CO27,
CO28, CO29, CO30, CO31, CO32,
CO33, CO34, CO35, CO36, CO37,
CO38, CO39, CO40, CO41, CO42,
CO43, CO44, CO45, CO46, CO47,
CO48, CO49, CO50, CO51, CO52,
CO53, CO54, CO55, CO56, CO57,
CO58, CO59, CO60, CO61, CO62,
CO63, CO64, CO65, CO66, CO67,
CO68, CO69, CO70, CO71, CO72,
CO73, CO74, CO75, CO76, CO77,
CO78, CO79, CO80
10µF, 6.3V X7R 1206 Capacitor
MURATA
GRM31CR70J106M
REEL
0
13
C25, C26, C29, C30, C33, C34, C57,
C58, C59, C60, C61, C62
100µF, 6.3V X5R 1210 Capacitor
MURATA
GRM31CR60J107M
REEL
10µF, 16V X5R 1206 Capacitor
MURATA
GRM31CR61C106K
BAG
470µF, 16V Sanyo OSCON
Sanyo
16SEPC470M
0 5% Resistor; 0603
Various
1
CI_1
29
R39, R41, R58, R59, R60, R61, R62,
R35, R36, R63, R75, R76, R79, R82,
VTT_R1, VTT_R2, R_SEL1, R82, R79,
R88, R89, R77, R78, R84, R85, R86,
R87, R40, R42
4
R44, R45, R83, RV1
0 5% Resistor; 1206
Various
REEL
1
R8
2.2 5% Resistor; 1206
Various
REEL
6
RS1, RS2, RS3, RS4, RS5, RS6
3.3 Resistor, 5%, 1206
Various
REEL
3
R1, R2, R3
10 5% Resistor; 0603
Various
REEL
6
RF1, RF2, RF3, RF4, RF5, RF6
12 1% Resistor; 0603
Various
REEL
6
R21, R23, R25, R27, R29, R31
402 1% Resistor; 0603
Various
REEL
1
R7
200 1% Resistor; 0603
Various
6
R9, R15, R16, R18, R33, R34
1k 1% Resistor; 0603
NIC
8
RVID0, RVID1, RVID2, RVID3, RVID4,
RVID5, RVID6, RVID7
2k 1% Resistor; 0603
Various
BAG
1
R4
4.32k 1% Resistor; 0603
Various
BAG
1.21k 1% Resistor; 0603
Various
6
R22, R24, R26, R28, R30, R32
10
R13, R43, R46, R48, R49, R50, R51,
R52, R54, R55
1
1
BAG
REEL
REEL
NRC06F1001TR
REEL
BAG
10k 1% Resistor; 0603
NIC
NRC06F1002TR
REEL
R5
12.1k 1% Resistor; 0603
NIC
NRC06F1002TR
REEL
R10
20k 1% Resistor; 0603
NIC
NRC06F2002TR
REEL
16
AN1268.0
October 26, 2010
Application Note 1268
Bill of Materials (Continued)
QTY
REF DESIGNATOR
2
R11, R17
2
R12, RC1
1
R47
1
RN2
THERM_6.8K_0805
3
L1, L2, L3
1
LIN_1
6
Q1U1, Q2U1, Q3U1, Q4U1, Q5U1,
Q6U1
6
DESCRIPTION
VENDOR
VENDOR P/N
PKG
NIC
NRC06F1003TR
REEL
100k 1% Resistor; 0603
NIC
NRC06F1003TR
REEL
10k x 8 Resistor Array
AVX
RNA4A8E103JT
REEL
Vishay
NTHS0805N02N6801
BAG
41.2k 1% Resistor; 0603
87nH/64A Coupled Inductor (0.55mΩ DCR)
ICE
IN-06006
DNS
150nH/40A Inductor (0.48mΩ DCR)
Cooper
FP4-150
REEL
Upper MOSFETs
Hitachi
HAT2168H or
RJK0305
BAG
Q1L1, Q2L1, Q3L1, Q4L1, Q5L1, Q6L1 Lower MOSFETs
Hitachi
HAT2165H or
RJK0301
BAG
Crystal 16.000 MHz HC49/US
ECS
ECS-160-20-4
BAG
1
Y1
6
U2, U3, U4, U5, U6, U7
Sync Rec Buck Drvr 5V QFN
Intersil
ISL6609CR (QFN)
TUBE
1
U1
Multiphase Buck Voltage Regulator
Intersil
ISL6327CR
BAG
1
U8
8-BIT Microchip Cntrl
Microchip
PIC16F874A-I/PT
BAG
2
CR1, CR2
4P LED 3X2.5MM SMD
Luminex
SSL-LXA3025IGC
BAG
1
Q24
N-Ch MOSFET SOT-23
Fairchild
2N7002
BAG
1
SW1
4 Pin DIP Switch
CTS
219-4LPST
TUBE
1
SW2
8 Pin DIP Switch
1
SW3
Momentary Pushbutton Switch
219-8LPST
TUBE
EVQ-QWT03W
BAG
1
EN1
ITT
GT11MSCKETR
BAG
1
5V_PWR1
24 Pin ATX Connector
Molex
39-29-9242
BAG
1
12V_PWR1
4 Pin Power Connector
Molex
39-29-9042
BAG
17
STEP1, VIN1, VIN2, VOUT1, VOUT2,
VCORE1, TP1, TP2, TP3, TP4, TP5,
TP13, TP14, TP15, TP16, TP17, TP18
Test Points
Keystone
5002
BAG
5
TP8, TP9, TP10, TP11, TP12
Test Points, Turret 0.281 Height
Keystone
1514-2
BAG
1
TP1
O'scope Probe Test Point
Tektronix
K131-4244-00
BAG
12
J_VID0, J_VID1, J_VID2, J_VID3,
J_VID4, J_VID5, J_VID6, J_VID7,
JP_4P_SEL1, JP_2P_SEL1,
JP_3P_SEL3, JP_5P_SEL2
3 Pin Header
AMP/TYCO
A26512-ND
BAG
2
5V1, 12V1
Banana Jack
Keystone
7006K
BAG
2
5V_GND1, 12V_GND1
Banana Jack
Keystone
7007K
1
BNC1
BNC connector
2
VCORE1, GND1
Terminal Lugs
5
5 on the back of the board
1
47
Toggle Switch Mini SPDT SMD
CTS
Panasonic
U100
31-5329-52RFX
BAG
Burndy
KPA8CTP
BAG
FOXCONN
LGA775
TRAY
Bumpons
CPU socket
R53, R56, C1, C6, C7, C10, R_SEL2, Not Populated List
CO1, CO2, CO3, CO4, CO5, CO6, CO7,
CO8, CO9, CO10, CO11, CO12, CO81,
CO82, CO83, R81, R80, R92, R93, R90,
R91, R43, R74, C66, CS1-6, CO13,
CO14, CO15, CO16, CO17, CO18,
CO19, CO20, CO21, CO22
DNS
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
AN1268.0
October 26, 2010
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