DATASHEET

ISL6327A
®
Data Sheet
February 17, 2009
FN6833.0
Enhanced 6-Phase PWM Controller with
8-Bit VID Code and Differential Inductor
DCR or Resistor Current Sensing
Features
The ISL6327A controls microprocessor core voltage
regulation by driving up to 6 synchronous-rectified buck
channels in parallel. Multiphase buck converter architecture
uses interleaved timing to multiply channel ripple frequency
and reduce input and output ripple currents. Lower ripple
results in fewer components, lower component cost, reduced
power dissipation, and smaller implementation area.
• Precision Multiphase Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over Life, Load, Line and
Temperature
- Adjustable Precision Reference-Voltage Offset
Microprocessor loads can generate load transients with
extremely fast edge rates. The ISL6327A utilizes Intersil’s
proprietary Active Pulse Positioning (APP) and Adaptive
Phase Alignment (APA) modulation scheme to achieve the
extremely fast transient response with fewer output
capacitors.
Today’s microprocessors require a tightly regulated output
voltage position versus load current (droop). The ISL6327A
senses the output current continuously by utilizing patented
techniques to measure the voltage across the dedicated
current sense resistor or the DCR of the output inductor.
Current sensing provides the needed signals for precision
droop, channel-current balancing, and overcurrent
protection. A programmable integrated temperature
compensation function is implemented to effectively
compensate the temperature variation of the current sense
element. The current limit function provides the overcurrent
protection for the individual phase.
A unity gain, differential amplifier is provided for remote
voltage sensing. Any potential difference between remote
and local grounds can be completely eliminated using the
remote-sense amplifier. Eliminating ground differences
improves regulation and protection accuracy. The
threshold-sensitive enable input is available to accurately
coordinate the start-up of the ISL6327A with any other
voltage rail. Dynamic-VID™ technology allows seamless
on-the-fly VID changes. The offset pin allows accurate
voltage offset settings that are independent of VID setting.
• Proprietary Active Pulse Positioning and Adaptive Phase
Alignment Modulation Scheme
• Precision Resistor or DCR Current Sensing
- Accurate Load-Line Programming, Channel-Current
Balancing, Differential Current Sense
• Microprocessor Voltage Identification Input
- Dynamic VID™ Technology
- 8-Bit VID Input with Selectable VR11 code and
Extended VR10 Code at 6.25mV Per Bit
- 0.5V to 1.600V Operation Range
• Monotonic Output Voltage Soft-start
• Thermal Monitoring
• Integrated Programmable Temperature Compensation
• Overcurrent Protection and Channel Current Limit
• Overvoltage Protection with OVP Output Indication
• 2-, 3-, 4-, 5- or 6-Phase Operation
• Adjustable Switching Frequency up to 1MHz Per Phase
• Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
• Pb-Free (RoHS Compliant)
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
ISL6327ACRZ* ISL6327A CRZ
ISL6327AIRZ*
ISL6327A IRZ
TEMP.
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
0 to +70 48 Ld 7x7 QFN L48.7x7
-40 to +85 48 Ld 7x7 QFN L48.7x7
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6327A
TM
VR_HOT
VR_FAN
VR_RDY
OVP
SS
FS
EN_VTT
EN_PWR
ISEN6-
ISEN6+
PWM6
ISL6327A
(48 LD QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
VID7
1
36
PWM3
VID6
2
35
ISEN3+
VID5
3
34
ISEN3-
VID4
4
33
ISEN1-
VID3
5
32
ISEN1+
VID2
6
31
PWM1
VID1
7
30
PWM4
VID0
8
29
ISEN4+
VRSEL
9
28
ISEN4-
OFS
10
27
ISEN2-
IOUT
11
26
ISEN2+
DAC
12
25
PWM2
2
13
14
15
16
17
18
19
20
21
22
23
24
REF
COMP
FB
IDROOP
VDIFF
RGND
VSEN
TCOMP
VCC
ISEN5-
ISEN5+
PWM5
GND
FN6833.0
February 17, 2009
ISL6327A
ISL6327A Block Diagram
VDIFF
VR_RDY
OVP
VCC
0.875V
RGND
POWER-ON
X1
VSEN
S
OVP
DRIVE
EN_VTT
RESET (POR)
R
0.875V
Q
EN_PWR
OVP
THREE-STATE
SOFT-START
AND
FAULT LOGIC
+175MV
CLOCK AND
RAMP
GENERATOR
SS
OFS
OFFSET
FS
APP AND APA
MODULATOR
PWM1
APP AND APA
MODULATOR
PWM2
APP AND APA
MODULATOR
PWM3
APP AND APA
MODULATOR
PWM4
APP AND APA
MODULATOR
PWM5
APP AND APA
MODULATOR
PWM6
REF
DAC
VRSEL
VID7
VID6
VID5
DYNAMIC
VID
D/A
VID4
VID3
VID2
E/A
VID1
VID0
CHANNEL CURRENT
BALANCE AND
CURRENT LIMIT
COMP
CHANNEL
DETECT
ISEN1+
FB
ISEN1I_TRIP
2V
OC2
OC1
1
N
ISEN2+
∑
ISEN2-
TEMPERATURE
COMPENSATION
IOUT
ISEN3+
CHANNEL
CURRENT
SENSE
I_TOT
ISEN3ISEN4+
ISEN4ISEN5+
IDROOP
THERMAL
MONITORING
TEMPERATURE
COMPENSATION
GAIN
ISEN5ISEN6+
ISEN6-
GND
3
TM
VR_FAN VR_HOT
TCOMP
FN6833.0
February 17, 2009
ISL6327A
Typical Application - 6-Phase Buck Converter with DCR Sensing and External TCOMP
+5V
VCC
BOOT
VIN
UGATE
NTC2
EXTERNAL TCOMP
COMPENSATION
NETWORK
PHASE
EN
ISL6609
DRIVER
PWM
LGATE
GND
+5V
VCC
BOOT
VIN
+5V
UGATE
PHASE
EN
FB
IDROOP
PWM
DAC
VDIFF
VSEN
GND
EN_VTT
VR_RDY
LGATE
GND
VCC
RGND
VTT
ISL6609
DRIVER
COMP REF
+5V
VCC
BOOT
ISL6327A
VID7
UGATE
PWM6
ISEN6ISEN6+
VID6
VID5
VID4
VID3
VID2
PHASE
EN
ISL6609
DRIVER
PWM
PWM4
ISEN4ISEN4+
VID1
VID0
VRSEL
OVP
LGATE
GND
PWM2
ISEN2ISEN2+
+5V
VCC
BOOT
PWM1
IOUT
VIN
VIN
µP
LOAD
UGATE
ISEN1R IOUT
EN
PWM3
ISEN3-
PWM
PWM5
ISEN5ISEN5+
VR_HOT
TM
+5V
ISL6609
DRIVER
LGATE
GND
ISEN3+
VR_FAN
PHASE
ISEN1+
+5V
VCC
BOOT
EN_PWR
TCOMP OFS FS
UGATE
SS
PHASE
EN
R OFS
RT
VIN
RSS
PWM
VIN
GND
ISL6609
DRIVER
LGATE
NTC
+5V
VCC
BOOT
VIN
UGATE
EN
PWM
PHASE
ISL6609
DRIVER
LGATE
GND
4
FN6833.0
February 17, 2009
ISL6327A
Typical Application - 6-Phase Buck Converter with DCR Sensing and Integrated TCOMP
+5V
VCC
BOOT
VIN
UGATE
PHASE
EN
ISL6609
DRIVER
PWM
LGATE
GND
+5V
VCC
BOOT
VIN
+5V
UGATE
PHASE
EN
FB
IDROOP
PWM
DAC
VDIFF
VSEN
GND
EN_VTT
VR_RDY
LGATE
GND
VCC
RGND
VTT
ISL6609
DRIVER
COMP REF
+5V
VCC
BOOT
ISL6327A
VID7
VIN
UGATE
PWM6
VID6
ISEN6ISEN6+
VID5
VID4
PWM4
ISEN4ISEN4+
VID3
VID2
VID1
VID0
VRSEL
OVP
PWM2
ISEN2ISEN2+
PHASE
EN
ISL6609
DRIVER
PWM
LGATE
GND
+5V
VCC
BOOT
PWM1
IOUT
VIN
μP
LOAD
UGATE
ISEN1R IOUT
EN
PWM3
ISEN3-
PWM
PWM5
ISEN5ISEN5+
VR_HOT
TM
+5V
LGATE
+5V
VCC
BOOT
EN_PWR
TCOMP OFS FS
UGATE
PHASE
EN
RT
VIN
SS
+5V
R OFS
ISL6609
DRIVER
GND
ISEN3+
VR_FAN
PHASE
ISEN1+
R SS
PWM
VIN
GND
ISL6609
DRIVER
LGATE
NTC
+5V
VCC
BOOT
VIN
UGATE
EN
PWM
GND
5
PHASE
ISL6609
DRIVER
LGATE
FN6833.0
February 17, 2009
ISL6327A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V
All Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to VCC + 0.3V
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)
48 Ld QFN Package. . . . . . . . . . . . . . .
32
3.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature
ISL6327ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ISL6327AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Operating Conditions: VCC = 5V, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VCC SUPPLY CURRENT
Nominal Supply
VCC = 5VDC; EN_PWR = 5VDC; RT = 100kΩ,
ISEN1 = ISEN2 = ISEN3 = ISEN4 = ISEN5 = ISEN6 = -70µA
-
18
26
mA
Shutdown Supply
VCC = 5VDC; EN_PWR = 0VDC; RT = 100kΩ
-
14
21
mA
VCC Rising
4.3
4.5
4.7
V
VCC Falling
3.7
3.9
4.2
V
0.850
0.875
0.910
V
-
130
-
mV
Falling
0.720
0.745
0.775
V
Rising
0.850
0.875
0.910
V
-
130
-
mV
0.720
0.745
0.775
V
POWER-ON RESET AND ENABLE
POR Threshold
EN_PWR Threshold
Rising
Hysteresis
EN_VTT Threshold
Hysteresis
Falling
REFERENCE VOLTAGE AND DAC
System Accuracy of ISL6327ACRZ
(VID = 1V to 1.6V), TJ = 0°C to +70°C
(Note 3)
-0.5
-
0.5
%VID
System Accuracy of ISL6327ACRZ
(VID = 0.5V to 1V), TJ = 0°C to +70°C
(Note 3)
-0.9
-
0.9
%VID
System Accuracy of ISL6327AIRZ
(VID = 1V to1.6V), TJ = -40°C to +85°C
(Note 3)
-0.6
-
0.6
%VID
System Accuracy of ISL6327AIRZ
(VID = 0.5V to 1V), TJ = -40°C to +85°C
(Note 3)
-1
-
1
%VID
-60
-40
-20
µA
VID Input Low Level
-
-
0.4
V
VID Input High Level
0.8
-
-
V
VRSEL Input Low Level
-
-
0.4
V
VRSEL Input High Level
0.8
-
-
V
-
4
7
mA
VID Pull-up
DAC Source Current
6
FN6833.0
February 17, 2009
ISL6327A
Electrical Specifications
Operating Conditions: VCC = 5V, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
-
300
µA
REF Source Current
45
50
55
µA
REF Sink Current
45
50
55
µA
Offset resistor connected to ground
380
400
420
mV
Voltage below VCC, offset resistor connected to VCC
1.55
1.60
1.65
V
RT = 100kΩ
225
250
275
kHz
0.08
-
1.0
MHz
-
1.563
-
mV/µs
0.625
-
6.25
mV/µs
-
1.25
-
V
DAC Sink Current
PIN-ADJUSTABLE OFFSET
Voltage at OFS Pin
OSCILLATORS
Accuracy of Switching Frequency Setting
Adjustment Range of Switching Frequency (Note 4)
Soft-Start Ramp Rate (Note 5)
RSS = 100kΩ
Adjustment Range of Soft-Start Ramp Rate (Note 4)
PWM GENERATOR
Sawtooth Amplitude
ERROR AMPLIFIER
Open-Loop Gain
RL = 10kΩ to ground (Note 4)
-
96
-
dB
Open-Loop Bandwidth
CL = 100pF, RL = 10kΩ to ground (Note 4)
-
80
-
MHz
Slew Rate
CL = 100pF (Note 4)
-
25
-
V/µs
Maximum Output Voltage
3.8
4.3
4.9
V
Output High Voltage @ 2mA
3.6
-
-
V
Output Low Voltage @ 2mA
-
-
1.8
V
-
20
-
MHz
REMOTE-SENSE AMPLIFIER
Bandwidth
(Note 4)
Output High Current
VSEN - RGND = 2.5V
-500
-
500
µA
Output High Current
VSEN - RGND = 0.6V
-500
-
500
µA
PWM OUTPUT
PWM Output Voltage LOW Threshold
ILOAD = ±500µA
-
-
0.5
V
PWM Output Voltage HIGH Threshold
ILOAD = ±500µA
4.3
-
-
V
57
60
63
µA
Overcurrent Trip Level for Average Current
72
85
98
µA
Peak Current Limit for Individual Channel
100
120
140
µA
Maximum Voltage at IDROOP and IOUT
Pins
1.97
2.0
2.03
V
TM Input Voltage for VR_FAN Trip
1.55
1.65
1.75
V
TM Input Voltage for VR_FAN Reset
1.85
1.95
2.05
V
TM Input Voltage for VR_HOT Trip
1.3
1.4
1.5
V
TM Input Voltage for VR_HOT Reset
1.55
1.65
1.75
V
-
-
30
µA
CURRENT SENSE AND OVERCURRENT PROTECTION
Sensed Current Tolerance
ISEN1 = ISEN2 = ISEN3 = ISEN4 = ISEN5 = ISEN6 = 60µA
THERMAL MONITORING
Leakage Current of VR_HOT
With external pull-up resistor connected to VCC
7
FN6833.0
February 17, 2009
ISL6327A
Electrical Specifications
Operating Conditions: VCC = 5V, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VR_HOT Low Voltage
With 1.25kΩ resistor pull-up to VCC, IVR_HOT = 4mA
-
-
0.4
V
Leakage Current of VR_FAN
With external pull-up resistor connected to VCC
-
-
30
µA
VR_FAN Low Voltage
With 1.25kΩ resistor pull-up to VCC, IVR_FAN = 4mA
-
-
0.4
V
VR READY AND PROTECTION MONITORS
Leakage Current of VR_RDY
With externally pull-up resistor connected to VCC
-
-
30
µA
VR_RDY Low Voltage
IVR_RDY = 4mA
-
-
0.4
V
Undervoltage Threshold
VDIFF Falling
48
50
52
%VID
VR_RDY Reset Voltage
VDIFF Rising
58
60
62
%VID
Overvoltage Protection Threshold
Before valid VID
1.250
1.275
1.300
V
150
175
200
mV
-
100
-
mV
-
-
0.4
V
After valid VID, the voltage above VID
Overvoltage Protection Reset Hysteresis
OVP Output Low Voltage
IOVP = 4mA
NOTES:
3. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.
4. Limits established by characterization and are not production tested.
5. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle.
Functional Pin Description
VCC - Supplies the power necessary to operate the chip.
The controller starts to operate when the voltage on this pin
exceeds the rising POR threshold and shuts down when the
voltage on this pin drops below the falling POR threshold.
Connect this pin directly to a +5V supply.
GND - Bias and reference ground for the IC. The bottom
metal base of ISL6327A is the GND.
EN_PWR - This pin is a threshold-sensitive enable input for
the controller. Connecting the 12V supply to EN_PWR
through an appropriate resistor divider provides a means to
synchronize power-up of the controller and the MOSFET
driver ICs. When EN_PWR is driven above 0.875V, the
ISL6327A is active depending on status of EN_VTT, the
internal POR, and pending fault states. Driving EN_PWR
below 0.745V will clear all fault states and prime the
ISL6327A to soft-start when re-enabled.
EN_VTT - This pin is another threshold-sensitive enable
input for the controller. It’s typically connected to VTT output
of VTT voltage regulator in the computer mother board.
When EN_VTT is driven above 0.875V, the ISL6327A is
active depending on status of ENLL, the internal POR, and
pending fault states. Driving EN_VTT below 0.745V will clear
all fault states and prime the ISL6327A to soft-start when reenabled.
FS - Use this pin to set up the desired switching frequency. A
resistor, placed from FS to ground will set the switching
frequency. The relationship between the value of the resistor
8
and the switching frequency will be described by an
approximate equation.
SS - Use this pin to set-up the desired start-up oscillator
frequency. A resistor, placed from SS to ground will set up
the soft-start ramp rate. The relationship between the value
of the resistor and the soft-start ramp up time will be
described by an approximate equation.
VID7, VID6, VID5, VID4, VID3, VID2, VID1 and VID0 These are the inputs to the internal DAC that generates the
reference voltage for output regulation. Connect these pins
either to open-drain outputs with or without external pull-up
resistors or to active-pull-up outputs. All VID pins have 40µA
internal pull-up current sources that diminish to zero as the
voltage rises above the logic-high level. These inputs can be
pulled up externally as high as VCC plus 0.3V.
VRSEL - VRSEL is the pin used to select the internal VID
code. When it is connected to GND, the extended VR10
code is selected. VRSEL pin has 40µA internal pull-up
current sources that diminish to zero as the voltage rises
above the logic-high level. When it’s floated or pulled to high,
VR11 code is selected. This input can be pulled up as high
as VCC plus 0.3V.
VDIFF, VSEN, and RGND - VSEN and RGND form the
precision differential remote-sense amplifier. This amplifier
converts the differential voltage of the remote output to a
single-ended voltage referenced to local ground. VDIFF is
the amplifier’s output and the input to the regulation and
protection circuitry. Connect VSEN and RGND to the sense
FN6833.0
February 17, 2009
ISL6327A
pins of the remote load. VDIFF is connected to FB through a
resistor.
FB and COMP - The inverting input and the output of the
error amplifier respectively. FB can be connected to VDIFF
through a resistor. A properly chosen resistor between
VDIFF and FB can set the load line (droop), when IDROOP
pin is tied to FB pin. The droop scale factor is set by the ratio
of the ISEN resistors and the inductor DCR or the dedicated
current sense resistor. COMP is tied back to FB through an
external R-C network to compensate the regulator.
DAC and REF - The DAC pin is the output of the precision
internal DAC reference. The REF pin is the positive input of
the Error Amp. In typical applications, a 1kΩ, 1% resistor is
used between DAC and REF to generate a precision offset
voltage. This voltage is proportional to the offset current
determined by the offset resistor from OFS to ground or
VCC. A capacitor is used between REF and ground to
smooth the voltage transition during Dynamic VID™
operations.
PWM1, PWM2, PWM3, PWM4, PWM5, PWM6 - Pulse
width modulation outputs. Connect these pins to the PWM
input pins of the Intersil driver IC. The number of active
channels is determined by the state of PWM3, PWM4,
PWM5, and PWM6. For 2-phase operation, connect PWM3
to VCC; similarly, PWM4 for 3-phase, PWM5 for 4-phase,
and PWM6 for 5-phase operation.
TABLE 1. PHASE FIRING SEQUENCE
CONFIGURATION
PHASE SEQUENCE
6-Phase
1-2-3-4-5-6
5-Phase
1-2-3-4-5
4-Phase
1-2-4-3
3-Phase
1-2-3
ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-;
ISEN4+, ISEN4-; ISEN5+, ISEN5-; ISEN6+, ISEN6- - The
ISEN+ and ISEN- pins are current sense inputs to individual
differential amplifiers. The sensed current is used for
channel current balancing, overcurrent protection, and droop
regulation. Inactive channels should have their respective
current sense inputs left open (for example, open ISEN6+
and ISEN6- for 5-phase operation).
For DCR sensing, connect each ISEN- pin to the node
between the RC sense elements. Tie the ISEN+ pin to the
other end of the sense capacitor through a resistor, RISEN.
The voltage across the sense capacitor is proportional to the
inductor current. Therefore, the sense current is proportional
to the inductor current, and scaled by the DCR of the
inductor and RISEN.
VR_RDY - VR_RDY indicates that the soft-start is completed
and the output voltage is within the regulated range around
VID setting. It is an open-drain logic output. When OCP or
9
OVP occurs, VR_RDY will be pulled to low. It will also be
pulled low if the output voltage is below the undervoltage
threshold.
OFS - The OFS pin provides a means to program a DC
offset current for generating a DC offset voltage at the REF
input. The offset current is generated via an external resistor
and precision internal voltage references. The polarity of the
offset is selected by connecting the resistor to GND or VCC.
For no offset, the OFS pin should be left unterminated.
TCOMP - Temperature compensation scaling input. The
voltage sensed on the TM pin is utilized as the temperature
input to adjust IDROOP and the overcurrent protection limit
to effectively compensate for the temperature coefficient of
the current sense element. To implement the integrated
temperature compensation, a resistor divider circuit is
needed with one resistor being connected from TCOMP to
VCC of the controller and another resistor being connected
from TCOMP to GND. Changing the ratio of the resistor
values will set the gain of the integrated thermal
compensation. When integrated temperature compensation
function is not used, connect TCOMP to GND.
OVP - The Overvoltage protection output indication pin. This
pin can be pulled to VCC and is latched when an overvoltage
condition is detected. When the OVP indication is not used,
keep this pin open.
IDROOP - IDROOP is the output pin of the sensed average
channel current, which is proportional to the load current. In
the application, which does not require loadline, leave this
pin open. In the application which requires load line, connect
this pin to FB so that the sensed average current will flow
through the resistor between FB and VDIFF to create a
voltage drop, which is proportional to the load current.
IOUT - IOUT has the same output as IDROOP with
additional OCP adjustment function. In actual application, a
resistor needs to be placed between IOUT and GND to
ensure the proper operation. The voltage at IOUT pin will be
proportional to the load current. If the voltage is higher than
2V, ISL6327A will go into the OCP mode, this means it will
shut down first and then hiccup. The additional OCP trip
level can be adjusted by changing the resistor value.
TM - TM is an input pin for VR temperature measurement.
Connect this pin through NTC thermistor to GND and a
resistor to VCC of the controller. The voltage at this pin is
reverse proportional to the VR temperature. ISL6327A
monitors the VR temperature based on the voltage at the TM
pin and the output signals at VR_HOT and VR_FAN.
VR_HOT - VR_HOT is used as an indication of high VR
temperature. It is an open-drain logic output. It will be open
when the measured VR temperature reaches a certain level.
VR_FAN - VR_FAN is an output pin with open-drain logic
output. It will be open when the measured VR temperature
reaches a certain level.
FN6833.0
February 17, 2009
ISL6327A
Operation
To understand the reduction of the ripple current amplitude in
the multiphase circuit, examine the equation representing an
individual channel’s peak-to-peak inductor current.
Multiphase Power Conversion
Microprocessor load current profiles have changed to the
point that the advantages of multiphase power conversion
are impossible to ignore. The technical challenges
associated with producing a single-phase converter which is
both cost-effective and thermally viable, have forced a
change to the cost-saving approach of multiphase. The
ISL6327A controller helps reduce the complexity of
implementation by integrating vital functions and requiring
minimal output components. The block diagrams on page 3,
page 4 and page 5 provide top level views of multiphase
power conversion using the ISL6327A controller.
( V IN – V OUT ) V OUT
I PP = ----------------------------------------------------L fS V
In Equation 1, VIN and VOUT are the input and the output
voltages respectively, L is the single-channel inductor value,
and fS is the switching frequency.
INPUT-CAPACITOR CURRENT 10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
Interleaving
The switching of each channel in a multiphase converter is
timed to be symmetrically out-of-phase with each of the
other channels. In a 3-phase converter, each channel
switches 1/3 cycle after the previous channel and 1/3 cycle
before the following channel. As a result, the three-phase
converter has a combined ripple frequency three times
greater than the ripple frequency of any one phase. In
addition, the peak-to-peak amplitude of the combined
inductor current is reduced in proportion to the number of
phases (Equations 1 and 2). The increased ripple frequency
and the lower ripple amplitude mean that the designer can
use less per-channel inductance and lower total output
capacitance for any performance specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
pulse is triggered 1/3 of a cycle after the start of the PWM
pulse of the previous phase. The DC components of the
inductor currents combine to feed the load.
(EQ. 1)
IN
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
1µs/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND
INPUT-CAPACITOR RMS CURRENT FOR
3-PHASE CONVERTER
The output capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
( V IN – N V OUT ) V OUT
I C ( P – P ) = ----------------------------------------------------------L fS V
IL1 + IL2 + IL3, 7A/DIV
(EQ. 2)
IN
IL3, 7A/DIV
PWM3, 5V/DIV
IL2, 7A/DIV
PWM2, 5V/DIV
IL1, 7A/DIV
PWM1, 5V/DIV
1µs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
10
Another benefit of interleaving is to reduce the input ripple
current. The input capacitance is determined in part by the
maximum input ripple current. Multiphase topologies can
improve the overall system cost and size by lowering the
input ripple current and allowing the designer to reduce the
cost of input capacitance. The example in Figure 2 illustrates
the input currents from a three-phase converter combining to
reduce the total input ripple current.
The converter depicted in Figure 2 delivers 36A to a 1.5V load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has
FN6833.0
February 17, 2009
ISL6327A
11.9ARMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent three-phase converter.
Figures 19, 20 and 21 in the section titled “Input Capacitor
Selection” on page 27 can be used to determine the input
capacitor RMS current based on the load current, the duty
cycle, and the number of channels. They are provided as
aids in determining the optimal input capacitor solution.
Figure 22 shows the single phase input-capacitor RMS
current for comparison.
PWM Modulation Scheme
The ISL6327A adopts Intersil's proprietary Active Pulse
Positioning (APP) modulation scheme to improve the
transient performance. APP control is a unique dual-edge
PWM modulation scheme with both PWM leading and
trailing edges being independently moved to provide the
best response to the transient loads. The PWM frequency,
however, is constant and set by the external resistor
between the FS pin and GND.
To further improve the transient response, the ISL6327A
also implements Intersil's proprietary Adaptive Phase
Alignment (APA) technique. APA, with sufficiently large load
step currents, can turn on all phases together.
With both APP and APA control, ISL6327A can achieve
excellent transient performance and reduce the demand on
the output capacitors.
Under the steady state conditions the operation of the
ISL6327A PWM modulator appears to be that of a
conventional trailing edge modulator. Conventional analysis
and design methods can therefore be used for steady state
and small signal operation.
PWM Operation
The timing of each converter is set by the number of active
channels. The default channel setting for the ISL6327A is
six. The switching cycle is defined as the time between PWM
pulse termination signals of each channel. The cycle time of
the pulse termination signal is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. The PWM signals command the MOSFET drivers to
turn on/off the channel MOSFETs.
In the default 6-phase operation, the PWM2 pulse happens
1/6 of a cycle after PWM1, the PWM3 pulse happens 1/6 of
a cycle after PWM2, the PWM4 pulse happens 1/6 of a cycle
after PWM3, the PWM5 pulse happens 1/6 of a cycle after
PWM4, and the PWM6 pulse happens 1/6 of a cycle after
PWM5.
cycle increments. Connecting the PWM4 to VCC selects
3-phase operation and the pulse times are spaced in 1/3
cycle increments. Connecting the PWM3 to VCC selects
2-phase operation and the pulse times are spaced in 1/2
cycle increments.
Switching Frequency
The switching frequency is determined by the selection of
the frequency-setting resistor, RT, which is connected from
FS pin to GND (see the figures labelled Typical Applications
on page 4 and page 5). Equation 3 is provided to assist in
selecting the correct resistor value.
10
2.5X10
R T = -------------------------- – 600
f SW
(EQ. 3)
where fSW is the switching frequency of each phase.
Current Sensing
ISL6327A senses the current continuously for fast response.
ISL6327A supports inductor DCR sensing, or resistive
sensing techniques. The associated channel current sense
amplifier uses the ISEN inputs to reproduce a signal
proportional to the inductor current, IL. The sensed current,
ISEN, is used for the current balance, the load-line
regulation, and the overcurrent protection.
The internal circuitry, shown in Figures 3 and 4, represents
one channel of an N-channel converter. This circuitry is
repeated for each channel in the converter, but may not be
active depending on the status of the PWM3, PWM4,
PWM5, and PWM6 pins, as described in “PWM Operation”
on page 11.
INDUCTOR DCR SENSING
An inductor’s winding is characteristic of a distributed
resistance as measured by the DCR (Direct Current
Resistance) parameter. Consider the inductor DCR as a
separate lumped quantity, as shown in Figure 3. The
channel current IL, flowing through the inductor, will also
pass through the DCR. Equation 4 shows the S-domain
(equivalent voltage across the inductor VL).
V L = I L ⋅ ( s ⋅ L + DCR )
(EQ. 4)
A simple RC network across the inductor extracts the DCR
voltage, as shown in Figure 3.
The voltage on the capacitor VC, can be shown to be
proportional to the channel current IL, see Equation 5.
L
⎛ s ⋅ ------------+ 1⎞ ⋅ ( DCR ⋅ I L )
⎝ DCR
⎠
V C = --------------------------------------------------------------------( s ⋅ RC + 1 )
(EQ. 5)
The ISL6327A works in 2-, 3-, 4-, 5-, or 6-phase
configuration. Connecting the PWM6 to VCC selects
5-phase operation and the pulse times are spaced in 1/5
cycle increments. Connecting the PWM5 to VCC selects
4-phase operation and the pulse times are spaced in 1/4
11
FN6833.0
February 17, 2009
ISL6327A
VIN
I (s)
L
L
ISL6609
DCR
VOUT
+
VC(s)
R
COUT
-
VL
-
+
INDUCTOR
The same capacitor CT is needed to match the time delay
between ISEN- and ISEN+ signals. Select the proper CT to
keep the time constant of RISEN and CT (RISEN x CT) close
to 27ns.
Equation 7 shows the ratio of the channel current to the
sensed current ISEN.
R SENSE
I SEN = I L ⋅ ----------------------R
C
(EQ. 7)
ISEN
PWM(n)
I
ISL6327A INTERNAL CIRCUIT
L
RISEN(n)
(PTC)
In
L
RSENSE VOUT
COUT
ISL6327A INTERNAL CIRCUIT
CURRENT
SENSE
ISEN-(n)
RISEN(n)
In
+
CURRENT
SENSE
-
ISEN+(n)
CT
ISEN-(n)
+
-
DCR
I SEN = I ----------------LR
ISEN
ISEN+(n)
R
SENSE
I SEN = I ------------------------L R
ISEN
FIGURE 3. DCR SENSING CONFIGURATION
If the RC network components are selected such that the RC
time constant (= R*C) matches the inductor time constant
(= L/DCR), the voltage across the capacitor VC is equal to
the voltage drop across the DCR, i.e., proportional to the
channel current.
With the internal low-offset current amplifier, the capacitor
voltage VC is replicated across the sense resistor RISEN.
Therefore the current out of ISEN+ pin, ISEN, is proportional
to the inductor current.
Because of the internal filter at ISEN- pin, one capacitor CT
is needed to match the time delay between the ISEN- and
ISEN+ signals. Select the proper CT to keep the time
constant of RISEN and CT (RISEN x CT) close to 27ns.
Equation 6 shows that the ratio of the channel current to the
sensed current ISEN is driven by the value of the sense
resistor and the DCR of the inductor.
DCR
I SEN = I L ⋅ -----------------R ISEN
(EQ. 6)
RESISTIVE SENSING
For accurate current sense, a dedicated current-sense
resistor RSENSE in series with each output inductor can
serve as the current sense element (see Figure 4). This
technique is more accurate, but reduces overall converter
efficiency due to the additional power loss on the current
sense element RSENSE.
12
CT
FIGURE 4. SENSE RESISTOR IN SERIES WITH INDUCTORS
The inductor DCR value will increase as the temperature
increases. Therefore the sensed current will increase as the
temperature of the current sense element increases. In order
to compensate the temperature effect on the sensed current
signal, a Positive Temperature Coefficient (PTC) resistor can
be selected for the sense resistor RISEN, or the integrated
temperature compensation function of ISL6327A should be
utilized. The integrated temperature compensation function
is described in “Temperature Compensation” on page 21.
Channel-Current Balance
The sensed current In from each active channel are summed
together and divided by the number of active channels. The
resulting average current IAVG provides a measure of the
total load current. Channel current balance is achieved by
comparing the sensed current of each channel to the
average current to make an appropriate adjustment to the
PWM duty cycle of each channel with Intersil’s patented
current-balance method.
Channel current balance is essential in achieving the
thermal advantage of multiphase operation. With good
current balance, the power loss is equally dissipated over
multiple devices and a greater area.
Voltage Regulation
The compensation network shown in Figure 5 assures that
the steady-state error in the output voltage is limited only to
the error in the reference voltage (output of the DAC) and
FN6833.0
February 17, 2009
ISL6327A
offset errors in the OFS current source, remote-sense and
error amplifiers. Intersil specifies the guaranteed tolerance of
the ISL6327A to include the combined tolerances of each of
these elements.
The output of the error amplifier, VCOMP, is compared to the
sawtooth waveforms to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET drivers and
regulate the converter output to the specified reference
voltage. The internal and external circuitries, which control the
voltage regulation, are illustrated in Figure 5.
The ISL6327A incorporates an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the local controller ground reference
point resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the
non-inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, VDIFF, is
connected to the inverting input of the error amplifier through an
external resistor.
A digital-to-analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID7
through VID0. The DAC decodes the 8-bit logic signal (VID)
into one of the discrete voltages shown in Table 3. Each VID
input offers a 45µA pull-up to an internal 2.5V source for use
with open-drain outputs. The pull-up current diminishes to
zero above the logic threshold to protect voltage-sensitive
output devices. External pull-up resistors can augment the
pull-up current sources in case the leakage into the driving
device is greater than 45µA.
EXTERNAL CIRCUIT
RC CC
COMP
Load-Line Regulation
Some microprocessor manufacturers require a precisely
controlled output resistance. This dependence of the output
voltage on the load current is often termed “droop” or “load
line” regulation. By adding a well controlled output
impedance, the output voltage can effectively be level shifted
in a direction which works to achieve the load-line regulation
required by these manufacturers.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from the fast changes of the load-current demand.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
TABLE 2. VR10 VID TABLE (WITH 6.25mV EXTENSION)
VID4
400mV
VID3
200mV
VID2
100mV
VID1
50mV
VID0
25mV
0
1
0
1
0
1
1
1.6
0
1
0
1
0
1
0
1.59375
0
1
0
1
1
0
1
1.5875
0
1
0
1
1
0
0
1.58125
0
1
0
1
1
1
1
1.575
0
1
0
1
1
1
0
1.56875
0
1
1
0
0
0
1
1.5625
0
1
1
0
0
0
0
1.55625
0
1
1
0
0
1
1
1.55
0
1
1
0
0
1
0
1.54375
0
1
1
0
1
0
1
1.5375
0
1
1
0
1
0
0
1.53125
0
1
1
0
1
1
1
1.525
0
1
1
0
1
1
0
1.51875
0
1
1
1
0
0
1
1.5125
0
1
1
1
0
0
0
1.50625
0
1
1
1
0
1
1
1.5
+
0
1
1
1
0
1
0
1.49375
-
0
1
1
1
1
0
1
1.4875
0
1
1
1
1
0
0
1.48125
0
1
1
1
1
1
1
1.475
0
1
1
1
1
1
0
1.46875
1
0
0
0
0
0
1
1.4625
1
0
0
0
0
0
0
1.45625
ISL6327A INTERNAL CIRCUIT
VID5
VID6 VOLTAGE
12.5mV 6.25mV
(V)
DAC
RREF
REF
CREF
+
-
FB
RFB
IDROOP
+
VDROOP
VDIFF
VOUT+
VOUT-
IAVG
VCOMP
ERROR AMPLIFIER
VSEN
RGND
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 5. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
13
FN6833.0
February 17, 2009
ISL6327A
TABLE 2. VR10 VID TABLE (WITH 6.25mV EXTENSION) (Continued)
VID4
400mV
VID3
200mV
VID2
100mV
VID1
50mV
VID0
25mV
VID4
400mV
VID3
200mV
VID2
100mV
VID1
50mV
VID0
25mV
1
0
0
0
0
1
1
1.45
1
1
0
1
0
1
0
1.19375
1
0
0
0
0
1
0
1.44375
1
1
0
1
1
0
1
1.1875
1
0
0
0
1
0
1
1.4375
1
1
0
1
1
0
0
1.18125
1
0
0
0
1
0
0
0
1
0
0
1.43125
1
1
0
1
1
1
1
1.175
1
1
1
1.425
1
1
0
1
1
1
0
1.16875
1
0
0
0
1
1
0
1.41875
1
1
1
0
0
0
1
1.1625
1
0
0
1
0
0
1
1.4125
1
1
1
0
0
0
0
1.15625
1
0
0
1
0
0
0
1.40625
1
1
1
0
0
1
1
1.15
1
0
0
1
0
1
1
1.4
1
1
1
0
0
1
0
1.14375
1
0
0
1
0
1
0
1.39375
1
1
1
0
1
0
1
1.1375
1
0
0
1
1
0
1
1.3875
1
1
1
0
1
0
0
1.13125
1
0
0
1
1
0
0
1.38125
1
1
1
0
1
1
1
1.125
1
0
0
1
1
1
1
1.375
1
1
1
0
1
1
0
1.11875
1
0
0
1
1
1
0
1.36875
1
1
1
1
0
0
1
1.1125
1
0
1
0
0
0
1
1.3625
1
1
1
1
0
0
0
1.10625
1
0
1
0
0
0
0
1.35625
1
1
1
1
0
1
1
1.1
1
0
1
0
0
1
1
1.35
1
1
1
1
0
1
0
1.09375
1
0
1
0
0
1
0
1.34375
1
1
1
1
1
0
1
OFF
1
0
1
0
1
0
1
1.3375
1
1
1
1
1
0
0
OFF
1
0
1
0
1
0
0
1.33125
1
1
1
1
1
1
1
OFF
1
0
1
0
1
1
1
1.325
1
1
1
1
1
1
0
OFF
1
0
1
0
1
1
0
1.31875
0
0
0
0
0
0
1
1.0875
1
0
1
1
0
0
1
1.3125
0
0
0
0
0
0
0
1.08125
1
0
1
1
0
0
0
1.30625
0
0
0
0
0
1
1
1.075
1
0
1
1
0
1
1
1.3
0
0
0
0
0
1
0
1.06875
1
0
1
1
0
1
0
1.29375
0
0
0
0
1
0
1
1.0625
1
0
1
1
1
0
1
1.2875
0
0
0
0
1
0
0
1.05625
1
0
1
1
1
0
0
1.28125
0
0
0
0
1
1
1
1.05
1
0
1
1
1
1
1
1.275
0
0
0
0
1
1
0
1.04375
1
0
1
1
1
1
0
1.26875
0
0
0
1
0
0
1
1.0375
1
1
0
0
0
0
1
1.2625
0
0
0
1
0
0
0
1.03125
1
1
0
0
0
0
0
1.25625
0
0
0
1
0
1
1
1.025
1
1
0
0
0
1
1
1.25
0
0
0
1
0
1
0
1.01875
1
1
0
0
0
1
0
1.24375
0
0
0
1
1
0
1
1.0125
1
1
0
0
1
0
1
1.2375
0
0
0
1
1
0
0
1.00625
1
1
0
0
1
0
0
1.23125
0
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1.225
0
0
0
1
1
1
0
0.99375
1
1
0
0
1
1
0
1.21875
0
0
1
0
0
0
1
0.9875
1
1
0
1
0
0
1
1.2125
0
0
1
0
0
0
0
0.98125
1
1
0
1
0
0
0
1.20625
0
0
1
0
0
1
1
0.975
1
1
0
1
0
1
1
1.2
0
0
1
0
0
1
0
0.96875
14
VID5
VID6 VOLTAGE
12.5mV 6.25mV
(V)
TABLE 2. VR10 VID TABLE (WITH 6.25mV EXTENSION) (Continued)
VID5
VID6 VOLTAGE
12.5mV 6.25mV
(V)
FN6833.0
February 17, 2009
ISL6327A
TABLE 3. VR11 VID 8-BIT (Continued)
TABLE 2. VR10 VID TABLE (WITH 6.25mV EXTENSION) (Continued)
VID4
400mV
VID3
200mV
VID2
100mV
VID1
50mV
VID0
25mV
VID5
VID6 VOLTAGE
12.5mV 6.25mV
(V)
0
0
1
0
1
0
1
0.9625
0
0
1
0
1
0
0
0.95625
0
0
1
0
1
1
1
0.95
0
0
1
0
1
1
0
0.94375
0
0
1
1
0
0
1
0.9375
0
0
1
1
0
0
0
0.93125
0
0
1
1
0
1
1
0.925
0
0
1
1
0
1
0
0.91875
0
0
1
1
1
0
1
0.9125
0
0
1
1
1
0
0
0.90625
0
0
1
1
1
1
1
0.9
0
0
1
1
1
1
0
0.89375
0
1
0
0
0
0
1
0.8875
0
1
0
0
0
0
0
0.88125
0
1
0
0
0
1
1
0.875
0
1
0
0
0
1
0
0.86875
0
1
0
0
1
0
1
0.8625
0
1
0
0
1
0
0
0.85625
0
1
0
0
1
1
1
0.85
0
1
0
0
1
1
0
0.84375
0
1
0
1
0
0
1
0
1
0
1
0
0
0
VID6
VID5
VID4
VID3
VID2
VID1
0
0
0
1
0
0
0
0
1.51250
0
0
0
1
0
0
0
1
1.50625
0
0
0
1
0
0
1
0
1.50000
0
0
0
1
0
0
1
1
1.49375
0
0
0
1
0
1
0
0
1.48750
0
0
0
1
0
1
0
1
1.48125
0
0
0
1
0
1
1
0
1.47500
0
0
0
1
0
1
1
1
1.46875
0
0
0
1
1
0
0
0
1.46250
0
0
0
1
1
0
0
1
1.45625
0
0
0
1
1
0
1
0
1.45000
0
0
0
1
1
0
1
1
1.44375
0
0
0
1
1
1
0
0
1.43750
0
0
0
1
1
1
0
1
1.43125
0
0
0
1
1
1
1
0
1.42500
0
0
0
1
1
1
1
1
1.41875
0
0
1
0
0
0
0
0
1.41250
0
0
1
0
0
0
0
1
1.40625
0
0
1
0
0
0
1
0
1.40000
0
0
1
0
0
0
1
1
1.39375
0
0
1
0
0
1
0
0
1.38750
0.8375
0
0
1
0
0
1
0
1
1.38125
0.83125
0
0
1
0
0
1
1
0
1.37500
0
0
1
0
0
1
1
1
1.36875
0
0
1
0
1
0
0
0
1.36250
0
0
1
0
1
0
0
1
1.35625
0
0
1
0
1
0
1
0
1.35000
0
0
1
0
1
0
1
1
1.34375
0
0
1
0
1
1
0
0
1.33750
0
0
1
0
1
1
0
1
1.33125
0
0
1
0
1
1
1
0
1.32500
0
0
1
0
1
1
1
1
1.31875
0
0
1
1
0
0
0
0
1.31250
0
0
1
1
0
0
0
1
1.30625
0
0
1
1
0
0
1
0
1.30000
0
0
1
1
0
0
1
1
1.29375
0
0
1
1
0
1
0
0
1.28750
0
0
1
1
0
1
0
1
1.28125
0
0
1
1
0
1
1
0
1.27500
0
0
1
1
0
1
1
1
1.26875
0
0
1
1
1
0
0
0
1.26250
0
0
1
1
1
0
0
1
1.25625
TABLE 3. VR11 VID 8-BIT
VID0 VOLTAGE
VID7
VID6
VID5
VID4
VID3
VID2
VID1
0
0
0
0
0
0
0
0
OFF
0
0
0
0
0
0
0
1
OFF
0
0
0
0
0
0
1
0
1.60000
0
0
0
0
0
0
1
1
1.59375
0
0
0
0
0
1
0
0
1.58750
0
0
0
0
0
1
0
1
1.58125
0
0
0
0
0
1
1
0
1.57500
0
0
0
0
0
1
1
1
1.56875
0
0
0
0
1
0
0
0
1.56250
0
0
0
0
1
0
0
1
1.55625
0
0
0
0
1
0
1
0
1.55000
0
0
0
0
1
0
1
1
1.54375
0
0
0
0
1
1
0
0
1.53750
0
0
0
0
1
1
0
1
1.53125
0
0
0
0
1
1
1
0
1.52500
0
0
0
0
1
1
1
1
1.51875
15
VID0 VOLTAGE
VID7
FN6833.0
February 17, 2009
ISL6327A
TABLE 3. VR11 VID 8-BIT (Continued)
TABLE 3. VR11 VID 8-BIT (Continued)
VID0 VOLTAGE
VID7
VID6
VID5
VID4
VID3
VID2
VID1
0
0
1
1
1
0
1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
1
0
0
1
1
0
1
0
0
1
0
0
1
0
VID0 VOLTAGE
VID7
VID6
VID5
VID4
VID3
VID2
VID1
1.25000
0
1
1
0
0
1
0
0
0.98750
1.24375
0
1
1
0
0
1
0
1
0.98125
0
1.23750
0
1
1
0
0
1
1
0
0.97500
0
1
1.23125
0
1
1
0
0
1
1
1
0.96875
1
1
0
1.22500
0
1
1
0
1
0
0
0
0.96250
1
1
1
1
1.21875
0
1
1
0
1
0
0
1
0.95625
0
0
0
0
0
1.21250
0
1
1
0
1
0
1
0
0.95000
0
0
0
0
1
1.20625
0
1
1
0
1
0
1
1
0.94375
0
0
0
0
1
0
1.20000
0
1
1
0
1
1
0
0
0.93750
1
0
0
0
0
1
1
1.19375
0
1
1
0
1
1
0
1
0.93125
0
1
0
0
0
1
0
0
1.18750
0
1
1
0
1
1
1
0
0.92500
0
1
0
0
0
1
0
1
1.18125
0
1
1
0
1
1
1
1
0.91875
0
1
0
0
0
1
1
0
1.17500
0
1
1
1
0
0
0
0
0.91250
0
1
0
0
0
1
1
1
1.16875
0
1
1
1
0
0
0
1
0.90625
0
1
0
0
1
0
0
0
1.16250
0
1
1
1
0
0
1
0
0.90000
0
1
0
0
1
0
0
1
1.15625
0
1
1
1
0
0
1
1
0.89375
0
1
0
0
1
0
1
0
1.15000
0
1
1
1
0
1
0
0
0.88750
0
1
0
0
1
0
1
1
1.14375
0
1
1
1
0
1
0
1
0.88125
0
1
0
0
1
1
0
0
1.13750
0
1
1
1
0
1
1
0
0.87500
0
1
0
0
1
1
0
1
1.13125
0
1
1
1
0
1
1
1
0.86875
0
1
0
0
1
1
1
0
1.12500
0
1
1
1
1
0
0
0
0.86250
0
1
0
0
1
1
1
1
1.11875
0
1
1
1
1
0
0
1
0.85625
0
1
0
1
0
0
0
0
1.11250
0
1
1
1
1
0
1
0
0.85000
0
1
0
1
0
0
0
1
1.10625
0
1
1
1
1
0
1
1
0.84375
0
1
0
1
0
0
1
0
1.10000
0
1
1
1
1
1
0
0
0.83750
0
1
0
1
0
0
1
1
1.09375
0
1
1
1
1
1
0
1
0.83125
0
1
0
1
0
1
0
0
1.08750
0
1
1
1
1
1
1
0
0.82500
0
1
0
1
0
1
0
1
1.08125
0
1
1
1
1
1
1
1
0.81875
0
1
0
1
0
1
1
0
1.07500
1
0
0
0
0
0
0
0
0.81250
0
1
0
1
0
1
1
1
1.06875
1
0
0
0
0
0
0
1
0.80625
0
1
0
1
1
0
0
0
1.06250
1
0
0
0
0
0
1
0
0.80000
0
1
0
1
1
0
0
1
1.05625
1
0
0
0
0
0
1
1
0.79375
0
1
0
1
1
0
1
0
1.05000
1
0
0
0
0
1
0
0
0.78750
0
1
0
1
1
0
1
1
1.04375
1
0
0
0
0
1
0
1
0.78125
0
1
0
1
1
1
0
0
1.03750
1
0
0
0
0
1
1
0
0.77500
0
1
0
1
1
1
0
1
1.03125
1
0
0
0
0
1
1
1
0.76875
0
1
0
1
1
1
1
0
1.02500
1
0
0
0
1
0
0
0
0.76250
0
1
0
1
1
1
1
1
1.01875
1
0
0
0
1
0
0
1
0.75625
0
1
1
0
0
0
0
0
1.01250
1
0
0
0
1
0
1
0
0.75000
0
1
1
0
0
0
0
1
1.00625
1
0
0
0
1
0
1
1
0.74375
0
1
1
0
0
0
1
0
1.00000
1
0
0
0
1
1
0
0
0.73750
0
1
1
0
0
0
1
1
0.99375
1
0
0
0
1
1
0
1
0.73125
16
FN6833.0
February 17, 2009
ISL6327A
TABLE 3. VR11 VID 8-BIT (Continued)
VID0 VOLTAGE
across RFB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined using Equation 8:
VID7
VID6
VID5
VID4
VID3
VID2
VID1
1
0
0
0
1
1
1
0
0.72500
1
0
0
0
1
1
1
1
0.71875
1
0
0
1
0
0
0
0
0.71250
1
0
0
1
0
0
0
1
0.70625
1
0
0
1
0
0
1
0
0.70000
1
0
0
1
0
0
1
1
0.69375
1
0
0
1
0
1
0
0
0.68750
1
0
0
1
0
1
0
1
0.68125
1
0
0
1
0
1
1
0
0.67500
1
0
0
1
0
1
1
1
0.66875
1
0
0
1
1
0
0
0
0.66250
1
0
0
1
1
0
0
1
0.65625
1
0
0
1
1
0
1
0
0.65000
1
0
0
1
1
0
1
1
0.64375
1
0
0
1
1
1
0
0
0.63750
1
0
0
1
1
1
0
1
0.63125
1
0
0
1
1
1
1
0
0.62500
1
0
0
1
1
1
1
1
0.61875
1
0
1
0
0
0
0
0
0.61250
Output-Voltage Offset Programming
1
0
1
0
0
0
0
1
0.60625
1
0
1
0
0
0
1
0
0.60000
1
0
1
0
0
0
1
1
0.59375
1
0
1
0
0
1
0
0
0.58750
1
0
1
0
0
1
0
1
0.58125
1
0
1
0
0
1
1
0
0.57500
1
0
1
0
0
1
1
1
0.56875
1
0
1
0
1
0
0
0
0.56250
The ISL6327A allows the designer to accurately adjust the
offset voltage. When a resistor, ROFS, is connected between
OFS to VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (IOFS) to flow into OFS. If
ROFS is connected to ground, the voltage across it is
regulated to 0.4V, and IOFS flows out of OFS. A resistor
between DAC and REF, RREF, is selected so that the
product (IOFS x ROFS) is equal to the desired offset voltage.
These functions are shown in Figure 6.
1
0
1
0
1
0
0
1
0.55625
1
0
1
0
1
0
1
0
0.55000
1
0
1
0
1
0
1
1
0.54375
1
0
1
0
1
1
0
0
0.53750
1
0
1
0
1
1
0
1
0.53125
1
0
1
0
1
1
1
0
0.52500
For Negative Offset (connect ROFS to GND):
1
0
1
0
1
1
1
1
0.51875
1
0
1
1
0
0
0
0
0.51250
0.4 × R REF
R OFS = -----------------------------V OFFSET
1
0
1
1
0
0
0
1
0.50625
1
0
1
1
0
0
1
0
0.50000
1
1
1
1
1
1
1
0
OFF
1
1
1
1
1
1
1
1
OFF
V DROOP = I AVG R FB
(EQ. 8)
The regulated output voltage is reduced by the droop voltage
VDROOP. The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed in Equation 9.
⎛ I OUT R X
⎞
- ------------------ R FB⎟
V OUT = V REF – V OFS – ⎜ -----------N
R
⎝
⎠
ISEN
(EQ. 9)
Where VREF is the reference voltage, VOFS is the
programmed offset voltage, IOUT is the total output current
of the converter, RISEN is the sense resistor connected to
the ISEN+ pin, and RFB is the feedback resistor, N is the
active channel number, and RX is the DCR, or RSENSE
depending on the sensing method.
Therefore, the equivalent loadline impedance (i.e. Droop
impedance) is equal to Equation 10:
R FB R X
-----------------R LL = -----------N R ISEN
(EQ. 10)
Once the desired output offset voltage has been determined,
use Equation 11 to set ROFS:
For Positive Offset (connect ROFS to VCC):
1.6 × R REF
R OFS = -----------------------------V OFFSET
(EQ. 11)
(EQ. 12)
Figure 5 shows a current proportional to the average current
of all active channels, IAVG, flows from FB through a loadline regulation resistor RFB. The resulting voltage drop
17
FN6833.0
February 17, 2009
ISL6327A
Enable and Disable
FB
DYNAMIC
VID D/A
DAC
RREF
E/A
REF
VCC
OR
GND
-
ROFS
1.6V
+
+
0.4V
VCC
OFS
-
ISL6327A
GND
FIGURE 6. OUTPUT VOLTAGE OFFSET PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of the normal operation. They direct the core
voltage regulator to do this by making changes to the VID
inputs during the regulator operation. The power management
solution is required to monitor the DAC inputs and respond to
on-the-fly VID changes in a controlled manner. Supervising
the safe output voltage transition within the DAC range of the
processor without discontinuity or disruption is a necessary
function of the core-voltage regulator.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of RREF and CREF, can be used. The selection of
RREF is based on the desired offset voltage as detailed in
“Output-Voltage Offset Programming” on page 17. The
selection of CREF is based on the time duration for 1 bit VID
change and the allowable delay time.
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6327A
is released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6327A is guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the ISL6327A will not inadvertently turn off unless the
bias voltage drops substantially (see “Electrical
Specifications” on page 6).
2. The ISL6327A features an enable input (EN_PWR) for
power sequencing between the controller bias voltage and
another voltage rail. The enable comparator holds the
ISL6327A in shutdown until the voltage at EN_PWR rises
above 0.875V. The enable comparator has about 130mV
of hysteresis to prevent bounce. It is important that the
driver ICs reach their POR level before the ISL6327A
becomes enabled. The schematic in Figure 7
demonstrates sequencing the ISL6327A with the ISL66xx
family of Intersil MOSFET drivers, which require 12V bias.
3. The voltage on EN_VTT must be higher than 0.875V to
enable the controller. This pin is typically connected to the
output of VTT VR.
When all conditions above are satisfied, ISL6327A begins
soft-start and ramps the VID setpoint if a valid VID code is
present. If the VID code is an OFF code, ISL6327A will shut
down, and cycling VCC, EN_PWR or EN_VTT is needed to
restart.
ISL6327A INTERNAL CIRCUIT
EXTERNAL CIRCUIT
+12V
VCC
POR
CIRCUIT
ENABLE
COMPARATOR
+
10kΩ
EN_PWR
910Ω
0.875V
Assuming the microprocessor controls the VID change at 1-bit
every TVID, the relationship between the time constant of
RREF and CREF network and TVID is given by Equation 13.
+
EN_VTT
-
(EQ. 13)
C REF R REF = T VID
0.875V
Operation Initialization
Prior to converter initialization, proper conditions must exist on
the enable inputs and VCC. When the conditions are met, the
controller begins soft-start. Once the output voltage is within
the proper window of operation, VR_RDY asserts logic high.
SOFT-START
AND
FAULT LOGIC
FIGURE 7. POWER SEQUENCING USING THRESHOLDSENSITIVE ENABLE (EN) FUNCTION
18
FN6833.0
February 17, 2009
ISL6327A
VR_RDY
UV
-
The soft-start sequence of an ISL6327A based VR is
comprised of 3 segments, as shown in Figure 8. Once VCC,
EN_VTT and EN_PWR all reach their POR/enable
thresholds, the controller initiates a fixed wait period, tD1.
Following tD1, the VR initiates the soft-start ramp, raising the
internal reference to the VID setpoint over the time interval,
tD2.
detected, or the controller is disabled by a reset from
EN_PWR, EN_VTT, POR, or VID OFF-code.
+
Soft-Start
50%
VOUT, 500mV/DIV
tD2
tD1
DAC
-
85µA
OC
+
IAVG
+
VDIFF
tD3
SOFT-START, FAULT
AND CONTROL LOGIC
OV
EN_VTT
VID + 0.175V
FIGURE 9. VR_RDY AND PROTECTION CIRCUITRY
VR_RDY
Undervoltage Detection
500µs/DIV
FIGURE 8. SOFT-START WAVEFORMS
tD1 is a fixed delay with the typical value as 1.36ms. During
tD2, ISL6327A digitally controls the DAC voltage change at
6.25mV per step. The time for each step is determined by
the frequency of the soft-start oscillator which is defined by
the resistor RSS from SS pin to GND. The soft-start ramp
time tD2 can be calculated based on Equations 14:
1.1xR SS
t D2 = ------------------------ ( μs )
6.25x25
(EQ. 14)
For example, when VID is set to 1.5V and the RSS is set at
100kΩ, the soft-start ramp time tD2 will be 704µs.
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay tD3. The
typical value for tD3 is 85µs.
Fault Monitoring and Protection
The ISL6327A actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to external
system monitors. The schematic in Figure 9 outlines the
interaction between the fault monitors and the VR_RDY signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate
that the soft-start period is completed and the output voltage
is within the regulated range. VR_RDY is pulled low during
shutdown and releases high after a successful soft-start and
a fix delay time, tD3. VR_RDY will be pulled low when an
undervoltage, overvoltage, or overcurrent condition is
19
The undervoltage threshold is set at 50% of the VID voltage.
When the output voltage at VSEN is below the undervoltage
threshold, VR_RDY gets pulled low. When the output
voltage comes back to 60% of the VID voltage, VR_RDY will
return back to high.
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6327A
overvoltage protection (OVP) circuit will be active after its
POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and before
the 2nd soft-start, the OVP threshold is 1.275V. Once the
controller detects a valid VID input, the OVP trip point will be
changed to the VID voltage plus 175mV.
Two actions are taken by the ISL6327A to protect the
microprocessor load when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs
are commanded low instantly (less than 20ns). This causes
the Intersil drivers to turn on the lower MOSFETs and pull
the output voltage below a level to avoid damaging the load.
When the VDIFF voltage falls below the DAC plus 75mV,
PWM signals enter a high-impedance state. The Intersil
drivers respond to the high-impedance input by turning off
both upper and lower MOSFETs. If the overvoltage condition
reoccurs, the ISL6327A will again command the lower
MOSFETs to turn on. The ISL6327A will continue to protect
the load in this fashion as long as the overvoltage condition
occurs.
Once an overvoltage condition is detected, normal PWM
operation ceases until the ISL6327A is reset. Cycling the
voltage on EN_PWR, EN_VTT or VCC below the POR
FN6833.0
February 17, 2009
ISL6327A
falling threshold will reset the controller. Cycling the VID
codes will not reset the controller.
Overcurrent Protection
ISL6327A has two levels of overcurrent protection. Each
phase is protected from a sustained overcurrent condition by
limiting its peak current, while the combined phase currents
are protected on an instantaneous basis.
In instantaneous protection mode, the ISL6327A utilizes the
sensed average current IAVG to detect an overcurrent
condition. See “Channel-Current Balance” on page 12 for
more detail on how the average current is measured. The
average current is continually compared with a constant
85µA reference current as shown in Figure 9. Once the
average current exceeds the reference current, a
comparator triggers the converter to shutdown.
At the beginning of overcurrent shutdown, the controller
places all PWM signals in a high-impedance state within
20ns commanding the Intersil MOSFET driver ICs to turn off
both upper and lower MOSFETs. The system remains in this
state a period of 4096 switching cycles. If the controller is still
enabled at the end of this wait period, it will attempt a
soft-start. If the fault remains, the trip-retry cycles will
continue indefinitely (as shown in Figure 10) until either
controller is disabled or the fault is cleared. Note that the
energy delivered during trip-retry cycling is much less than
during full-load operation, so there is no thermal hazard
during this kind of operation.
The overcurrent protection level for the above two OCP
modes can be adjusted by changing the value of current
sensing resistors. In addition, ISL6327A can also adjust the
average OCP threshold level by adjusting the value of the
resistor from IOUT to GND. This provides additional safety
for the voltage regulator.
Equation 15 can be used to calculate the value of the resistor
RIOUT based on the desired OCP level IAVG, OCP2.
2
R IOUT = ------------------------------I AVG, OCP2
(EQ. 15)
Current Sense Output
The ISL6327A has 2 current sense output pins IDROOP and
IOUT; They are identical. In typical application, IDROOP pin
is connected to FB pin for the application where load line is
required. IOUT pin was designed for load current
measurement. As shown in the typical application
schematics on page 4 and page 5, load current information
can be obtained by measuring the voltage at IOUT pin with a
resistor connecting IOUT pin to the ground. When the
programmable temperature compensation function of
ISL6327A is properly used, the output current at IOUT pin is
proportional to the load current as shown in Figure 11.
V_IOUT, 200mV/DIV
For the individual channel overcurrent protection, the
ISL6327A continuously compares the sensed current signal
of each channel with the 120µA reference current. If one
channel current exceeds the reference current, ISL6327A
will pull PWM signal of this channel to low for the rest of the
switching cycle. This PWM signal can be turned on next
cycle if the sensed channel current is less than the 120µA
reference current. The peak current limit of individual
channel will not trigger the converter to shutdown.
0A
50A
100A
FIGURE 11. VOLTAGE AT IOUT PIN WITH A NTC NETWORK
PLACED BETWEEN IOUT TO GROUND WHEN
LOAD CURRENT CHANGES
OUTPUT CURRENT
There are two thermal signals to indicate the temperature
status of the voltage regulator: VR_HOT and VR_FAN. Both
VR_FAN and VR_HOT are open-drain outputs, and external
pull-up resistors are required. Those signals are valid only
after the controller is enabled.
0A
OUTPUT VOLTAGE
0V
Thermal Monitoring (VR_HOT/VR_FAN)
2ms/DIV
FIGURE 10. OVERCURRENT BEHAVIOR IN HICCUP MODE.
fSW = 500kHz
20
VR_FAN signal indicates that the temperature of the voltage
regulator is high and more cooling airflow is needed.
VR_HOT signal can be used to inform the system that the
temperature of the voltage regulator is too high and the CPU
should reduce its power consumption. VR_HOT signal may
be tied to the CPU’s PROCHOT# signal.
FN6833.0
February 17, 2009
ISL6327A
The diagram of thermal monitoring function block is shown in
Figure 12. One NTC resistor should be placed close to the
power stage of the voltage regulator to sense the operational
temperature, and one pull-up resistor is needed to form the
voltage divider for TM pin. As the temperature of the power
stage increases, the resistance of the NTC will reduce,
resulting in the reduced voltage at TM pin. Figure 13 shows
the TM voltage over the temperature for a typical design with
a recommended 6.8kΩ NTC (P/N: NTHS0805N02N6801
from Vishay) and 1kΩ resistor RTM1. We recommend using
those resistors for the accurate temperature compensation.
There are two comparators with hysteresis to compare the
TM pin voltage to the fixed thresholds for VR_FAN and
VR_HOT signals respectively. VR_FAN signal is set to high
when TM voltage is lower than 33% of VCC voltage, and is
pulled to GND when TM voltage increases to above 39% of
VCC voltage. VR_HOT is set to high when TM voltage goes
below 28% of VCC voltage, and is pulled to GND when TM
voltage goes back to above 33% of VCC voltage. Figure 14
shows the operation of those signals.
VCC
VR_FAN
+
0.33*VCC
VR_HOT
TM
+
-
RNTC
C
0.28*VCC
FIGURE 12. BLOCK DIAGRAM OF THERMAL MONITORING
FUNCTION
VR_FAN
VR_HOT
TEMPERATURE
T1
T2
T3
FIGURE 14. VR_HOT AND VR_FAN SIGNAL vs TM VOLTAGE
Based on the NTC temperature characteristics and the
desired threshold of VR_HOT signal, the pull-up resistor
RTM1 of TM pin is given by Equation 16:
R TM1 = 2.75xR NTC ( T3 )
(EQ. 16)
RNTC(T3) is the NTC resistance at the VR_HOT threshold
temperature T3.
The NTC resistance at the set point T2 and release point T1 of
VR_FAN signal can be calculated using Equations 17 and 18:
R NTC ( T2 ) = 1.267xR NTC ( T3 )
(EQ. 17)
R NTC ( T1 ) = 1.644xR NTC ( T3 )
(EQ. 18)
Temperature Compensation
ISL6327A supports inductor DCR sensing, or resistive
sensing techniques. The inductor DCR have the positive
temperature coefficient, which is about +0.38%/°C. Because
the voltage across inductor is sensed for the output current
information, the sensed current has the same positive
temperature coefficient as the inductor DCR.
70
In order to obtain the correct current information, there
should be a way to correct the temperature impact on the
current sense component. ISL6327A provides two methods:
integrated temperature compensation and external
temperature compensation.
60
Integrated Temperature Compensation
50
When TCOMP voltage is equal or greater than VCC/15,
ISL6327A will utilize the voltage at TM and TCOMP pins to
compensate the temperature impact on the sensed current.
The block diagram of this function is shown in Figure 15.
100
90
80
VTM/VCC (%)
0.39*VCC
0.33*VCC
0.28*VCC
With the NTC resistance value obtained from Equations 17
and 18, the temperature value T2 and T1 can be found from
the NTC datasheet.
RTM1
TM
40
30
20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
FIGURE 13. THE RATIO OF TM VOLTAGE TO NTC
TEMPERATURE WITH RECOMMENDED PARTS
21
FN6833.0
February 17, 2009
ISL6327A
the temperature impact on the sensed channel current. The
compensated channel current signal is used for droop and
overcurrent protection functions.
.
VCC
ISEN6
RTM1
TM
°C
NON-LINEAR
A/D
CHANNEL CURRENT SENSE
ISEN5
ISEN4
ISEN3
ISEN2
ISEN1
RNTC
I5
I6
D/A
I3
I4
I2
I1
Ki
X
X
X
X
X
X
RTC1
TCOMP
4-BIT
A/D
DROOP, IOUT AND
OVERCURRENT PROTECTION
RTC2
Design Procedure
1. Properly choose the voltage divider for TM pin to match
the TM voltage vs temperature curve with the
recommended curve in Figure 13.
2. Run the actual board under the full load and the desired
cooling condition.
3. After the board reaches the thermal steady state, record
the temperature (TCSC) of the current sense component
(inductor) and the voltage at TM and VCC pins.
4. Use Equation 19 to calculate the resistance of the TM
NTC, and find out the corresponding NTC temperature
TNTC from the NTC datasheet.
R NTC ( T
FIGURE 15. BLOCK DIAGRAM OF INTEGRATED
TEMPERATURE COMPENSATION
When the TM NTC is placed close to the current sense
component (inductor), the temperature of the NTC will track
the temperature of the current sense component. Therefore,
the TM voltage can be utilized to obtain the temperature of
the current sense component.
Based on VCC voltage, ISL6327A converts the TM pin
voltage to a 6-bit TM digital signal for temperature
compensation. With the non-linear A/D converter of
ISL6327A, TM digital signal is linearly proportional to the
NTC temperature. For accurate temperature compensation,
the ratio of the TM voltage to the NTC temperature of the
practical design should be similar to that in Figure 13.
Depending on the location of the NTC and the air-flowing,
the NTC may be cooler or hotter than the current sense
component. TCOMP pin voltage can be utilized to correct
the temperature difference between NTC and the current
sense component. When a different NTC type or different
voltage divider is used for the TM function, TCOMP voltage
can also be used to compensate for the difference between
the recommended TM voltage curve in Figure 14 and that of
the actual design. According to the VCC voltage, ISL6327A
converts the TCOMP pin voltage to a 4-bit TCOMP digital
signal as TCOMP factor N.
TCOMP factor N is an integer between 0 and 15. The
integrated temperature compensation function is disabled for
N = 0. For N = 4, the NTC temperature is equal to the
temperature of the current sense component. For N < 4, the
NTC is hotter than the current sense component. The NTC is
cooler than the current sense component for N > 4. When
N > 4, the larger TCOMP factor N, the larger the difference
between the NTC temperature and the temperature of the
current sense component.
NTC )
V TM xR
TM1
= ------------------------------V CC – V
(EQ. 19)
TM
5. Use Equation 20 to calculate the TCOMP factor N:
209x ( TCSC – T
)
NTC
N = -------------------------------------------------------- + 4
3xT NTC + 400
(EQ. 20)
6. Choose an integral number close to the above result for
the TCOMP factor. If this factor is higher than 15, use
N = 15. If it is less than 1, use N = 1.
7. Choose the pull-up resistor RTC1 (typical 10kΩ);
8. If N = 15, do not need the pull-down resistor RTC2,
otherwise obtain RTC2 using Equation 21:
NxR TC1
R TC2 = ----------------------15 – N
(EQ. 21)
9. Run the actual board under full load again with the proper
resistors to TCOMP pin.
10. Record the output voltage as V1 immediately after the
output voltage is stable with the full load; record the
output voltage as V2 after the VR reaches the thermal
steady state.
11. If the output voltage increases over 2mV as the
temperature increases, i.e. V2 - V1 >2mV, reduce N and
redesign RTC2; if the output voltage decreases over 2mV
as the temperature increases, i.e. V1 - V2 >2mV,
increase N and redesign RTC2.
The design spreadsheet is available for those calculations.
External Temperature Compensation
By pulling the TCOMP pin to GND, the integrated
temperature compensation function is disabled. And one
external temperature compensation network, shown in
Figure 16, can be used to cancel the temperature impact on
the droop (i.e. load line).
ISL6327A multiplexes the TCOMP factor N with the TM
digital signal to obtain the adjustment gain to compensate
22
FN6833.0
February 17, 2009
ISL6327A
.
COMP
ISL6327A
INTERNAL
CIRCUIT
IDROOP
°C
require heat sinks and forced air to cool the MOSFETs,
inductors, and heat-dissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching
frequency; the capability of the MOSFETs to dissipate heat;
and the availability and nature of heat sinking and air flow.
FB
LOWER MOSFET POWER CALCULATION
VDIFF
FIGURE 16. EXTERNAL TEMPERATURE COMPENSATION
The sensed current will flow out of IDROOP pin and develop
the droop voltage across the resistor (RFB) between FB and
VDIFF pins. If RFB resistance reduces as the temperature
increases, the temperature impact on the droop can be
compensated. An NTC resistor can be placed close to the
power stage and used to form RFB. Due to the non-linear
temperature characteristics of the NTC, a resistor network is
needed to make the equivalent resistance between FB and
VDIFF pin reverse proportional to the temperature.
The external temperature compensation network can only
compensate the temperature impact on the droop, while it
has no impact to the sensed current inside ISL6327A.
Therefore, this network cannot compensate for the
temperature impact on the overcurrent protection function.
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
MOSFET is due to current conducted through the channel
resistance (rDS(ON)). In Equation 22, IM is the maximum
continuous output current; IP-P is the peak-to-peak inductor
current (see Equation 1); d is the duty cycle (VOUT/VIN); and
L is the per-channel inductance.
I L ( P-P )2( 1 – d )
⎛ I M⎞ 2
P LOW, 1 = r DS ( ON ) ⎜ -----⎟ ( 1 – d ) + -----------------------------------12
⎝ N⎠
(EQ. 22)
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the dead
time when inductor current is flowing through the lower
MOSFET body diode. This term is dependent on the diode
forward voltage at IM, VD(ON); the switching frequency, fS; and
the length of dead times, td1 and td2, at the beginning and the
end of the lower-MOSFET conduction interval respectively.
.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts for all common microprocessor
applications.
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board; whether through-hole components are permitted; and
the total board space available for power-supply circuitry.
Generally speaking, the most economical solutions are
those in which each phase handles between 15A and 20A.
All surface-mount designs will tend toward the lower end of
this current range. If through-hole MOSFETs and inductors
can be used, higher per-phase currents are possible. In
cases where board space is the limiting constraint, current
can be pushed as high as 40A per phase, but these designs
23
⎛I
⎞
IM I ⎞
M I P-P
P-P- t
P LOW, 2 = V D ( ON ) f S ⎛ ----d1 + ⎜ ------ – ----------⎟ t d2
⎝ N- + --------⎠
2
2
⎝N
⎠
(EQ. 23)
Thus, the total maximum power dissipated in each lower
MOSFET is approximated by the summation of PLOW,1 and
PLOW,2.
UPPER MOSFET POWER CALCULATION
In addition to rDS(ON) losses, a large portion of the upper
MOSFET losses are due to currents conducted across the
input voltage (VIN) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent on
switching frequency, the power calculation is more complex.
Upper MOSFET losses can be divided into separate
components involving the upper-MOSFET switching times;
the lower-MOSFET body-diode reverse-recovery charge, Qrr,
and the upper MOSFET rDS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 24,
the required time for this commutation is t1 and the
approximated associated power loss is PUP,1.
I M I P-P⎞ ⎛ t 1 ⎞
P UP,1 ≈ V IN ⎛ ----- ⎜ ---- ⎟ f
⎝ N- + --------2 ⎠ ⎝ 2⎠ S
(EQ. 24)
FN6833.0
February 17, 2009
ISL6327A
At turn-on, the upper MOSFET begins to conduct and this
transition occurs over a time t2. In Equation 25, the
approximate power loss is PUP,2.
temperature. RX in Equation 28 should be the maximum DC
resistance of the current sense element at all the operational
temperature.
⎛ I M I P-P⎞ ⎛ t 2 ⎞
P UP, 2 ≈ V IN ⎜ ----- – ----------⎟ ⎜ ---- ⎟ f S
2 ⎠⎝ 2⎠
⎝N
In certain circumstances, it may be necessary to adjust the
value of one or more ISEN resistors. When the components
of one or more channels are inhibited from effectively
dissipating their heat so that the affected channels run hotter
than desired, choose new, smaller values of RISEN for the
affected phases (see the section titled “Channel-Current
Balance” on page 12). Choose RISEN,2 in proportion to the
desired decrease in temperature rise in order to cause
proportionally less current to flow in the hotter phase.
(EQ. 25)
A third component involves the lower MOSFET’s reverse
recovery charge, Qrr. Since the inductor current has fully
commutated to the upper MOSFET before the lower
MOSFET’s body diode can draw all of Qrr, it is conducted
through the upper MOSFET across VIN. The power
dissipated as a result is PUP,3 and is approximately.
P UP,3 = V IN Q rr f S
(EQ. 26)
Finally, the resistive part of the upper MOSFET’s is given in
Equation 27 as PUP,4.
2
I P-P2
⎛ I M⎞
P UP,4 ≈ r DS ( ON ) ⎜ -----⎟ d + ----------d
12
⎝ N⎠
(EQ. 27)
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 24, 25, 26 and 27. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
ΔT
R ISEN ,2 = R ISEN ----------2
ΔT 1
(EQ. 29)
In Equation 29, make sure that ΔT2 is the desired temperature
rise above the ambient temperature, and ΔT1 is the measured
temperature rise above the ambient temperature. While a
single adjustment according to Equation 29 is usually
sufficient, it may occasionally be necessary to adjust RISEN
two or more times to achieve optimal thermal balance
between all channels.
Load-Line Regulation Resistor
The load-line regulation resistor is labelled RFB in Figure 5.
Its value depends on the desired loadline requirement of the
application.
Current Sensing Resistor
The desired loadline can be calculated using Equation 30:
The resistors connected to the Isen+ pins determine the
gains in the load-line regulation loop and the channel-current
balance loop as well as setting the overcurrent trip point.
Select values for these resistors by the Equation 28.
V DROOP
R LL = -----------------------I FL
RX
I OCP
R ISEN = ---------------------- ------------–6 N
85 ×10
(EQ. 28)
where RISEN is the sense resistor connected to the ISEN+
pin, N is the active channel number, RX is the resistance of
the current sense element, either the DCR of the inductor or
RSENSE depending on the sensing method, and IOCP is the
desired overcurrent trip point. Typically, IOCP can be chosen
to be 1.3x the maximum load current of the specific
application.
With integrated temperature compensation, the sensed
current signal is independent on the operational temperature
of the power stage, i.e. the temperature effect on the current
sense element RX is cancelled by the integrated
temperature compensation function. RX in Equation 28
should be the resistance of the current sense element at the
room temperature.
When the integrated temperature compensation function is
disabled by pulling the TCOMP pin to GND, the sensed
current will be dependent on the operational temperature of
the power stage, since the DC resistance of the current
sense element may be changed according to the operational
24
(EQ. 30)
where IFL is the full load current of the specific application,
and VRDROOP is the desired voltage droop under the full
load condition.
Based on the desired loadline RLL, the loadline regulation
resistor can be calculated using Equation 31:
NR
R
ISEN LL
R FB = --------------------------------RX
(EQ. 31)
where N is the active channel number, RISEN is the sense
resistor connected to the ISEN+ pin, and RX is the
resistance of the current sense element, either the DCR of
the inductor or RSENSE depending on the sensing method.
If one or more of the current sense resistors are adjusted for
thermal balance, as in Equation 29, the load-line regulation
resistor should be selected based on the average value of
the current sensing resistors, as given in Equation 32:
R LL
R FB = ---------RX
∑ RISEN ( n )
n
(EQ. 32)
where RISEN(n) is the current sensing resistor connected to
the nth ISEN+ pin.
FN6833.0
February 17, 2009
ISL6327A
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
each of the three cases in Equation 33, there are a separate
set of equations for the compensation components.
Case 1:
1
------------------- > f 0
2π LC
2πf 0 V P-P LC
R C = R FB ------------------------------------0.75V
IN
0.75V IN
C C = ------------------------------------2πV P-P R FB f 0
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, RC and CC.
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
Case 2:
1
1
------------------- ≤ f 0 < ----------------------------2πC ( ESR )
2π LC
V P-P ( 2π ) 2 f 02 LC
R C = R FB --------------------------------------------0.75 V
(EQ. 33)
IN
0.75V IN
C C = -------------------------------------------------------------2
( 2π ) f 02 V P-P R FB LC
Case 3:
1
f 0 > -----------------------------2πC ( ESR )
2π f 0 V P-P L
R C = R FB ----------------------------------------0.75 V IN ( ESR )
0.75V IN ( ESR ) C
C C = -----------------------------------------------2πV P-P R FB f 0 L
.
In Equation 33, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and VPP is the peak-topeak sawtooth signal amplitude as described in “Electrical
Specifications” on page 6.
C2 (OPTIONAL)
CC
COMP
FB
+
RFB
IDROOP
VDROOP
ISL6327A
RC
VDIFF
FIGURE 17. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6327A CIRCUIT
The feedback resistor, RFB, has already been chosen as
outlined in “Load-Line Regulation Resistor” on page 24.
Select a target bandwidth for the compensated system, f0.
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f0
to the L-C pole frequency and the ESR zero frequency. For
25
The optional capacitor C2, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 18). Keep
a position available for C2, and be prepared to install a high
frequency capacitor of between 22pF and 150pF in case any
leading-edge jitter problem is noted.
Once selected, the compensation values in Equation 33
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to RC. Slowly increase the
value of RC while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
CC will not need adjustment. Keep the value of CC from
Equation 33 unless some performance issue is noted.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type III controller, as shown in Figure 18, provides the
necessary compensation.
FN6833.0
February 17, 2009
ISL6327A
Output Filter Design
.
C2
CC
COMP
FB
C1
IDROOP
RFB
R1
ISL6327A
RC
The output inductors and the output capacitor bank together
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must
provide the transient energy until the regulator can respond.
Because it has a low bandwidth compared to the switching
frequency, the output filter necessarily limits the system
transient response. The output capacitor must supply or sink
load current while the current in the output inductors
increases or decreases to meet the demand.
VDIFF
FIGURE 18. COMPENSATION CIRCUIT FOR ISL6327A BASED
CONVERTER WITHOUT LOAD-LINE
REGULATION
The first step is to choose the desired bandwidth, f0, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, fHF. This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose fHF = 10f0, but it can be
higher if desired. Choosing fHF to be lower than 10f0 can
cause problems with too much phase shift below the system
bandwidth.
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 34, RFB is selected arbitrarily. The remaining
compensation components are then selected according to
Equation 34..
C ( ESR )
R 1 = R FB ----------------------------------------LC – C ( ESR )
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ΔI; the load-current slew rate, di/dt; and the
maximum allowable output-voltage deviation under transient
loading, ΔVMAX. Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total
output-voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount:
di
ΔV ≈ ( ESL ) ----- + ( ESR ) ΔI
dt
(EQ. 35)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔVMAX.
LC – C ( ESR )
C 1 = ----------------------------------------R FB
0.75V IN
C 2 = ------------------------------------------------------------------( 2π ) 2 f 0 f HF LCR FB V P-P
(EQ. 34)
2
V PP ⎛ 2π⎞ f 0 f HF LCR FB
⎝ ⎠
R C = -------------------------------------------------------------------⎛2πf
⎞
0.75 V
⎝ HF LC – 1⎠
IN
⎞
0.75V IN ⎛2πf
⎝ HF LC – 1⎠
C C = -------------------------------------------------------------------( 2π ) 2 f 0 f HF LCR FB V P-P
In Equation 34, L is the per-channel filter inductance divided by
the number of active channels; C is the sum total of all output
capacitors; ESR is the equivalent-series resistance of the bulk
output-filter capacitance; and VP-P is the peak-to-peak
sawtooth signal amplitude as described in “Electrical
Specifications” on page 6.
26
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Interleaving” on
page 10 and Equation 2), a voltage develops across the
bulk-capacitor ESR equal to IC(P-P) (ESR). Thus, once the
output capacitors are selected, the maximum allowable
ripple voltage, VP-P(MAX), determines the lower limit on the
inductance.
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
FN6833.0
February 17, 2009
ISL6327A
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔVMAX. This places an upper limit on inductance.
Equation 37 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 38
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
2NCVO
L ≤ -------------------- ΔV MAX – ΔI ( ESR )
( ΔI ) 2
(EQ. 37)
( 1.25 ) NC
L ≤ -------------------------- ΔV MAX – ΔI ( ESR ) ⎛ V IN – V O⎞
⎝
⎠
( ΔI ) 2
(EQ. 38)
Switching Frequency
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper-MOSFET loss calculation. These effects are
outlined in “MOSFETs” on page 23, and they establish the
upper limit for the switching frequency. The lower limit is
established by the requirement for fast transient response and
small output-voltage ripple as outlined in “Output Filter
Design” on page 26. Choose the lowest switching frequency
that allows the regulator to meet the transient-response
requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, RT (see the figures labelled
“Typical Application” on page 4 and page 5). Equation 3 is
provided to assist in selecting the correct value for RT.
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs that is related to duty cycle and the number of
active phases.
For a two phase design, use Figure 19 to determine the
input-capacitor RMS current requirement given the duty
cycle, maximum sustained output current (IO), and the ratio
of the per-phase peak-to-peak inductor current (IL(P-P)) to
IO. Select a bulk capacitor with a ripple current rating which
will minimize the total number of input capacitors required to
support the RMS current calculated. The voltage rating of
the capacitors should also be at least 1.25x greater than the
maximum input voltage.
27
0.3
INPUT-CAPACITOR CURRENT (IRMS/IO)
(EQ. 36)
0.2
0.1
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0
0
0.2
0.4
0.6
DUTY CYCLE (VO/VIN)
0.8
1.0
FIGURE 19. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 2-PHASE CONVERTER
0.3
INPUT-CAPACITOR CURRENT (IRMS/IO)
⎛V – N V
⎞
OUT⎠ V OUT
⎝ IN
L ≥ ( ESR ) -----------------------------------------------------------f S V IN V P – P( MAX )
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.25 IO
IL(P-P) = 0.75 IO
0.2
0.1
0
0
0.2
0.4
0.6
DUTY CYCLE (VO/VIN)
0.8
1.0
FIGURE 20. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 3-PHASE CONVERTER
Figures 20 and 21 provide the same input RMS current
information for three and four phase designs respectively.
Use the same approach to selecting the bulk capacitor type
and number as described previously.
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the bulk capacitors to suppress leading
and falling edge voltage spikes. They result from the high
current slew rates produced by the upper MOSFETs turning on
and off. Select low ESL ceramic capacitors and place one as
close as possible to each upper MOSFET drain to minimize
board parasitic impedances and maximize suppression.
MULTIPHASE RMS IMPROVEMENT
Figure 22 is provided as a reference to demonstrate the
dramatic reductions in input-capacitor RMS current upon the
implementation of the multiphase topology. For example,
compare the input RMS current requirements of a two-phase
converter versus that of a single phase. Assume both
converters have a duty cycle of 0.25, maximum sustained
output current of 40A, and a ratio of IL(P-P) to IO of 0.5. The
single phase converter would require 17.3ARMS current
capacity while the two-phase converter would only require
10.9ARMS. The advantages become even more pronounced
FN6833.0
February 17, 2009
ISL6327A
when output current is increased and additional phases are
added to keep the component cost down relative to the
single phase approach.
.
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.3
IL(P-P) = 0
IL(P-P) = 0.25 IO
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0.2
0.1
0
0
0.2
0.4
0.6
DUTY CYCLE (VO/VIN)
0.8
1.0
FIGURE 21. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 4-PHASE CONVERTER
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.6
Within the allotted implementation area, orient the switching
components first. The switching components are the most
critical because they carry large amounts of energy and tend
to generate high levels of noise. Switching component
placement should take into account power dissipation. Align
the output inductors and MOSFETs such that spaces
between the components are minimized while creating the
PHASE plane. Place the Intersil MOSFET driver IC as close
as possible to the MOSFETs they control to reduce the
parasitic impedances due to trace length between critical
driver input and output signals. If possible, duplicate the
same placement of these components for each phase.
Next, place the input and output capacitors. Position one
high-frequency ceramic input capacitor next to each upper
MOSFET drain. Place the bulk input capacitors as close to the
upper MOSFET drains as dictated by the component size and
dimensions. Long distances between input capacitors and
MOSFET drains result in too much trace inductance and a
reduction in capacitor performance. Locate the output
capacitors between the inductors and the load, while keeping
them in close proximity to the microprocessor socket.
The ISL6327A can be placed off to one side or centered
relative to the individual phase switching components.
Routing of sense lines and PWM signals will guide final
placement. Critical small signal components to place close
to the controller include the ISEN resistors, RT resistor,
feedback resistor, and compensation components.
0.4
0.2
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0
Component Placement
0
0.2
Bypass capacitors for the ISL6327A and ISL66xx driver bias
supplies must be placed next to their respective pins. Trace
parasitic impedances will reduce their effectiveness.
0.4
0.6
DUTY CYCLE (VO/VIN)
0.8
1.0
FIGURE 22. NORMALIZED INPUT-CAPACITOR RMS
CURRENT vs DUTY CYCLE FOR SINGLE-PHASE
CONVERTER
Layout Considerations
The following layout strategies are intended to minimize the
impact of board parasitic impedances on converter
performance and to optimize the heat-dissipating capabilities
of the printed-circuit board. These sections highlight some
important practices which should not be overlooked during the
layout process.
Plane Allocation and Routing
Dedicate one solid layer, usually a middle layer, for a ground
plane. Make all critical component ground connections with
vias to this plane. Dedicate one additional layer for power
planes; breaking the plane up into smaller islands of
common voltage. Use the remaining layers for signal wiring.
Route phase planes of copper filled polygons on the top and
bottom once the switching component placement is set. Size
the trace width between the driver gate pins and the
MOSFET gates to carry 4A of current. When routing
components in the switching path, use short wide traces to
reduce the associated parasitic impedances.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
28
FN6833.0
February 17, 2009
ISL6327A
Package Outline Drawing
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 10/06
4X 5.5
7.00
A
44X 0.50
B
37
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
1
7.00
36
4. 30 ± 0 . 15
12
25
(4X)
0.15
13
24
0.10 M C A B
48X 0 . 40± 0 . 1
TOP VIEW
4 0.23 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
( 6 . 80 TYP )
(
0.10 C
BASE PLANE
0 . 90 ± 0 . 1
4 . 30 )
C
SEATING PLANE
0.08 C
SIDE VIEW
( 44X 0 . 5 )
C
0 . 2 REF
5
( 48X 0 . 23 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
29
FN6833.0
February 17, 2009
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