DATASHEET

ISL6439, ISL6439A
Data Sheet
September 15, 2015
Single Sync Buck PWM Controller for
Broadband Gateway Applications
The ISL6439 makes easy work out of implementing a
complete control and protection scheme for a DC/DC
step-down converter. Designed to drive N-Channel
MOSFETs in a synchronous buck topology, the ISL6439
integrates the control, output adjustment, monitoring and
protection functions into a single package.
The ISL6439 provides simple, single feedback loop, voltagemode control with fast transient response. The output
voltage can be precisely regulated to as low as 0.8V, with a
maximum tolerance of ±1.5% over temperature and line
voltage variations. A fixed frequency oscillator reduces
design complexity, while balancing typical application cost
and efficiency.
The error amplifier features a 15MHz gain-bandwidth
product and 6V/s slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
Protection from overcurrent conditions is provided by
monitoring the rDS(ON) of the upper MOSFET to inhibit PWM
operation appropriately. This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor.
FN9057.6
Features
• Operates from 3.3V to 5V Input
• 0.8V to VIN Output Range
- 0.8V Internal Reference
- ±1.5% Over Load, Line Voltage and Temperature
• Drives N-Channel MOSFETs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
• Lossless, Programmable Overcurrent Protection
- Uses Upper MOSFET’s rDS(on)
• Converter can Source and Sink Current
• Small Converter Size
- Internal Fixed Frequency Oscillator
- ISL6439: 300kHz
- ISL6439A: 600kHz
• Internal Soft-Start
• 14 Pin SOIC or 16 Lead 5x5 QFN
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Lead - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-free (RoHS compliant)
Applications
• Cable Modems, Set Top Boxes, and DSL Modems
• DSP and Core Communications Processor Supplies
• Memory Supplies
• Personal Computer Peripherals
• Industrial Power Supplies
• 3.3V-Input DC/DC Regulators
• Low-Voltage Distributed Power Supplies
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC.
Copyright © Intersil Americas LLC. 2003-2004, 2008, 2015. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL6439, ISL6439A
Pinouts
CT1
2
CT2
3
OCSET
4
TE
D
R
BOOT
11 VCC
IL
A
AV
A
10 CPGND
9
ER
8 COMP
NC
5
6
7
8
NC
FB
COMP
ENABLE
N
O
LO
N
G
FB 7
12 PHASE
B
9 ENABLE
OCSET 6
O
SU
1
13
R
CPVOUT
14
O
11 VCC
10 CPGND
15
LE
CT1 4
CT2 5
16
PP
12 PHASE
CPVOUT 3
UGATE
13 BOOT
LGATE 2
GND
14 UGATE
GND 1
LGATE
ISL6439, ISL6439A
(16 LEAD 5x5 QFN)
TOP VIEW
ISL6439, ISL6439A
(14 LEAD SOIC)
TOP VIEW
Ordering Information
PART NUMBER
(See Note)
PART MARKING
TEMP RANGE (°C)
PACKAGE
(RoHS Compliant)
PKG DWG. #
ISL6439CBZ (No longer
available, recommended
replacement: ISL6439IBZ)
6439CBZ
0 to +70
14 lead SOIC
M14.15
ISL6439IBZ
6439IBZ
-40 to +85
14 lead SOIC
M14.15
ISL6439AIBZ
6439AIBZ
-40 to +85
14 lead SOIC
M14.15
ISL6439IRZ (No longer
available or supported)
ISL6439 IRZ
-40 to +85
16 Lead 5x5 QFN
L16.5x5B
ISL6439AIRZ (No longer
available or supported)
ISL6439 AIRZ
-40 to +85
16 Lead 5x5 QFN
L16.5x5B
ISL6439EVAL1
ISL6439 SOIC Evaluation Board
*Add “-T” suffix to part number for tape and reel packaging. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
2
FN9057.6
September 15, 2015
ISL6439, ISL6439A
Typical Application - 3.3V Input
3.3V
VIN
CIN
CBULK
VCC
OCSET
CT1
ROCSET
CPUMP
CPVOUT
CT2
ISL6439
DBOOT
CDCPL
CHF
BOOT
CPGND
CBOOT
UGATE
GND
Q1
PHASE
ENABLE
LGATE
COMP
DISABLE
Q2
FB
LOUT
VOUT
COUT
CI
RFB
RF
CF
ROFFSET
3
FN9057.6
September 15, 2015
ISL6439, ISL6439A
Typical Application - 5V Input
+5V
VIN
CBULK
VCC
OCSET
CT1
ROCSET
CPVOUT
N/C
CT2
ISL6439
DBOOT
CIN
CHF
BOOT
CPGND
CBOOT
UGATE
GND
Q1
PHASE
ENABLE
LGATE
COMP
DISABLE
Q2
FB
LOUT
VOUT
COUT
CI
RFB
CF
RF
ROFFSET
Block Diagram
VCC
CT1
CPVOUT
CHARGE
PUMP
CT2
POWER-ON
RESET (POR)
ENABLE
CPGND
BOOT
+
-
OCSET
SOFTSTART
OC
COMPARATOR
20A
UGATE
ERROR
AMP
+
-
+
0.8V
PWM
COMPARATOR
+
-
INHIBIT
PHASE
GATE
CONTROL
LOGIC
PWM
LGATE
FB
OSCILLATOR
COMP
FIXED 300kHz or 600kHz
GND
4
FN9057.6
September 15, 2015
ISL6439, ISL6439A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V
Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . +6.0V
Input, Output or I/O Voltage . . . . . . . . . . GND - 0.3V to VCC + 0.3V
Thermal Resistance
JA (°C/W)
JC (°C/W)
SOIC Package (Note 1) . . . . . . . . . . . .
67
N/A
QFN Package (Note 2). . . . . . . . . . . . .
35
5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
For Recommended soldering conditions see Tech Brief TB389.
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3V ±10%
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. JC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
3. Limits established by characterization and are not production tested.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted VCC = 3.3V±5% and TA = +25°C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
6.1
6.9
7.7
mA
Commercial
4.25
4.30
4.42
V
Industrial
4.10
4.30
4.50
V
0.3
0.6
0.9
V
IC = ISL6439C, Commercial
275
300
325
kHz
IC = ISL6439I, Industrial
250
300
340
kHz
IC = ISL6439AC, Commercial
554
600
645
kHz
IC = ISL6439AI, Industrial
524
600
650
kHz
-
1.5
-
VP-P
-
-
1.5
%
-
0.800
-
V
-
5.1
-
V
-
2
-
%
-
88
-
dB
GBWP
-
15
-
MHz
SR
-
6
-
V/s
VCC SUPPLY CURRENT
Nominal Supply
IBIAS
POWER-ON RESET
Rising CPVOUT POR Threshold
POR
CPVOUT POR Threshold Hysteresis
OSCILLATOR
Frequency
fOSC
VOSC
Ramp Amplitude
REFERENCE
Reference Voltage Tolerance
Nominal Reference Voltage
VREF
Charge Pump
Nominal Charge Pump Output
VCPVOUT
VVCC = 3.3V, No Load
Charge Pump Output Regulation
ERROR AMPLIFIER
DC Gain
Note 3
Gain-Bandwidth Product
Slew Rate
SOFT START
Soft Start Slew Rate
5
Commercial
6.2
7.3
ms
Industrial
6.2
7.6
ms
FN9057.6
September 15, 2015
ISL6439, ISL6439A
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted VCC = 3.3V±5% and TA = +25°C (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
GATE DRIVERS
Upper Gate Source Current
IUGATE-SRC VBOOT - VPHASE = 5V, VUGATE = 4V
-
-1
-
A
Upper Gate Sink Current
IUGATE-SNK
-
1
-
A
Lower Gate Source Current
ILGATE-SRC VVCC = 3.3V, VLGATE = 4V
-
-1
-
A
Lower Gate Sink Current
ILGATE-SNK
-
2
-
A
Commercial
18
20
22
A
Industrial
16
20
22
A
-
-
0.8
V
PROTECTION / DISABLE
OCSET Current Source
IOCSET
Disable Threshold
VDISABLE
Functional Pin Description
PHASE
14 LEAD SOIC
14 UGATE
GND 1
13 BOOT
LGATE 2
12 PHASE
CPVOUT 3
CT1 4
11 VCC
CT2 5
10 CPGND
9 ENABLE
OCSET 6
GND
UGATE
BOOT
16 LEAD 5x5 QFN
8 COMP
LGATE
FB 7
16
15
14
13
1
12 PHASE
CT1
2
11 VCC
CT2
3
10 CPGND
OCSET
4
9
NC
8
ENABLE
7
COMP
FB
NC
6
VCC
This pin provides the bias supply for the ISL6439. Connect a
well-decoupled 3.3V supply to this pin.
COMP and FB
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the internal
error amplifier and the COMP pin is the error amplifier
output. These pins are used to compensate the voltagecontrol feedback loop of the converter.
GND
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
6
UGATE
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive
shoot-through protection circuitry to determine when the
upper MOSFET has turned off.
BOOT
CPVOUT
5
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection.
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-Channel MOSFET.
LGATE
Connect this pin to the lower MOSFET’s gate. This pin provides
the PWM-controlled gate drive for the lower MOSFET. This pin
is also monitored by the adaptive shoot-through protection
circuitry to determine when the lower MOSFET has turned off.
OCSET
Connect a resistor (ROCSET) from this pin to the drain of the
upper MOSFET (VIN). ROCSET, an internal 20A current
source (IOCSET), and the upper MOSFET on-resistance
(rDS(ON)) set the converter overcurrent (OC) trip point
according to Equation 1:
I OCSET xR OCSET
I PEAK = ------------------------------------------------r DS  ON 
(EQ. 1)
An overcurrent trip cycles the soft-start function.
ENABLE
This pin is the open-collector enable pin. Pulling this pin to a
level below 0.8V will disable the controller. Disabling the
ISL6439 causes the oscillator to stop, the LGATE and
UGATE outputs to be held low, and the softstart circuitry to
re-arm.
FN9057.6
September 15, 2015
ISL6439, ISL6439A
CT1 and CT2
These pins are the connections for the external charge
pump capacitor. A minimum of a 0.1F ceramic capacitor is
recommended for proper operation of the IC.
CPVOUT
This pin represents the output of the charge pump. The
voltage at this pin is the bias voltage for the IC. Connect a
decoupling capacitor from this pin to ground. The value of
the decoupling capacitor should be at least 10x the value of
the charge pump capacitor. This pin may be tied to the
bootstrap circuit as the source for creating the BOOT
voltage.
CPGND
This pin represents the signal and power ground for the
charge pump. Tie this pin to the ground island/plane through
the lowest impedance connection available.
Functional Description
Initialization
The ISL6439 automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary.
The Power-On Reset (POR) function continually monitors the
the output voltage of the charge pump. During POR, the charge
pump operates on a free running oscillator. Once the POR level
is reached, the charge pump oscillator is synched to the PWM
oscillator. The POR function also initiates the soft-start
operation after the charge pump output voltage exceeds its
POR threshold.
Soft-Start
The POR function initiates the digital soft-start sequence. The
PWM error amplifier reference is clamped to a level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator generates PHASE pulses of
increasing width that charge the output capacitor(s). This
method provides a rapid and controlled output voltage rise. The
soft start sequence typically takes about 6.5ms.
(1V/DIV)
CPVOUT (5V)
VCC (3.3V)
VOUT (2.50V)
Figure 1 shows the soft-start sequence for a typical application.
At t0, the +3.3V VCC voltage starts to ramp. At time t1, the
Charge Pump begins operation and the +5V CPVOUT IC bias
voltage starts to ramp up. Once the voltage on CPVOUT
crosses the POR threshold at time t2, the output begins the
soft-start sequence. The triangle waveform from the PWM
oscillator is compared to the rising error amplifier output
voltage. As the error amplifier voltage increases, the pulsewidth on the UGATE pin increases to reach the steady-state
duty cycle at time t3.
Shoot-Through Protection
A shoot-through condition occurs when both the upper
MOSFET and lower MOSFET are turned on simultaneously,
effectively shorting the input voltage to ground. To protect
the regulator from a shoot-through condition, the ISL6439
incorporates specialized circuitry which insures that the
complementary MOSFETs are not ON simultaneously.
The adaptive shoot-through protection utilized by the
ISL6439 looks at the lower gate drive pin, LGATE, and the
upper gate drive pin, UGATE, to determine whether a
MOSFET is ON or OFF. If the voltage from UGATE or from
LGATE to GND is less than 0.8V, then the respective
MOSFET is defined as being OFF and the complementary
MOSFET is turned ON. This method of shoot-through
protection allows the regulator to sink or source current.
Since the voltage of the lower MOSFET gate and the upper
MOSFET gate are being measured to determine the state of
the MOSFET, the designer is encouraged to consider the
repercussions of introducing external components between
the gate drivers and their respective MOSFET gates before
actually implementing such measures. Doing so may
interfere with the shoot-through protection.
Output Voltage Selection
The output voltage can be programmed to any level between
VIN and the internal reference, 0.8V. An external resistor
divider is used to scale the output voltage relative to the
reference voltage and feed it back to the inverting input of
the error amplifier, see Figure 2. However, since the value of
R1 affects the values of the rest of the compensation
components, it is advisable to keep its value less than 5k.
R4 can be calculated based on Equation 2:
R1  0.8V
R4 = -------------------------------------V OUT1 – 0.8V
(EQ. 2)
If the output voltage desired is 0.8V, simply route the output
back to the FB pin through R1, but do not populate R4.
Overcurrent Protection
0V
T0
T1
T2
T3
TIME
FIGURE 1. SOFT-START INTERVAL
7
The overcurrent function protects the converter from a shorted
output by using the upper MOSFET on-resistance, rDS(ON), to
monitor the current. This method enhances the converter’s
efficiency and reduces cost by eliminating a current sensing
resistor.
FN9057.6
September 15, 2015
ISL6439, ISL6439A
+3.3V
VOUT (2.5V)
VIN
VCC
CPVOUT
D1
BOOT
C4
UGATE
ISL6439
Q1
LOUT
VOUT
PHASE
Q2
LGATE
0V
+
COUT
Internal Soft-Start Function
FB
C1
COMP
R1
C3
C2
Delay Interval
R3
R2
R4
T1
T0
T2
TIME
FIGURE 3. OVER CURRENT PROTECTION RESPONSE
FIGURE 2. OUTPUT VOLTAGE SELECTION
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (ROCSET)
programs the overcurrent trip level (see Typical Application
diagrams on pages 2 and 3). An internal 20A (typical) current
sink develops a voltage across ROCSET that is referenced to
VIN. When the voltage across the upper MOSFET (also
referenced to VIN) exceeds the voltage across ROCSET, the
overcurrent function initiates a soft-start sequence.
Figure 3 illustrates the protection feature responding to an
overcurrent event. At time t0, an overcurrent condition is
sensed across the upper MOSFET. As a result, the regulator
is quickly shutdown and the internal soft-start function begins
producing soft-start ramps. The delay interval seen by the
output is equivalent to three soft-start cycles. The fourth
internal soft-start cycle initiates a normal soft-start ramp of
the output, at time t1. The output is brought back into
regulation by time t2, as long as the overcurrent event has
cleared.
Had the cause of the over current still been present after the
delay interval, the over current condition would be sensed
and the regulator would be shut down again for another
delay interval of three soft-start cycles. The resulting hiccup
mode style of protection would continue to repeat
indefinitely.
The overcurrent function will trip at a peak inductor current
(IPEAK) determined by Equation 3:
I OCSET x R OCSET
I PEAK = ----------------------------------------------------r DS  ON 
(EQ. 3)
where IOCSET is the internal OCSET current source (20A
typical). The OC trip point varies mainly due to the MOSFET
8
rDS(ON) variations. To avoid overcurrent tripping in the
normal operating load range, find the ROCSET resistor from
the equation above with:
1. The maximum rDS(ON) at the highest junction
temperature.
2. The minimum IOCSET from the specification table.
 I 
- ,
3. Determine IPEAK for I PEAK  I OUT  MAX  + --------2
whereI is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
A small ceramic capacitor should be placed in parallel with
ROCSET to smooth the voltage across ROCSET in the
presence of switching noise on the input voltage.
Current Sinking
The ISL6439 incorporates a MOSFET shoot-through
protection method which allows a converter to sink current
as well as source current. Care should be exercised when
designing a converter with the ISL6439 when it is known that
the converter may sink current.
When the converter is sinking current, it is behaving as a
boost converter that is regulating its input voltage. This
means that the converter is boosting current into the input
rail of the regulator. If there is nowhere for this current to go,
such as to other distributed loads on the rail or through a
voltage limiting protection device, the capacitance on this rail
will absorb the current. This situation will allow the voltage
level of the input rail to increase. If the voltage level of the rail
is boosted to a level that exceeds the maximum voltage
rating of any components attached to the input rail, then
those components may experience an irreversible failure or
experience stress that may shorten their lifespan. Ensuring
FN9057.6
September 15, 2015
ISL6439, ISL6439A
that there is a path for the current to flow other than the
capacitance on the rail will prevent this failure mode.
+3.3V VIN
ISL6439
Application Guidelines
VCC
Layout Considerations
CVCC
As an example, consider the turn-off transition of the PWM
MOSFET. Prior to turn-off, the MOSFET is carrying the full load
current. During turn-off, current stops flowing in the MOSFET
and is picked up by the lower MOSFET. Any parasitic
inductance in the switched current path generates a large
voltage spike during the switching interval. Careful component
selection, tight layout of the critical components, and short, wide
traces minimizes the magnitude of voltage spikes.
There are two sets of critical components in a DC/DC
converter using the ISL6439. The switching components are
the most critical because they switch large amounts of
energy, and therefore tend to generate large amounts of
noise. Next are the small signal components which connect
to sensitive nodes or supply critical bypass current and
signal coupling.
A multi-layer printed circuit board is recommended. Figure 4
shows the connections of the critical components in the
converter. Note that capacitors CIN and COUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground
plane and make all critical component ground connections
with vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminals to the output inductor short. The power
plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
The switching components should be placed close to the
ISL6439 first. Minimize the length of the connections between
the input capacitors, CIN, and the power switches by placing
them nearby. Position both the ceramic and bulk input
capacitors as close to the upper MOSFET drain as possible.
Position the output inductor and output capacitors between the
upper MOSFET and lower MOSFET and the load.
9
CPVOUT
CBP
GND
CIN
D1
BOOT
CBOOT
Q1
UGATE
PHASE
Q2
LGATE
COMP
LOUT
PHASE
C2
VOUT
COUT
LOAD
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
300kHz or 600kHz, the resulting current transitions from one
device to another cause voltage spikes across the
interconnecting impedances and parasitic circuit elements.
These voltage spikes can degrade efficiency, radiate noise
into the circuit, and lead to device overvoltage stress.
Careful component layout and printed circuit board design
minimizes the voltage spikes in the converters.
C1
R2
R1
FB
R4
C3 R3
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Position the bypass capacitor, CBP, close to
the VCC pin with a via directly to the ground plane. Place the
PWM converter compensation components close to the FB
and COMP pins. The feedback resistors for both regulators
should also be located as close as possible to the relevant
FB pin with vias tied straight to the ground plane as required.
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (VE/A) is compared with
the oscillator (OSC) triangular wave to provide a pulsewidth modulated (PWM) wave with an amplitude of VIN at
the PHASE node. The PWM wave is smoothed by the output
filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A . This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR . The DC Gain of
FN9057.6
September 15, 2015
ISL6439, ISL6439A
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage VOSC .
VIN
DRIVER
OSC
PWM
COMPARATOR
LO
+
VOSC
DRIVER
PHASE
CO
REFERENCE
DETAILED COMPENSATION COMPONENTS
ZFB
C1
C2
VOUT
ZIN
C3
R2
R3
R1
COMP
FB
+
1
F Z2 = ------------------------------------------------------2 x  R 1 + R 3  x C 3
1
F P2 = -----------------------------------2 x R 3 x C 3
Figure 6 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at FP2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 6 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
ZIN
ERROR
AMP
1
F P1 = -------------------------------------------------------- C 1 x C 2
2 x R 2 x  ----------------------
 C1 + C2 
(EQ. 5)
VE/A
+
1
F Z1 = ---------------------------------2  R 2  C 2
VOUT
ESR
(PARASITIC)
ZFB
Compensation Break Frequency Equations
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
ISL6439
REFERENCE
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
1
F LC = -----------------------------------------2 x L O x C O
FZ1
1
F ESR = ------------------------------------------2 x ESR x C O
FZ2
FP1
FP2
100
OPEN LOOP
ERROR AMP GAIN
 V IN 
20 log  ----------------
 V OSC
80
(EQ. 4)
1. Pick gain (R2/R1) for desired converter bandwidth.
2. Place first zero below filter’s double pole (~75% FLC).
3. Place second zero at filter’s double pole.
4. Place first pole at the ESR zero.
5. Place second pole at half the switching frequency.
6. Check gain against error amplifier’s open-loop gain.
GAIN (dB)
60
The compensation network consists of the error amplifier
(internal to the ISL6439) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180 degrees. The expressions in Equation 5 relate the
compensation network’s poles, zeros and gain to the
components (R1 , R2 , R3 , C1 , C2 , and C3) in Figure 5. Use
these guidelines for locating the poles and zeros of the
compensation network:
40
COMPENSATION
GAIN
20
0
-20
R2
20 log  --------
 R1
-40
MODULATOR
GAIN
-60
10
100
FLC
1K
LOOP GAIN
FESR
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
Charge Pump Capacitor Selection
A capacitor across pins CT1 and CT2 is required to create
the proper bias voltage for the ISL6439 when operating the
IC from 3.3V. Selecting the proper capacitance value is
important so that the bias current draw and the current
required by the MOSFET gates do not overburden the
7. Estimate phase margin - repeat if necessary.
10
FN9057.6
September 15, 2015
ISL6439, ISL6439A
capacitor. A conservative approach is presented in
Equation 6.
I BiasAndGate
C PUMP = ------------------------------------  1.5
V CC  f s
(EQ. 6)
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern digital ICs can produce high transient load slew
rates. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (Effective Series Resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the expressions in Equation 7:
I =
VIN - VOUT
fs x L
x
VOUT
VIN
VOUT = I x ESR
(EQ. 7)
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
11
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6439 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The expressions
in Equation 8 give the approximate response time interval for
application and removal of a transient load:
tRISE =
L x ITRAN
VIN - VOUT
tFALL =
L x ITRAN
VOUT
(EQ. 8)
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q1 and the source of Q2 .
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
The maximum RMS current required by the regulator may be
closely approximated through Equation 9:
I RMS
MAX
=
V OUT 
V IN – V OUT V OUT 2
2
1
--------------  I OUT
+ ------   -----------------------------  -------------- 

V IN
V IN  
12  L  f s
MAX
(EQ. 9)
For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
FN9057.6
September 15, 2015
ISL6439, ISL6439A
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
MOSFET Selection/Considerations
The ISL6439 requires two N-Channel power MOSFETs.
These should be selected based upon rDS(ON) , gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor. The switching
losses seen when sourcing current will be different from the
switching losses seen when sinking current. When sourcing
current, the upper MOSFET realizes most of the switching
losses. The lower switch realizes most of the switching losses
when the converter is sinking current (see equations on next
page). These equations assume linear voltage-current
transitions and do not adequately model power loss due the
reverse-recovery of the upper and lower MOSFET’s body
diode. The gate-charge losses are dissipated by the ISL6439
and don't heat the MOSFETs. However, large gate-charge
increases the switching interval, tSW which increases the
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
Losses while Sourcing current
2
1
P UPPER = Io  r DS  ON   D + ---  Io  V IN  t SW  f s
2
PLOWER = Io2 x rDS(ON) x (1 - D)
Losses while Sinking current
PUPPER = Io2 x rDS(ON) x D
2
1
P LOWER = Io  r DS  ON    1 – D  + ---  Io  V IN  t SW  f s
2
Where: D is the duty cycle = VOUT / VIN ,
tSW is the combined switch ON and OFF time, and
fs is the switching frequency.
Given the reduced available gate bias voltage (5V), logiclevel or sub-logic-level transistors should be used for both NMOSFETs. Caution should be exercised with devices
exhibiting very low VGS(ON) characteristics. The shootthrough protection present aboard the ISL6439 may be
circumvented by these MOSFETs if they have large parasitic
impedences and/or capacitances that would inhibit the gate
of the MOSFET from being discharged below its threshold
level before the complementary MOSFET is turned on.
12
Bootstrap Component Selection
External bootstrap components, a diode and capacitor, are
required to provide sufficient gate enhancement to the upper
MOSFET. The internal MOSFET gate driver is supplied by
the external bootstrap circuitry as shown in Figure 7. The
boot capacitor, CBOOT, develops a floating supply voltage
referenced to the PHASE pin. This supply is refreshed each
cycle, when DBOOT conducts, to a voltage of CPVOUT less
the boot diode drop, VD, plus the voltage rise across
QLOWER.
CPVOUT
DBOOT
+
VD
-
VIN
BOOT
CBOOT
ISL6439
UGATE
QUPPER
PHASE
+
LGATE
NOTE:
VG-S = VCC -VD
QLOWER
NOTE:
VG-S = VCC
GND
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
Just after the PWM switching cycle begins and the charge
transfer from the bootstrap capacitor to the gate capacitance
is complete, the voltage on the bootstrap capacitor is at its
lowest point during the switching cycle. The charge lost on
the bootstrap capacitor will be equal to the charge
transferred to the equivalent gate-source capacitance of the
upper MOSFET as shown:
Q GATE = C BOOT   V BOOT1 – V BOOT2 
(EQ. 10)
where QGATE is the maximum total gate charge of the upper
MOSFET, CBOOT is the bootstrap capacitance, VBOOT1 is
the bootstrap voltage immediately before turn-on, and
VBOOT2 is the bootstrap voltage immediately after turn-on.
The bootstrap capacitor begins its refresh cycle when the gate
drive begins to turn-off the upper MOSFET. A refresh cycle
ends when the upper MOSFET is turned on again, which
varies depending on the switching frequency and duty cycle.
The minimum bootstrap capacitance can be calculated by
rearranging the Equation 10 and solving for CBOOT.
Q GATE
C BOOT = ----------------------------------------------------V BOOT1 – V
BOOT2
(EQ. 11)
Typical gate charge values for MOSFETs considered in
these types of applications range from 20nC to 100nC.
Since the voltage drop across QLOWER is negligible,
VBOOT1 is simply VCPVOUT - VD. A schottky diode is
FN9057.6
September 15, 2015
ISL6439, ISL6439A
charge loss. Otherwise, the recovery charge, QRR, would
have to be added to the gate charge of the MOSFET and
taken into consideration when calculating the minimum
bootstrap capacitance.
recommended to minimize the voltage drop across the
bootstrap capacitor during the on-time of the upper
MOSFET. Initial calculations with VBOOT2 no less than 4V
will quickly help narrow the bootstrap capacitor range.
For example, consider an upper MOSFET is chosen with a
maximum gate charge, Qg, of 100nC. Limiting the voltage
drop across the bootstrap capacitor to 1V results in a value
of no less than 0.1F. The tolerance of the ceramic capacitor
should also be considered when selecting the final bootstrap
capacitance value.
ISL6439 DC/DC Converter Application
Circuit
Figure 8 shows an application circuit of a DC/DC Converter.
Detailed information on the circuit, including a complete
Bill-of-Materials and circuit board description, can be found
in the ISL6439 Application Note.
A fast recovery diode is recommended when selecting a
bootstrap diode to reduce the impact of reverse recovery
3.3V
C1
0.1F
GND
11
TP1
4
C2
1000pF
U1
VCC
OCSET
CT1
C3
6
ISL6439
C4
0.22F
CPVOUT
5
10
1
ENABLE
3
C5
10F
Ceramic
D1
CT2
BOOT
CPGND
UGATE
GND
PHASE
9
R1
9.76k
TP3
ENABLE
LGATE
COMP
13
14
C7
0.1F
L1
12
2
C8,9
7
C10
R3
33pF
R2
2.5V @ 5A
Q1
FB
8
C6
1F
C11
2.26k
R4
6.49k 5600pF
R5
1.07k
124
C12
8200pF
GND
FIGURE 8. 3.3V to 2.5V 5A DC/DC CONVERTER
Component Selection Notes:
C3,8,9 - Each 150F, Panasonic EEF-UE0J151R or Equivalent.
D1 - 30mA Schottky Diode, MA732 or Equivalent
L1 - 1H Inductor, Panasonic P/N ETQ-P6F1ROSFA or Equivalent.
Q1 - Fairchild MOSFET; ITF86110DK8.
13
FN9057.6
September 15, 2015
ISL6439, ISL6439A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
September 15, 2015
FN9057.6
CHANGE
Updated Ordering Information on page 2.
Added Revision History and About Intersil sections.
Updated Package Outline Drawing M14.15 to the latest revision changes are as follows:
-Add land pattern and moved dimensions from table onto drawing.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN9057.6
September 15, 2015
ISL6439, ISL6439A
Package Outline Drawing
L16.5x5B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 02/08
4X 2.4
5.00
12X 0.80
A
B
13
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
16
12
5.00
1
3 . 10 ± 0 . 15
9
(4X)
4
0.15
5
8
TOP VIEW
0.10 M C A B
+0.15
16X 0 . 60
-0.10
4 0.33 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
1.00 MAX
C
BASE PLANE
SEATING PLANE
0.08 C
( 4 . 6 TYP )
(
SIDE VIEW
( 12X 0 . 80 )
3 . 10 )
C
( 16X 0 .33 )
( 16 X 0 . 8 )
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
15
FN9057.6
September 15, 2015
ISL6439, ISL6439A
Package Outline Drawing
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
8.65
A 3
4
0.10 C A-B 2X
6
14
DETAIL"A"
8
0.22±0.03
D
6.0
3.9
4
0.10 C D 2X
0.20 C 2X
7
PIN NO.1
ID MARK
5
0.31-0.51
B 3
(0.35) x 45°
4° ± 4°
6
0.25 M C A-B D
TOP VIEW
0.10 C
1.75 MAX
H
1.25 MIN
0.25
GAUGE PLANE C
SEATING PLANE
0.10 C
0.10-0.25
1.27
SIDE VIEW
(1.27)
DETAIL "A"
(0.6)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Datums A and B to be determined at Datum H.
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5. The pin #1 indentifier may be either a mold or mark feature.
(1.50)
6. Does not include dambar protrusion. Allowable dambar protrusion
shall be 0.10mm total in excess of lead width at maximum condition.
7. Reference to JEDEC MS-012-AB.
TYPICAL RECOMMENDED LAND PATTERN
16
FN9057.6
September 15, 2015
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