DATASHEET

ISL6410, ISL6410A
®
Data Sheet
September 17, 2004
FN9149.3
Single Synchronous Buck Regulators
with Integrated FET
Features
The ISL6410, ISL6410A are synchronous current-mode
PWM regulators designed to provide a total DC-DC solution
for microcontrollers, microprocessors, CPLDs, FPGAs, core
processors/BBP/MAC, and ASICs. The ISL6410 should be
selected for applications using 3.3V ±10% as an input
voltage and the ISL6410A in applications requiring 5.0V
±10%.
• PWM Fixed Output Voltage Options
- 1.8V, 1.5V or 1.2V with ISL6410 (VIN = 3.3V)
- 3.3V, 1.8V or 1.2V with ISL6410A (VIN = 5.0V)
• Fully Integrated Synchronous Buck Regulator
These synchronous current mode PWM regulators have
integrated N- and P-Channel power MOSFETs and provide
pre-set pin programmable outputs. Synchronous rectification
with internal MOSFETs is used to achieve higher efficiency
and a reduced external component count. The operating
frequency of 750kHz typical allows the use of small inductor
and capacitor values. The device can be synchronized to an
external clock signal in the range of 500kHz to 1MHz. A
power good signal “PG” is generated when the output
voltage falls outside the regulation limits. Other features
include overcurrent protection and thermal overload
shutdown. The ISL6410, ISL6410A are available in an
MSOP 10 lead package.
• Stable with Small Ceramic Output Capacitors
• High Conversion Efficiency
• Extensive Circuit Protection and Monitoring features
- Overvoltage, UVLO
- Overcurrent
- Thermal Shutdown
• Available in MSOP and QFN packages
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
PKG.
DWG. #
Applications
• CPUs, DSP, CPLDs, FPGAs
ISL6410IR
-40 to 85
16 Ld 4x4 QFN
L16.4x4
ISL6410IRZ (Note)
-40 to 85
16 Ld 4x4 QFN
(Pb-free)
L16.4x4
ISL6410IU
-40 to 85
10 Ld MSOP
M10.118
ISL6410IUZ (Note)
-40 to 85
10 Ld MSOP (Pb-free) M10.118
ISL6410AIR
-40 to 85
16 Ld 4x4 QFN
L16.4x4
• Generic 5V to 3.3V Conversion
ISL6410AIRZ (Note)
-40 to 85
16 Ld 4x4 QFN
(Pb-free)
L16.4x4
Pinouts
ISL6410AIU
-40 to 85
10 Ld MSOP
M10.118
ISL6410AIUZ (Note)
-40 to 85
10 Ld MSOP (Pb-free) M10.118
• DVD and DSL applications
PVCC
1
10 PGND
PGND
ISL6410 (QFN)
TOP VIEW
L
ISL6410 (MSOP)
TOP VIEW
PVCC
VIN
2
9
L
16
15
14
13
GND
3
8
EN
PG
4
7
FB
5
6
1
12 NC
SYNC
CT
2
11 RESET
VSET
GND
3
10 EN
PG
4
9
5
6
7
8
PG
VIN
VSET
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
• WLAN Cards
VIN
*For tape and reel, add “-T”, “-TK” or “-T5K” suffix.
1
• ASICs
NC
PACKAGE
FB
TEMP.
RANGE (°C)
• Ultra-Compact DC-DC Converter Design
• Pb-Free Packaging Available
Ordering Information
PART NUMBER*
• Continuous Output Current . . . . . . . . . . . . . . . . . . 600mA
SYNC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram for MSOP Version
VIN
0.1µF
10µF
PVCC
2
2
VIN
3
GND
1
CURRENT
SENSE
SLOPE
COMPENSATION
SOFT
START
EN
EA
PWM
OVERCURRENT,
OVERVOLTAGE
LOGIC
GM
L1
8.2µH
GATE
DRIVE
L
9
VOUT
COMPENSATION
PGND
7
SYNC
6
VSET
10
750kHz
OSCILLATOR
POWER GOOD
PWM
VOUT
UVLO
8
PWM
REFERENCE
0.45V
EN
FB
4
PG
NOTES:
1. VIN is 3.3V for ISL6410 and 5.0V for ISL6410A.
2. VSET in the above schematic is connected to VIN, so the VOUT is 1.8V for ISL6410 and 3.3V for ISL6410A.
5
ISL6410, ISL6410A
10µF
Functional Block Diagram for QFN Version
VIN
0.1µF
10µF
PVCC
3
CURRENT
SENSE
16 VIN
3
15
SLOPE
COMPENSATION
SOFT
START
GND
EN
EA
L1
8.2µH
PWM
OVERCURRENT,
OVERVOLTAGE
LOGIC
GM
L
GATE
DRIVE
14
VOUT
COMPENSATION
PGND
9
SYNC
7
VSET
13
750kHz
OSCILLATOR
POWER GOOD
PWM
VIN
11
VOUT
RESET
BLOCK
UVLO
RESET
PWM
REFERENCE
0.45V
10 EN
FB
4
PG
8
PG
2 C
T
NOTES:
1. VIN is 3.3V for ISL6410 and 5.0V for ISL6410A.
2. VSET in the above schematic is connected to VIN, so the VOUT is 1.8V for ISL6410 and 3.3V for ISL6410A.
5
ISL6410, ISL6410A
10µF
ISL6410, ISL6410A
Typical Application Schematics
VIN
3.3V
±10%
CIN
10µF
0.1µF
2 VIN
L1
8.2µH
PGND 10
1 PVCC
3 GND
VOUT
1.8V
L 9
ISL6410
EN 8
4 PG
SYNC 7
5 FB
VSET 6
COUT
10µF
FIGURE 1. SCHEMATIC USING THE ISL6410 MSOP
VIN
5.0V
±10%
CIN
10µF
0.1µF
1 PVCC
L1
12µH
PGND 10
2 VIN
ISL6410A
3 GND
VOUT
3.3V
L 9
EN 8
4 PG
SYNC 7
5 FB
VSET 6
COUT
10µF
FIGURE 2. SCHEMATIC USING THE ISL6410A MSOP
L1
+3.3V
VIN
+1.2V
VOUT
8.2µH
1
2
VIN
L
VIN
GND
PGND
16 15 14 13
1µF
PVCC
CIN
10µF
COUT
10µF
NC
12
GND
11
CT
RESET
U1
10
GND ISL6410IR
EN
9
4
PG
SYNC
17
EP
VSET
FB
5
PG
CT
0.01µF
C7
0.1µF
NC
3
6
7
8
FIGURE 3. SCHEMATIC USING THE ISL6410 QFN
4
RESET
BAR
ISL6410, ISL6410A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
SYNC, FB, VSET & Enable Input (Note 3) . . . . -0.3V to VCC+0.3V
ESD Classification (Human Body Model) . . . . . . . . . . . . . . . Class 2
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
MSOP Package (Note 4) . . . . . . . . . . .
128
NA
QFN Package (Notes 4, 5). . . . . . . . . .
45
7.5
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (10s, soldering . . . . . . . . . . . . . 260°C
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . -40°C to 85°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . -40°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. All voltages are with respect to GND.
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended operating conditions unless otherwise noted. VIN = 3.3V ±10% (ISL6410) or 5V ±10%
(ISL6410A), TA = 25°C (Note 6).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VIN (ISL6410)
3.0
3.3
3.6
V
VIN (ISL6410A)
4.5
5.0
5.5
V
VTR (ISL6410) Rising
2.62
2.68
2.73
V
VTF (ISL6410) Falling
2.53
2.59
2.64
V
VTR (ISL6410A) Rising
4.27
4.37
4.45
V
VTF (ISL6410A) Falling
4.1
4.22
4.32
V
VCC SUPPLY
Supply Voltage Range
Input UVLO Threshold
Quiescent Supply Current
IOUT = 0mA
-
2.3
-
mA
Shutdown Supply Current
EN = GND, TA = 25°C
-
5
10
µA
EN = GND, TA = 85°C
-
10
15
µA
Rising Threshold
-
150
-
°C
-
20
25
°C
ISL6410, VSET = L
-
1.2
-
V
ISL6410, VSET = H
-
1.8
-
V
ISL6410, VSET = OPEN
-
1.5
-
V
ISL6410A, VSET = L
-
1.2
-
V
ISL6410A, VSET = H
-
3.3
-
V
ISL6410A, VSET = OPEN
-
1.8
-
V
Thermal Shutdown Temperature (Note 7)
Thermal Shutdown Hysteresis (Note 7)
SYNCHRONOUS BUCK PWM REGULATOR
Output Voltage
Output Voltage Accuracy
IOUT = 3mA, TA = -40°C to 85°C
-1.5
-
+1.5
%
Line Regulation
IOUT = 3mA
-0.5
-
+0.5
%
Load Regulation
IOUT = 3mA to 600mA
-1.5
-
+1.5
%
Maximum Output Current
-
-
600
mA
Peak Output Current Limit
700
-
1300
mA
PMOS rDS(ON)
IOUT = 200mA
-
230
-
mΩ
NMOS rDS(ON)
IOUT = 200mA
-
230
-
mΩ
Efficiency
IOUT = 200mA, VIN = 3.3V, VO = 1.8V (ISL6410)
-
92
-
%
5
ISL6410, ISL6410A
Electrical Specifications
Recommended operating conditions unless otherwise noted. VIN = 3.3V ±10% (ISL6410) or 5V ±10%
(ISL6410A), TA = 25°C (Note 6). (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Efficiency
IOUT = 200mA, VIN = 5.0V, VO = 3.3V (ISL6410A)
-
93
-
%
Efficiency
IOUT = 600mA, VIN = 5.0V, VO = 3.3V (ISL6410A)
-
91
-
%
Soft-Start Time
4096 Clock Cycles @ 750kHz
-
5.5
-
ms
OSCILLATOR
Oscillator Frequency
620
750
860
kHz
Frequency Synchronization Range (fSYNC)
Clock signal on SYNC pin
500
-
1000
kHz
SYNC High Level Input Voltage
As % of VIN
70
-
-
%
SYNC Low Level Input Voltage
As % of VIN
-
-
30
%
Sync Input Leakage Current
SYNC = GND or VIN
-1
-
1
µA
20
-
60
%
+5.0
8.0
+10.5
%
-10.5
-8.0
-5.0
%
-
1
-
%
Duty Cycle of External Clock Signal (Note 7)
PGOOD (ISL6410 interfaces to 3.3V Logic, ISL6410A interfaces to 5.0V Logic)
Rising Threshold
1mA minimum source/sink
Falling Threshold
Rising/Falling Hysteresis
ENABLE
EN High Level Input Voltage
As % of VIN
70
-
-
%
EN Low Level Input Voltage
As % of VIN
-
-
30
%
EN Input Leakage Current
EN = GND or VIN
-1
1
µA
OVERVOLTAGE
Overvoltage Threshold
27
30
33
%
0.8VIN
-
-
V
-
-
0.3
V
RESET BLOCK SPECIFICATIONS
RESET (reset released)
ISL6410, ISOURCE = 500µA, VIN = 2.90V
RESET (reset asserted)
ISL6410, ISINK = 1.2mA, VIN = 2.50V
RESET Rising Threshold
ISL6410
2.74
2.78
2.81
V
RESET Falling Threshold
ISL6410
2.72
2.77
2.79
V
RESET (reset released)
ISL6410A, ISOURCE = 800µA, VIN = 4.70V
0.8VIN
-
-
V
RESET (reset asserted)
ISL6410A, ISINK = 3.2mA, VIN = 4.10V
-
-
0.4
V
RESET Rising Threshold
ISL6410A
4.5
4.58
4.64
V
RESET Falling Threshold
ISL6410A
4.47
4.55
4.61
V
RESET Threshold Hysteresis
ISL6410
-
20
-
mV
RESET Threshold Hysteresis
ISL6410A
-
30
-
mV
RESET Active Timeout Period (Note 8)
CT = 0.01mF
-
25
-
ms
VSET High Level Input
VIN-0.4V
-
-
V
VSET Low Level Input
-
-
0.4
V
VSET Open Level Input
-
VIN /2
-
V
VSET
NOTES:
6. Specifications at -40°C and +85°C are guaranteed by design, not production tested.
7. Guaranteed by design, not production tested.
8. The RESET Timeout period is linear with CT at a slope of 2.5ms/nF, thus a 10nF capacitor provides for 25ms.
6
ISL6410, ISL6410A
Pin Description
VIN - Supply voltage for the IC. It is recommended to place a
1µF decoupling capacitor as close as possible to the IC.
GND - Small signal ground for the PWM controller stage. All
internal control circuits are referenced to this pin.
PG - The Power good is an open-drain output. A pull-up
resistor should be connected between PG and VIN. It is
asserted active high when the output voltage reaches
94.5% of the nominal value.
FB - The Feedback pin is used to sense the output voltage,
and should be connected to VOUT for normal operation.
VSET - This pin is used to program the output voltages.
Refer to Table 1 below for details.
TABLE 1.
VSET
ISL6410
Vo
ISL6410A
Vo
High
1.8V
3.3V
Open (NC)
1.5V
1.8V
Low
1.2V
1.2V
SYNC - This pin is used for synchronization. The converter
switching frequency can be synchronized to an external
CMOS clock signal in the range of (500kHz to 1MHz).
EN - A logic high enables the converter, logic low forces the
device into shutdown mode reducing the supply current to
less than 10µA at 25°C. This pin should be pulled up to VCC
via a 10K resistor.
L - This pin is the drain junction of the internal power
MOSFETs and is to be connected to the external inductor.
PGND - Power ground. Connect all power grounds to this pin.
PVCC - This pin provides the Input supply for the internal
MOSFETs. It is recommended to place a 1µF decoupling
capacitor as close as possible to the IC.
CT - Timing capacitor connection to set the 25ms minimum
pulse width for the RESET signal.
RESET - The outputs of the reset supervisory circuit, which
monitors VIN. The IC asserts these RESET signals
whenever the supply voltage drops below a preset threshold
and keeps it asserted for at least 25ms after VCC (VIN) has
risen above the reset threshold. These outputs are pushpull. RESET is LOW when re-setting the microprocessor.
The PWM will continue to operate until VIN drops below the
UVLO threshold.
efficiency and reduced number of external components.
Operating frequency of 750kHz typical allows the use of
small inductor and capacitor values. The device can be
synchronized to an external clock signal in the range of
500kHz to 1MHz. The PG output indicates loss of regulation
on PWM output.
The PWM is based on the peak current mode control
topology with internal slope compensation. At the beginning
of each clock cycle, the high side P-channel MOSFET is
turned on. The current in the inductor ramps up and is
sensed via an internal circuit. On exceeding a preset limit the
high side switch is turned off causing the PWM comparator
to trip. This occurs whenever the output voltage is in
regulation or when the inductor current reaches the current
limit. After a minimum dead time to prevent shoot through
current, the low side N-channel MOSFET turns on and the
current ramps down. As the clock cycle is completed, the low
side switch turns off and the next clock cycle is initiated.
The control loop is internally compensated thus reducing the
amount of external components.
The switch current is internally sensed and the maximum
current limit is 1300mA peak.
Synchronization
The typical operating frequency for the converter is 750kHz.
It is possible to synchronize the converter to an external
clock frequency in the range of 500kHz to 1000kHz when an
external signal is applied to SYNC pin. The device will
automatically detect and synchronize to the rising edge of
the first clock pulse. If the clock signal is stopped, the
converter automatically switches back to the internal clock
and continues its operation without interruption. The switch
over will be initiated if no rising edge triggers are present on
the SYNC pin for a duration of four clock cycles.
Soft-Start
As the EN (Enable) pin goes high, the soft-start function will
generate an internal voltage ramp. This causes the start-up
current to slowly rise preventing output voltage overshoot
and high inrush currents. The soft-start duration is typically
5.5ms with 750kHz switching frequency. When the soft-start
is completed, the error amplifier will be connected directly to
the internal voltage reference.
Enable
Logic low on EN pin forces the PWM section into shutdown.
In the shutdown mode all the major blocks of the PWM
including power switches, drivers, voltage reference, and
oscillator are turned off.
Functional Description
Undervoltage Lockout
The ISL6410, ISL6410A is a synchronous buck regulator
with integrated N- and P-channel power MOSFET and
provides pre-set pin programmable outputs. Synchronous
rectification with internal MOSFETs is used to achieve higher
An undervoltage lockout circuit prevents the converter from
turning on when the voltage on VIN is less than the values
specified in the Input UVLO Threshold section of the
electrical specification.
7
ISL6410, ISL6410A
Power Good
Input Capacitor Selection
This output is asserted high when the PWM is enabled, and
Vout is within 8.0% typical of its final value, and is active low
outside this range. When disabled, the output turns active
low. It is recommended to leave the PG pin unconnected
when not used.
The input current to the buck converter is pulsed, and
therefore a low ESR input capacitor is required. This results
in good input voltage filtering and minimizes the interference
it causes to other circuits. The input capacitor should have a
minimum value of 10µF and a higher value can be selected
for improving input voltage filtering. The input capacitor
should be rated for the maximum input ripple current
calculated as:
PWM Overvoltage and Overcurrent Protection
The PWM output current is sampled at the end of each PWM
cycle, exceeding the overcurrent limit, causes a 4 bit
up/down counter to increment by one LSB. A normal current
state causes the counter to decrement by one LSB (the
counter will not however “rollover” or count below 0000).
When the PWM goes into overcurrent, the counter rapidly
reaches count 1111 and the PWM output is shut down and
the soft-start counter is reset. After 16 clocks the PWM
output is enabled and the soft-start cycle is started.
If Vout exceeds the overvoltage limit for 32 consecutive clock
cycles the PWM output is shut off and the soft-start cycle is
initiated.
No Load Operation
If there is no load connected to the output, the converter will
regulate the output voltage by allowing the inductor current
to reverse for a short period of time.
Output Capacitor Selection
For best performance, a low ESR output capacitor is
needed. Output voltages below 1.8V require a larger output
capacitor and ESR value to improve the performance and
stability of the converter. For 1.8V output applications, a
ceramic capacitor of 10µF or higher value with ESR ≤50mΩ
is recommended.
The RMS ripple current is calculated as:
Ceramic capacitors are preferred because of their low ESR
value. They are also less sensitive to voltage transients
when compared to tantalum capacitors. It is good practice to
place the input capacitor as close as possible to the input pin
of the IC for optimum performance.
Inductor Selection
The ISL6410 is an internally compensated device and hence
a minimum of 8.2µH must be used for the ISL6410 and a
minimum of 12µH for the ISL6410A. The selected inductor
must have a low DC resistance and a saturation current
greater than the maximum inductor current value can be
calculated from the equations below
Vo
1 – --------Vin
dIL = Vo × ------------------L×f
dIL = the peak to peak inductor current
L = the inductor value
f = the switching frequency
f = the switching frequency
The overall output ripple voltage is the sum of the voltage spike
caused by the output capacitor ESR and the voltage ripple
caused by charge and discharge of the output capacitor:
Vo
1 – --------Vin
1
∆Vo = Vo × ------------------- ×  ------------------------- + ESR
 8 × Co × f

L×f
Where the highest output voltage ripple occurs at the highest
input voltage VIN.
TABLE 2. RECOMMENDED OUTPUT CAPACITORS
10µF
D = Duty Cycle
where
L = the inductor value
ESR
(mΩ)
The worst case RMS ripple current occurs at D = 0.5 and is
calculated as: Irms = Io/2.
IL max = Io max + dIL
--------2
Vo
1 – --------Vin
1
------------------ × ----------------I RMS ( Co ) = Vo ×
L×f
2× 3
CAPACITOR
VALUE
Vo
Vo
I RMS = Io ( max ) × --------- ×  1 – ---------
Vin 
Vin
COMPONENT
SUPPLIER
<50 AVX 08056D106KAT2A
8
COMMENTS
Ceramic
ILmax = the max inductor current
TABLE 3. RECOMMENDED INDUCTORS
COMPONENT
SUPPLIER
INDUCTOR VALUE
DCR (mΩ)
8.2µH
75
Coilcraft
MSS6122-822MX
12µH
100
Coilcraft
MSS6122-123MX
ISL6410, ISL6410A
Layout Considerations
As in all switching power supplies, the layout is an important
step in the design process, more so at high peak currents
and switching frequencies. Improper layout practice will give
rise to Stability and EMI issues. It is recommended that wide
and short traces are used for the main current paths. The
input capacitor should be placed as close as possible to the
IC pins. This applies to the output inductor and capacitor as
well. The analog ground, GND, and the power ground,
PGND, need to be separated. Use a common ground node
to minimize the effects of ground noise.
Performance Curves and Waveforms
100
100
VOUT = 1.8V
IOUT = 200mA
90
VOUT = 1.5V
EFFICIENCY (%)
EFFICIENCY (%)
90
VOUT = 1.2V
80
70
60
50
IOUT = 600mA
80
70
60
50
100
50
1000
2.9
3.1
3.3
VIN INPUT VOLTAGE (V)
IOUT LOAD CURRENT (mA)
FIGURE 4. ISL6410 EFFICIENCY vs LOAD CURRENT
FIGURE 5. ISL6410 VIN vs EFFICIENCY
100
100
VOUT = 3.3V
IOUT = 200mA
90
VOUT = 1.8V
80
EFFICIENCY (%)
EFFICIENCY (%)
90
VOUT = 1.2V
70
60
50
50
3.5
IOUT = 600mA
80
70
60
100
1000
IOUT LOAD CURRENT (mA)
FIGURE 6. ISL6410A EFFICIENCY vs LOAD CURRENT
9
50
4.4
4.6
4.8
5.0
VIN (V)
5.2
5.4
FIGURE 7. ISL6410A EFFICIENCY vs VIN
5.6
ISL6410, ISL6410A
Performance Curves and Waveforms
(Continued)
780
SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
800
790
780
770
760
750
-40
-15
10
35
TEMPERATURE (°C)
60
FIGURE 8. ISL6410 OSCILLATOR FREQUENCY vs
TEMPERATURE
85
770
760
750
740
730
-40
-15
10
35
TEMPERATURE (°C)
60
85
FIGURE 9. ISL6410A OSCILLATOR FREQUENCY vs
TEMPERATURE
CH1 = Top, CH2 = Middle, CH4 = Bottom, where applicable
VOUT
VOUT
L PIN VOLTAGE
L PIN VOLTAGE
L1 CURRENT
L1 CURRENT
VIN = 5.0V, VOUT = 1.2V, IOUT = 0.5A
0.5µs/DIV
CH1 = 0.1V/DIV, CH2 = 2V/DIV CH4 = 200mA/DIV
0.5µs/DIV
CH1 = 0.1V/DIV, CH2 = 2V/DIV CH4 = 200mA/DIV
FIGURE 10. SWITCHING WAVEFORM FOR ISL6410
FIGURE 11. SWITCHING WAVEFORM FOR ISL6410A
VOUT
VOUT
IOUT
IOUT
VIN = 3.3V, VOUT = 1.2V
0.5ms/DIV
CH1 = 0.2V/DIV, CH4 = 200mA/DIV
FIGURE 12. TRANSIENT LOAD WAVEFORM FOR ISL6410
10
VIN = 5.0V, VOUT = 1.2V
0.5ms/DIV
CH1 = 0.1V/DIV, CH4 = 200mA/DIV
FIGURE 13. TRANSIENT LOAD WAVEFORM FOR ISL6410A
ISL6410, ISL6410A
Performance Curves and Waveforms
(Continued)
VOUT
VOUT
VIN = 3.3V, VOUT = 1.2V
VIN = 5.0V, VOUT = 1.2V
1µs/DIV
CH1 = 20mV/DIV
1µs/DIV
CH1 = 20mV/DIV
FIGURE 14. RIPPLE WAVEFORM FOR ISL6410
FIGURE 15. RIPPLE WAVEFORM FOR ISL6410A
-40
-40
VIN = 3.3V, VOUT = 1.2V
VIN = 5.0V, VOUT = 1.2V
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-100
-110
-110
-120
-120
NOISE LEVEL 761kHz = -54.0dBm
CENTER 2.75MHz, SPAN = 4.5MHz
FIGURE 16. SWITCHING HARMONICS AND NOISE FOR
ISL6410
11
NOISE LEVEL 732kHz = -65.3dBm
CENTER 2.75MHz, SPAN = 4.5MHz
FIGURE 17. SWITCHING HARMONICS AND NOISE FOR
ISL6410A
ISL6410, ISL6410A
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
A3
b
0.23
D
0.28
9
0.35
5, 8
4.00 BSC
D1
D2
9
0.20 REF
-
3.75 BSC
1.95
2.10
9
2.25
7, 8
E
4.00 BSC
-
E1
3.75 BSC
9
E2
1.95
e
2.10
2.25
7, 8
0.65 BSC
-
k
0.25
-
-
-
L
0.50
0.60
0.75
8
L1
-
-
0.15
10
N
16
2
Nd
4
3
Ne
4
3
P
-
-
0.60
9
θ
-
-
12
9
Rev. 5 5/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
12
ISL6410, ISL6410A
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
SEATING
PLANE -CA
4X θ
A2
A1
b
-H-
0.10 (0.004)
L
SEATING
PLANE
C
MIN
MAX
MIN
MAX
NOTES
A
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.007
0.011
0.18
0.27
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.020 BSC
0.20 (0.008)
C
C
a
SIDE VIEW
CL
E1
0.20 (0.008)
C D
-
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
-A-
0.50 BSC
E
L1
e
D
SYMBOL
e
L1
MILLIMETERS
0.95 REF
10
R
0.003
R1
-
10
-
0.07
0.003
-
θ
5o
15o
α
0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
-B-
Rev. 0 12/02
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B -
to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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13
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