ISL65426EVAL1Z Evaluation Kit ® Application Note July 24, 2007 6A Dual Synchronous Buck Regulator with Integrated MOSFETs Features The ISL65426EVAL1Z is a high efficiency dual output monolithic synchronous buck converter operating over an input voltage range of 2.375V to 5.5V. This single chip power solution provides two output voltages, which are selectable or externally adjustable from 1V to 80% of the supply voltage while delivering up to 6A of total output current. The two PWMs are synchronized 180° out of phase reducing the RMS input current and ripple voltage. • Fixed Frequency: 1MHz The ISL65426EVAL1Z switches at a fixed frequency of 1MHz and utilizes current-mode control with integrated compensation to minimize the size and number of external components and provide excellent transient response. The internal synchronous power switches are optimized for good thermal performance, high efficiency, and eliminate the need for an external Schottky diode. A unique power block architecture allows partitioning of six 1A capable blocks to support one of four configuration options. One master power block is associated with each synchronous converter channel. Four floating slave power blocks allow the user to assign them to either channel. Proper external configuration of the power blocks is verified internally prior to soft-start initialization. Independent enable inputs allow for synchronization or sequencing soft-start intervals of the two converter channels. A third enable input allows additional sequencing for multi input bias supply designs. Individual power good indicators (PG1, PG2) signal when output voltage is within regulation window. The ISL65426EVAL1Z integrates protection for both synchronous buck regulator channels. The fault conditions include overcurrent, undervoltage, and IC thermal monitor. High integration contained in a thin Quad Flat No-lead (QFN) package makes the ISL65426EVAL1Z an ideal choice to power many of today’s small form factor applications. A single chip solution for large scale digital ICs, like field programmable gate arrays (FPGA), requiring separate core and I/O voltages. AN1281.1 • High Efficiency: Up to 95% • Operates From 2.375V to 5.5V Supply • ±1% Reference • Flexible Output Voltage Options - Programmable 2-Bit VID Input - Adjustable Output From 0.6V to 4.0V • User Partitioned Power Blocks • Ultra-Compact DC/DC Converter Design • PWMs Synchronized 180° Out of Phase • Independent Enable Inputs and System Enable • Stable All Ceramic Solutions • Excellent Dynamic Response • Independent Output Digital Soft-Start • Power Good Output Voltage Monitor • Short-Circuit and Thermal-Overload Protection • Overcurrent and Undervoltage Protection • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • FPGA, CPLD, DSP, and CPU Core and I/O Voltages - Xilinx Spartan IIITM, Virtex IITM, Virtex II ProTM, Virtex 4TM - Altera StratixTM, Stratix IITM, CycloneTM, Cyclone IITM - Actel FusionTM, LatticeSCTM, LatticeECTM • Low-Voltage, High-Density Distributed Power Systems • Point-of-Load Regulation • Distributed Power Systems • Set-Top Boxes. Ordering Information PART NUMBER (Note) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISL65426HRZ* ISL65426 HRZ -10 to +100 50 Ld QFN L50.5x10 ISL65426IRZA* ISL65426 IRZ L50.5x10 -40 to +85 50 Ld QFN *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1281 Pinout PG2 FB2 ISET2 PG1 EN EN2 EN1 FB1 ISL65426 (50 LD QFN) TOP VIEW 50 49 48 47 46 45 44 43 PGND 1 42 PGND PGND 2 41 PGND PGND 3 40 PGND PGND 39 PGND 4 LX1 5 38 LX6 LX1 6 37 LX6 PVIN1 7 36 PVIN6 PGND PVIN2 8 35 PVIN5 LX2 9 34 LX5 PGND 10 33 PGND PGND 11 32 PGND LX3 12 31 LX4 PVIN3 13 30 PVIN4 VCC 14 29 PGND VCC 15 28 PGND VCC 16 27 GND PGND 17 26 GND PGND PGND V2SET2 V2SET1 ISET1 V1SET2 PGND 2 V1SET1 18 19 20 21 22 23 24 25 AN1281.1 July 24, 2007 R7 R14 2.43K 2 D2 10K R13 2 D1 GREEN 1 R9 10K GREEN 3 TP7 R11 2N7002 1 0 Q3 3 2 R17 ENABLE1 R12 0 1 0 2N7002 Q4 3 2 0 C13 1 10UF 2 C16 10UF C11 1 1 10UF TP3 2 GND VCC C10 1 1 10UF TP4 1 VCC 2 Q1 C12 1 2N7002 1 2 R8 R6 DNP DNP CERAMIC AND SP CAP FOOTPRINTS 1 3 P1 1SW1 2 3 P1 1SW2 P1 3 SW31 P2 2 C7 1UF 100UF 1 2 3 4 5 2 P2 V1SET1 C8 C9 CERAMIC AND SP CAP FOOTPRINTS VCC VCC 0 R3 VOUT2 L2 1.0UH 1 PHASE2 PHASE1 D2D1 FB1 EN1 EN2 EN ISET2 PG1 PG2 FB2 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 18 19 20 21 22 23 24 25 51 PGND PGND PGND PGND LX6 LX6 PVIN6 PVIN5 LX5 PGND PGND LX4 PVIN4 PGND PGND GND GND 2 0 PGND PGND PGND PGND LX1 LX1 PVIN1 PVIN2 LX2 PGND U1 PGND LX3 PVIN3 VCC VCC ISL65426 VCC PGND EP PGND V1SET1 V1SET2 ISET1 V2SET1 V2SET2 PGND PGND D1 R16 0.1UF C6 100UF 1 C5 VCC 2 1 C4 2 PHASE1 C1 TP1 C3 2 5 4 3 GND L1 1.0UH 1 1 0 R1 VOUT1 100UF 1 SP1 1UF TP2 C2 VOUT1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 V2SET1 2 P1 3 SW41 AN1281.1 July 24, 2007 FIGURE 1. ISL65426EVAL1Z REV A CIRCUIT SCHEMATIC VCC 1 Application Note 1281 R2 50 49 48 47 46 45 44 43 10K 2 2 P2 C14 P1 1000PF 3 1SW5 2 VCC Q2 1 10K R4 TP8 3 1 C15 3 P2 R15 2 1SW6 2 ENABLE2 0 2N7002 1000PF P1 1 R18 3 1 ENABLE 2.43K R5 10K OPEN VCC R10 VCC Application Note 1281 TABLE 1. SWITCH TABLE SW1 V1SET1 L Connect to GND. H Connect to VCC. SW2 Recommended Equipment • 0V to 6V power supply with at least 10A source current capability, battery, or notebook AC adapter. • Two electronic loads capable of sinking current up to 5A. V1SET2 • Digital multimeters (DMMs). 1 Connect to GND. • 100MHz quad-trace oscilloscope. 2 Connect to VCC. Quick Start SW3 V2SET1 1 Connect to GND. 3 Connect to VCC. SW4 2. Turn on the input power supply. 3. Turn on EN1 and EN2. V2SET2 1 Connect to GND. 2 Connect to VCC. SW5 1. Ensure that the circuit is correctly connected to the supply and loads prior to applying any power. 4. Verify the outputs voltages are correct based following Table 2: TABLE 2. OUTPUT VOLTAGE PROGRAMMING EN1 VOUT1 V1SET1 V1SET2 VOUT2 V2SET1 V2SET2 1 Connect to GND. 1.8V 1 1 3.3V 1 1 2 Connect to VCC. 1.5V 0 1 2.5V 0 1 1.2V 1 0 1.8V 1 0 0.6V 0 0 0.6V 0 0 SW6 EN2 1 Connect to GND. 2 Connect to VCC. 5. Load VOUT1 up to 4A. 6. Load VOUT2 up to 2A. 4 AN1281.1 July 24, 2007 Application Note 1281 ISL65426EVAL1Z BOM REF DES QTY PART NUMBER C1 1 0.1µF Ceramic Capacitor, 16V, 10%, X7R, 0603 various C10, C11, C12, C13 4 10µF Ceramic Capacitor, 6.3V, 20%, X7R, 1206 various C14, C15 2 1000pF Ceramic Capacitor, 50V, 10%, X7R, 0603 various C16 0 2200µF Electrolytic Capacitor, 6.3V, 20%, thru-hole Nichicon C2, C7 2 1µF Ceramic Capacitor, 10V, 10%, X5R, 0603 various C3, C6, C8 3 100µF Ceramic Capacitor, 6.3V, 20%, X5R, 1210 TDK UHN0J222MPP C3225X5R0J107M VALUE C4, C5, C9 DESCRIPTION MANUFACTURER SP Cap Place Holder D1, D2 2 LTST-C170CKT L1, L2 2 FDV0630-1R0M Q1, Q2, Q3, Q4 4 2N7002 R1, R3, R7, R11, R12, R17, R18 7 R10, R14 R16 Green LED, 0805 1.0µH Power Inductor, 20%, 7.7A, 10m DCR, SMD TOKO N-Channel MOSFET, 60V, 115mA,SOT23 various 0 Chip Resistor, 0603 various 2 2.43k Chip Resistor, 0603 various 1 5 Chip Resistor, 0603 various DNP Chip Resistor, 0603 various R2, R6 R4 1 2.21k Chip Resistor, 0603 various R5, R8, R9, R13, R15 5 10k Chip Resistor, 0603 various SP1, SP2 2 1314353-00 Probe Socket, Thru Hole Tektronics SW1, SW2, SW3, SW4, SW5, SW6 6 GT11MSCKE Toggle Switch, Mini SPDT, SMD C&K TP1, TP2, TP3, TP4, TP5, TP6 6 1514-2 Turret Test Point, Thru Hole Keystone TP7, TP8 2 SPCJ-123-01 Small Test Point, Thru Hole Jolo U1 1 ISL65426CRZ Dual Controller 50 Ld QFN Intersil 5 AN1281.1 July 24, 2007 Application Note 1281 FIGURE 2. TOP LAYER COMPONENTS 6 AN1281.1 July 24, 2007 Application Note 1281 FIGURE 3. TOP LAYER ETCH 7 AN1281.1 July 24, 2007 Application Note 1281 FIGURE 4. SECOND LAYER ETCH 8 AN1281.1 July 24, 2007 Application Note 1281 FIGURE 5. THIRD LAYER ETCH 9 AN1281.1 July 24, 2007 Application Note 1281 FIGURE 6. BOTTOM LAYER ETCH (MIRRORED) Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 10 AN1281.1 July 24, 2007