DATASHEET

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Data Sheet
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ISL6612B, ISL6613B
®
May 1, 2012
Advanced Synchronous Rectified Buck
MOSFET Drivers with Pre-POR OVP
The ISL6612B and ISL6613B are high frequency MOSFET
drivers specifically designed to drive upper and lower power
N-Channel MOSFETs in a synchronous rectified buck
converter topology. These drivers combined with HIP63xx or
ISL65xx Multi-Phase Buck PWM controllers and N-Channel
MOSFETs form complete core-voltage regulator solutions for
advanced microprocessors.
The ISL6612B drives the upper gate to above rising VCC
POR (7V), while the lower gate can be independently driven
over a range from 5V to 12V. The ISL6613B drives both
upper and lower gates over a range of 5V to 12V. This drivevoltage provides the flexibility necessary to optimize
applications involving trade-offs between gate charge and
conduction losses. These drivers are optimized for POL
DC/DC Converters for IBA Systems.
FN9205.4
Features
• Pin-to-pin Compatible with HIP6601 SOIC family
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Low VCC Rising Threshold (7V) for IBA Applications.
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
- Auto-zero of rDS(ON) Conduction Offset Effect
• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 2MHz)
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Three-State PWM Input for Output Stage Shutdown
An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the dead
time. These products add an overvoltage protection feature
operational before VCC exceeds its turn-on threshold, at
which the PHASE node is connected to the gate of the low
side MOSFET (LGATE). The output voltage of the converter
is then limited by the threshold of the low side MOSFET,
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during initial start-up.
• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement
These drivers also feature a three-state PWM input which,
working together with Intersil’s multi-phase PWM controllers,
prevents a negative transient on the output voltage when the
output is shut down. This feature eliminates the Schottky
diode that is used in some systems for protecting the load
from reversed output voltage events.
• Pb-Free (RoHS Compliant)
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
Applications
• Optimized for POL DC/DC Converters for IBA Systems
• Core Regulators for Intel® and AMD® Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB417 for Power Train Design, Layout
Guidelines, and Feedback Compensation Design
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006, 2012. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6612B, ISL6613B
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6612BCBZ
6612 BCBZ
0 to +85
8 Ld SOIC
M8.15
ISL6612BCRZ
12BZ
0 to +85
10 Ld 3x3 DFN
L10.3x3
ISL6612BECBZ
6612 BECBZ
0 to +85
8 Ld EPSOIC
M8.15B
ISL6612BEIBZ
6612 BEIBZ
-40°C to +85°C
8 Ld EPSOIC
M8.15B
ISL6612BIBZ
6612 BIBZ
-40°C to +85°C
8 Ld SOIC
M8.15
ISL6612BIRZ
2BIZ
-40°C to +85°C
10 Ld 3x3 DFN
L10.3x3
ISL6613BCBZ
6613 BCBZ
0 to +85
8 Ld SOIC
M8.15
ISL6613BCRZ
13BZ
0 to +85
10 Ld 3x3 DFN
L10.3x3
ISL6613BECBZ
6613 BECBZ
0 to +85
8 Ld EPSOIC
M8.15B
ISL6613BEIBZ
6613 BEIBZ
-40°C to +85°C
8 Ld EPSOIC
M8.15B
ISL6613BIBZ
6613 BIBZ
-40°C to +85°C
8 Ld SOIC
M8.15
ISL6613BIRZ
3BIZ
-40°C to +85°C
10 Ld 3x3 DFN
L10.3x3
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6612B, ISL6613B. For more information on MSL, please see
Technical Brief TB363.
Pinouts
ISL6612BCB, ISL6613BCB, ISL6612BECB, ISL6613BECB
(8 LD SOIC, EPSOIC)
TOP VIEW
UGATE
1
BOOT
2
GND
8
PHASE
7
PVCC
PWM
3
6
VCC
GND
4
5
LGATE
2
ISL6612BCR, ISL6613BCR
(10 LD 3x3 DFN)
TOP VIEW
1
UGATE
BOOT
2
N/C
3
PWM
4
GND
5
10 PHASE
9 PVCC
GND
8
N/C
7
VCC
6 LGATE
FN9205.4
May 1, 2012
ISL6612B, ISL6613B
Block Diagram
ISL6612B AND ISL6613B
UVCC
BOOT
VCC
UGATE
PRE-POR OVP
FEATURES
+5V
10K
POR/
PWM
SHOOTTHROUGH
PROTECTION
PHASE
(LVCC)
PVCC
UVCC = VCC FOR ISL6612B
UVCC = PVCC FOR ISL6613B
CONTROL
8K
LOGIC
LGATE
GND
PAD
3
FOR DFN AND EPSOIC-DEVICES, THE PAD ON THE BOTTOM SIDE OF
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
FN9205.4
May 1, 2012
ISL6612B, ISL6613B
Typical Application - 3 Channel Converter Using ISL65xx and ISL6612B Gate Drivers
+7V to +12V
+5V TO 12V
VCC
BOOT
UGATE
PVCC
PWM
ISL6612B
PHASE
LGATE
GND
+7V to +12V
+5V TO 12V
+5V
VCC
VFB
VCC
UGATE
PVCC
PWM1
VSEN
PWM2
PGOOD
+VCORE
BOOT
COMP
PWM
ISL6612B
PHASE
PWM3
LGATE
MAIN
CONTROL
ISL65xx
VID
GND
ISEN1
ISEN2
FS
ISEN3
+7V to +12V
+5V TO 12V
GND
VCC
BOOT
UGATE
PVCC
ISL6612B
PHASE
PWM
LGATE
GND
4
FN9205.4
May 1, 2012
ISL6612B, ISL6613B
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to VPVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to VPVCC + 0.3V
PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to 15VDC
GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT-GND<36V)
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Resistance
θJA (°C/W)
θJC (°C/W)
SOIC Package (Note 4) . . . . . . . . . . . .
100
N/A
EPSOIC Package (Notes 5, 6). . . . . . .
50
7
DFN Package (Notes 5, 6) . . . . . . . . . .
48
7
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V to 13.2V
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operating
temperature range.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
VCC SUPPLY CURRENT
Bias Supply Current
IVCC
IVCC
Gate Drive Bias Current
IPVCC
IPVCC
ISL6612B, fPWM = 300kHz, VVCC =12V
-
8
-
mA
ISL6613B, fPWM = 300kHz, VVCC =12V
-
4.5
-
mA
ISL6612B, fPWM = 1MHz, VVCC = 12V
-
10.5
-
mA
ISL6613B, fPWM = 1MHz, VVCC = 12V
-
5
-
mA
ISL6612B, fPWM = 300kHz, VPVCC=12V
-
4
-
mA
ISL6613B, fPWM = 300kHz, VPVCC=12V
-
7.5
-
mA
ISL6612B, fPWM = 1MHz, VPVCC = 12V
-
5
-
mA
ISL6613B, fPWM = 1MHz, VPVCC = 12V
-
8.5
-
mA
0°C to +85°C
6.75
6.92
7.10
V
-40°C to +85°C
5.75
7.10
V
0°C to +85°C
5.20
5.60
V
-40°C to +85°C
4.20
5.60
V
POWER-ON RESET AND ENABLE
VCC Rising Threshold
VCC Falling Threshold
5.44
PWM INPUT (See Timing Diagram on page 7)
Input Current
IPWM
VPWM = 5V
-
500
-
µA
VPWM = 0V
-
-450
-
µA
PWM Rising Threshold
VCC = 12V
-
3.00
-
V
PWM Falling Threshold
VCC = 12V
-
2.00
-
V
Typical Three-State Shutdown Window
VCC = 12V
1.80
2.40
V
Three-State Lower Gate Falling Threshold
VCC = 12V
1.50
V
Three-State Lower Gate Rising Threshold
VCC = 12V
1.00
V
Three-State Upper Gate Rising Threshold
VCC = 12V
3.20
V
5
FN9205.4
May 1, 2012
ISL6612B, ISL6613B
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operating
temperature range. (Continued)
PARAMETER
SYMBOL
Three-State Upper Gate Falling Threshold
Shutdown Holdoff Time
TEST CONDITIONS
MIN
(Note 8)
VCC = 12V
TYP
MAX
(Note 8)
2.60
tTSSHD
UNITS
V
-
245
-
ns
tRU
VPVCC = 12V, 3nF Load, 10% to 90%
-
26
-
ns
LGATE Rise Time
tRL
VPVCC = 12V, 3nF Load, 10% to 90%
-
18
-
ns
UGATE Fall Time
tFU
VPVCC = 12V, 3nF Load, 90% to 10%
-
18
-
ns
LGATE Fall Time
tFL
VPVCC = 12V, 3nF Load, 90% to 10%
-
12
-
ns
UGATE Rise Time
UGATE Turn-On Propagation Delay (Note 7)
tPDHU
VPVCC = 12V, 3nF Load, Adaptive
-
10
-
ns
LGATE Turn-On Propagation Delay (Note 7)
tPDHL
VPVCC = 12V, 3nF Load, Adaptive
-
10
-
ns
UGATE Turn-Off Propagation Delay (Note 7)
tPDLU
VPVCC = 12V, 3nF Load
-
10
-
ns
LGATE Turn-Off Propagation Delay (Note 7)
tPDLL
VPVCC = 12V, 3nF Load
-
10
-
ns
LG/UG Three-State Propagation Delay (Note 7)
tPDTS
VPVCC = 12V, 3nF Load
-
10
-
ns
Upper Drive Source Current
IU_SOURCE
VPVCC = 12V, 3nF Load
-
1.25
-
Α
Upper Drive Source Impedance
RU_SOURCE 150mA Source Current
1.25
2.0
3.0
Ω
OUTPUT (Note 7)
Upper Drive Sink Current
IU_SINK
VPVCC = 12V, 3nF Load
-
2
-
Α
RU_SINK
150mA Source Current
0.9
1.6
3.0
Ω
Lower Drive Source Current
IL_SOURCE
VPVCC = 12V, 3nF Load
-
2
-
A
Lower Drive Source Impedance
RL_SOURCE 150mA Source Current
0.85
1.35
2.2
Ω
-
3
-
A
0.60
0.80
1.35
Ω
Upper Drive DC Sink Impedance
Lower Drive Sink Current
IL_SINK
VPVCC = 12V, 3nF Load
Lower Drive Sink Impedance
RL_SINK
150mA Sink Current
NOTE:
7. Limits established by characterization and are not production tested.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Functional Pin Description
PACKAGE PIN #
SOIC
DFN
PIN
SYMBOL
1
1
UGATE
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2
2
BOOT
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 8 for guidance in choosing the capacitor value.
-
3, 8
N/C
3
4
PWM
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
the “Three-State PWM Input” on page 7 for further details. Connect this pin to the PWM output of the controller.
4
5
GND
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
5
6
LGATE
6
7
VCC
7
9
PVCC
This pin supplies power to both upper and lower gate drives in ISL6613B; only the lower gate drive in ISL6612B.
Its operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND.
8
10
PHASE
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
9
11
PAD
FUNCTION
No Connection.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
6
FN9205.4
May 1, 2012
ISL6612B, ISL6613B
Description
1.5V<PWM<3.2V
1.0V<PWM<2.6V
PWM
tPDLU
tPDHU
tTSSHD
tPDTS
tPDTS
UGATE
tFU
tRU
LGATE
tFL
tRL
tTSSHD
tPDLL
tPDHL
FIGURE 1. TIMING DIAGRAM
Operation
Designed for versatility and speed, the ISL6612B and
ISL6613B MOSFET drivers control both high-side and low-side
N-Channel FETs of a half-bridge power train from one
externally provided PWM signal.
Prior to VCC exceeding its POR level, the Pre-POR overvoltage protection function is activated during initial start-up; the
upper gate (UGATE) is held low and the lower gate (LGATE),
controlled by the Pre-POR overvoltage protection circuits, is
connected to the PHASE. Once the VCC voltage surpasses the
VCC Rising Threshold (See “Electrical Specifications” on
page 5), the PWM signal takes control of gate transitions. A
rising edge on PWM initiates the turn-off of the lower MOSFET
(see Timing Diagram on page 7). After a short propagation
delay [tPDLL], the lower gate begins to fall. Typical fall times
[tFL] are provided in the “Electrical Specifications” section.
Adaptive shoot-through circuitry monitors the PHASE voltage
and determines the upper gate delay time [tPDHU]. This
prevents both the lower and upper MOSFETs from conducting
simultaneously. Once this delay period is complete, the upper
gate drive begins to rise [tRU] and the upper MOSFET turns on.
A falling transition on PWM results in the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [tPDLU] is encountered before the upper
gate begins to fall [tFU]. Again, the adaptive shoot-through
circuitry determines the lower gate delay time, tPDHL. The
PHASE voltage and the UGATE voltage are monitored, and
the lower gate is allowed to rise after PHASE drops below a
level or the voltage of UGATE to PHASE reaches a level
depending upon the current direction (See next section for
details). The lower gate then rises [tRL], turning on the lower
MOSFET.
7
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
These drivers incorporate a unique adaptive deadtime control
technique to minimize deadtime, resulting in high efficiency
from the reduced freewheeling time of the lower MOSFETs’
body-diode conduction, and to prevent the upper and lower
MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.2V/+0.8V trip point for a
forward/reverse current, at which time the UGATE is released
to rise. An auto-zero comparator is used to correct the rDS(ON)
drop in the phase voltage preventing from false detection of the
-0.2V phase level during rDS(ON conduction period. In the case
of zero current, the UGATE is released after 35ns delay of the
LGATE dropping below 0.5V. During the phase detection, the
disturbance of LGATE’s falling transition on the PHASE node is
blanked out to prevent falsely tripping. Once the PHASE is
high, the advanced adaptive shoot-through circuitry monitors
the PHASE and UGATE voltages during a PWM falling edge
and the subsequent UGATE turn-off. If either the UGATE falls
to less than 1.75V above the PHASE or the PHASE falls to less
than +0.8V, the LGATE is released to turn on.
Three-State PWM Input
A unique feature of these drivers and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set holdoff time, the driver outputs are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the “Electrical Specifications”
determine when the lower and upper gates are enabled.
FN9205.4
May 1, 2012
ISL6612B, ISL6613B
This feature helps prevent a negative transient on the output
voltage when the output is shut down, eliminating the
Schottky diode that is used in some systems for protecting
the load from reversed output voltage events.
In addition, more than 400mV hysteresis also incorporates
into the three-state shutdown window to eliminate PWM
input oscillations due to the capacitive load seen by the
PWM input through the body diode of the controller’s PWM
output when the power-up and/or power-down sequence of
bias supplies of the driver and PWM controller are required.
As an example, suppose two IRLR7821 FETs are chosen as
the upper MOSFETs. The gate charge, QG, from the data
sheet is 10nC at 4.5V (VGS) gate-source voltage. Then the
QGATE is calculated to be 53nC for UVCC (i.e. PVCC in
ISL6613B, VCC in ISL6612B) =12V. We will assume a
200mV droop in drive voltage over the PWM cycle. We find
that a bootstrap capacitance of at least 0.267μF is required.
1.6
1.4
1.2
During initial start-up, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds 6.9V (typically),
operation of the driver is enabled and the PWM input signal
takes control of the gate drives. If VCC drops below the
falling threshold of 5.6V (typically), operation of the driver is
disabled.
CBOOT_CAP (µF)
Power-On Reset (POR) Function
1.
0.8
0.6
QGATE = 100nC
0.4
50nC
Pre-POR Overvoltage Protection
0.2
Prior to VCC exceeding its POR level, the upper gate is held
low and the lower gate is controlled by the overvoltage
protection circuits during initial startup. The PHASE is
connected to the gate of the low side MOSFET (LGATE),
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during initial start-up. For
complete protection, the low side MOSFET should have a
gate threshold well below the maximum voltage rating of the
load/microprocessor.
When VCC drops below its POR level, both gates pull low
and the Pre-POR overvoltage protection circuits are not
activated until VCC resets.
Internal Bootstrap Device
Both drivers feature an internal bootstrap schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above UVCC + 5V and its capacitance value can be
chosen from the following equation:
Q GATE
C BOOT_CAP ≥ -------------------------------------ΔV BOOT_CAP
(EQ. 1)
Q G1 • UVCC
Q GATE = ------------------------------------ • N Q1
V GS1
where QG1 is the amount of gate charge per upper MOSFET
at VGS1 gate-source voltage and NQ1 is the number of
control MOSFETs. The ΔVBOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive.
8
20nC
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
ΔVBOOT_CAP (V)
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
The ISL6612B and ISL6613B provide the user flexibility in
choosing the gate drive voltage for efficiency optimization.
The ISL6612B upper gate drive can be driven above VCC
rising POR (7V) to 12V, but the lower drive rail can range
from 12V down to 5V depending on what voltage is applied
to PVCC. The ISL6613B ties the upper and lower drive rails
together. Simply applying a voltage from 5V up to 12V on
PVCC sets both gate drive rail voltages simultaneously.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (FSW), the output drive impedance, the
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
+125°C. The maximum allowable IC power dissipation for
the SO8 package is approximately 800mW at room
temperature, while the power dissipation capacity in the
EPSOIC and DFN packages, with an exposed heat escape
pad, is more than 2W and 1.5W, respectively. Both EPSOIC
and DFN packages are more suitable for high frequency
applications. See Layout Considerations paragraph for
thermal transfer improvement suggestions. When designing
the driver into an application, it is recommended that the
following calculation is used to ensure safe operation at the
FN9205.4
May 1, 2012
ISL6612B, ISL6613B
desired frequency for the selected MOSFETs. The total gate
drive power losses due to the gate charge of MOSFETs and
the driver’s internal circuitry and their corresponding average
driver current can be estimated with Equations 2 and 3,
respectively,
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q • VCC
BOOT
UVCC
D
CGD
RHI1
RLO1
(EQ. 2)
G
RG1
CGS
Q G1 • UVCC 2
P Qg_Q1 = --------------------------------------- • F SW • N Q1
V GS1
PHASE
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
⎛ Q G1 • UVCC • NQ1 Q G2 • LVCC • N Q2⎞
I DR = ⎜ ------------------------------------------------------ + -----------------------------------------------------⎟ • F SW + I Q
V GS1
V GS2
⎝
⎠
LVCC
D
(EQ. 3)
where the gate charge (QG1 and QG2) is defined at a
particular gate to source voltage (VGS1and VGS2) in the
corresponding MOSFET datasheet; IQ is the driver’s total
quiescent current with no load at both drive outputs; NQ1
and NQ2 are the number of upper and lower MOSFETs,
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The IQ*VCC
product is the quiescent power of the driver without
capacitive load and is typically 116mW at 300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (RG1 and RG2) and the internal gate resistors
(RGI1 and RGI2) of MOSFETs. Figures 3 and 4 show the
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as:
P DR = P DR_UP + P DR_LOW + I Q • VCC
(EQ. 4)
R HI1
R LO1
⎛
⎞ P Qg_Q1
P DR_UP = ⎜ -------------------------------------- + ----------------------------------------⎟ • --------------------R
+
R
R
+
R
2
⎝ HI1
EXT1
LO1
EXT1⎠
R LO2
R HI2
⎛
⎞ P Qg_Q2
P DR_LOW = ⎜ -------------------------------------- + ----------------------------------------⎟ • --------------------2
⎝ R HI2 + R EXT2 R LO2 + R EXT2⎠
Q1
Q1
S
Q G2 • LVCC 2
P Qg_Q2 = -------------------------------------- • F SW • N Q2
V GS2
R GI1
R EXT1 = R G1 + ------------N
CDS
RGI1
R GI2
R EXT2 = R G2 + ------------N
CGD
RHI2
RLO2
G
RG2
CDS
RGI2
CGS
Q2
S
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Layout Considerations
For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.
Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
DRAINs of lower FETs and the power ground. Thus, smaller
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
in between the power components is required for good
airflow. The traces from the drivers to the FETs should be
kept short and wide to reduce the inductance of the traces
and to promote clean drive signals.
Q2
9
FN9205.4
May 1, 2012
ISL6612B, ISL6613B
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 6, 09/09
3.00
6
PIN #1 INDEX AREA
A
B
1
6
PIN 1
INDEX AREA
(4X)
3.00
2.00
8x 0.50
2
10 x 0.23
4
0.10
1.60
TOP VIEW
10x 0.35
BOTTOM VIEW
4
(4X)
0.10 M C A B
0.415
PACKAGE
OUTLINE
0.200
0.23
0.35
(10 x 0.55)
SEE DETAIL "X"
(10x 0.23)
1.00
MAX
0.10 C
BASE PLANE
2.00
0.20
C
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
C
0.20 REF
5
1.60
0.05
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Lead width applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
10
FN9205.4
May 1, 2012
ISL6612B, ISL6613B
Small Outline Exposed Pad Plastic Packages (EPSOIC)
M8.15B
N
INDEX
AREA
H
0.25(0.010) M
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
B M
E
INCHES
-B1
2
3
TOP VIEW
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
SIDE VIEW
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.056
0.066
1.43
1.68
-
A1
0.001
0.005
0.03
0.13
-
B
0.0138
0.0192
0.35
0.49
9
C
0.0075
0.0098
0.19
0.25
-
D
0.189
0.196
4.80
4.98
3
E
0.150
0.157
3.81
3.99
4
e
α
e
MILLIMETERS
0.050 BSC
1.27 BSC
-
H
0.230
0.244
5.84
6.20
-
h
0.010
0.016
0.25
0.41
5
L
0.016
0.035
0.41
0.89
6
N
8
8
7
α
0°
8°
0°
8°
-
P
-
0.094
-
2.387
11
P1
-
0.094
-
2.387
11
Rev. 5 8/10
NOTES:
1
2
3
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
P1
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
N
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
P
BOTTOM VIEW
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: INCH. Converted millimeter dimensions
are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
11
FN9205.4
May 1, 2012
ISL6612B, ISL6613B
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
A
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MIN
MAX
MIN
MAX
NOTES
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
N
α
NOTES:
MILLIMETERS
8
0°
1.27
8
8°
0°
6
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN9205.4
May 1, 2012
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