an1044

ISL6558EVAL2 - Low-Profile, 5V/12V Input,
500kHz, and 90% Efficiency DC/DC Converter
®
Application Note
AN1044.2
April 4, 2006
Author: Chun Cheung
Introduction
Intersil’s ISL6558 and ISL6609
The changing computer performance landscape has brought
about the need for flexible power solutions. Peripheral
performance continues to increase as higher speed bus
interfaces are made available. Router designs continue to
grow in complexity as on-board processors perform more
functions within a limited board space while continuing to
increase the speed of data transfer. This places higher
power density requirements on the DC/DC converters which
supply them.
The ISL6558 controller, coupled with ISL6609 singlechannel driver ICs, forms the basic building blocks for
applications which demand high current, rapid load transient
response, and high efficiency performance at high switching
frequency within a limited board area and height.
Intersil’s Endura™ multi-phase controllers (HIP63xx and
ISL65xx) and synchronous-rectified buck MOSFET drivers
(HIP66xx and ISL66xx) are suitable for the interleaved
DC/DC buck converter implementation, as shown in
Figure 1, and provide superior performance solutions with
their space economical MLFP packages.
Q1
Lo
Q2
Q1
VIN
Lo
Lin
Q2
Cin
Vo
Co
Q1
Lo
Q2
FIGURE 1. MULTI-PHASE INTERLEAVED BUCK CONVERTER
This application note first gives a brief introduction of
Intersil’s four-phase controller ISL6558 and synchronousrectified driver ISL6609. A summary of the ISL6558 and
ISL6609 based design follows. The experimental results for
a low-profile [email protected], 500kHz, and 90% efficiency
converter in two-phase operation using the interleaved
approach and with their space economical MLFP package
ICs are discussed. The evaluation board can be pushed up
to 80A in four-phase operation, or modified for 12V input
applications by replacing the input capacitors with higher
voltage rating capacitors. Term Definitions, Reference,
Schematics, Bill of Materials, and Layout are included at the
end of this application note.
1
The ISL6558 regulates output voltage and balances load
currents for two to four synchronous-rectified buck converter
channels; its internal structure is shown in Figure 2. The
internal 0.8V reference allows output voltage selection down
to that level with a 1% system accuracy over temperature.
The current-channel balance loop provides good thermal
balance among all phases. Output voltage droop or active
voltage positioning is optional. Overvoltage and overcurrent
monitors and protection functions of the IC provide a safe
environment for the microprocessor or other load. The
controller is available in a 16-lead SOIC package and a
5x5mm2 20-lead MLFP package with some space savings.
For more detailed descriptions of the ISL6558 functionality,
refer to the device datasheet [1].
The ISL6609 is a 5V driver IC capable of delivering up to 4A
of gate current for rapidly switching both MOSFETs in a
synchronous-rectified bridge; its internal structure is shown
in Figure 2. It is especially designed for voltage regulators
that require high efficiency performance at high switching
frequency within a limited board space. The ISL6609
accepts a single logic input to control both upper and lower
MOSFETs. Its Tri-State® feature, working together with
Intersil’s Multi-Phase PWM controllers, helps prevent a
negative transient on the output voltage when the output is
being shut down. This eliminates the Schottky diode that is
used in some systems for protecting the microprocessor
from reversed-output-voltage damage. Furthermore,
adaptive shoot-through protection is implemented on both
switching edges to provide optimal dead time and minimize
conduction losses. Bootstrap circuitry permits greater
enhancement of the upper MOSFET. The driver is available
in a 8-lead SOIC package and a space economical 3x3mm2
8-lead MLFP package. For a more detailed description of the
ISL6609, refer to the device data sheet [2].
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2006. All Rights Reserved
Endura™ is a trademark of Intersil Americas Inc. | Tri-State® is a registered trademark of National Semiconductor Corp.
Application Note 1044
ISL6558
PGOOD
POWER-ON
RESET (POR)
-
VSEN
VCC
UV
+
X 0.9
TRI-STATE®
R
OV
LATCH
CLOCK AND
SAWTOOTH
GENERATOR
S
+
+
OV
-
X1.15
∑
+
+
-
∑
+
COMP
+
PWM2
PWM
-
-
∑
+
0.8V
REFERENCE
+
+
-
∑
+
-
E/A
PWM3
PWM
-
-
PWM4
PWM
PHASE
NUMBER
CURRENT
CORRECTION
FB
PWM1
PWM
-
SOFTSTART
AND FAULT
LOGIC
FS/EN
CHANNEL
DETECTOR
DETECTOR
DROOP
ISEN1
+
ITOTAL
+
+
OC
-
ISEN2
∑
+
ISEN3
+
ISEN4
ITRIP
GND
ISL6609
VCC
BOOT
EN
UGATE
VCC
PWM
20K
PHASE
SHOOTTHROUGH
PROTECTION
20K
CONTROL
LOGIC
VCC
LGATE
GND
FIGURE 2. SIMPLIFIED ISL6558 AND ISL6609 INTERNAL STRUCTURE
2
AN1044.2
April 4, 2006
Application Note 1044
Summary of Design
TABLE 2. CRITICAL DESIGN PARAMETERS (Continued)
Table 1 summarizes the specifications of a power converter
for mid-range router applications. The ISL6558 and ISL6609
based evaluation board has been designed to meet these
criteria.
TABLE 1. ISL6558EVAL2 SPECIFICATIONS
PARAMETER
CONDITION
MIN
TYP
MAX
Input Voltage
VIN
4.5V
5V
5.5V
Output Regulation
0.1% R16
and R19
1.336
1.35
1.365
Transient Regulation
6.5A Step
200A/µs
Vo 20mV
Continuous Load
25°C with
200LFM
Vo +
20mV
30A
VALUE UNIT
OUTPUT INDUCTORS (ASSUMING EQUAL DISTRIBUTION
AMONG OUTPUT INDUCTORS)
ILo,PP
Lo(Io) = 0.3µH, VIN = 5.5V
6.88
A
Lo(Io) = 0.3µH, VIN = 5.5V, N = 2
4.65
A
ILo,Peak
Lo(Io) = 0.3µH, VIN = 5.5V
18.44
A
ILo,RMS
Lo(Io) = 0.3µH, VIN = 5.5V
15.13
A
8.48
A
13.04
A
IPP
200A/µs
25°C with
200LFM
IQ1,RMS
Channel Switching
Frequency
500kHz
Lo(Io) = 0.3µH, VIN = 5.5V
Table 3 summarizes a rough power dissipation analysis for
the referenced design.
43A
0 LFM
Lo(Io) = 0.3µH, VIN = 4.5V
LOWER FETs
IQ1,RMS
Minimum Airflow
Efficiency
CONDITIONS
UPPER FETs
Transient Slew Rate
Over Current
PARAMETER
TABLE 3. FULL-LOAD POWER DISSIPATION BUDGET
POWER DISSIPATION AT 30A LOAD
ELEMENTS
4.5V
5.0V
5.5V
25°C with
200LFM
89.7%
25°C with No
Airflow
89.3%
Switching Frequency
500kHz
0.92Vo
Per-Channel Output
Inductor
0.3µH at Full load
Undervoltage Rising
Threshold
Undervoltage Falling
Threshold
0.9Vo
Overvoltage
Threshold
1.15Vo
CALCULATION CONDITIONS
Number of Active Channels
PER-CHANNEL LOSSES (xN)
Table 2 shows the calculation results of critical design
parameters for the reference design, a two-phase
interleaved DC/DC buck converter.
TABLE 2. CRITICAL DESIGN PARAMETERS
PARAMETER
CONDITIONS
VALUE UNIT
DUTY CYCLE AND SWITCHING FREQUENCY
D
Fsw
N=2
VIN = 5, Vo = 1.35
28.3
%
RT = 51.1kΩ (measured)
500
kHz
Upper FETs Conduction
0.395W
0.356W
0.323W
Upper FETs Switching
0.461W
0.516W
0.572W
Lower FETs Conduction
0.333W
0.328W
0.340W
Lower FETs Body-diode
Conduction
0.233W
0.232W
0.231W
Output Inductor Copper
0.123W
0.123W
0.123W
Output Inductor Core
(Estimated)
0.036W
0.0.036W
0.036W
Per-Channel Driver
0.305W
0.375W
0.454W
0.044W
0.037W
OTHERS (x1)
Input Inductors Copper
INPUT INDUCTOR AND CAPACITORS
0.055W
Io = 30A, N = 2, ∆VIN,CAP = 20mV
180
µF
Input Inductors Core
IIN,RMS
VIN = 5.5V, Io = 30A
7.63
A
Input Capacitors
0.273W
0.287W
0.291W
Lin (min)
Cin = 180µFx3, dIin/dt = 0.1A/µs
300
nH
Output Capacitors
0.0035W
0.0048W
0.0061W
Controller
0.078W
0.078W
0.078W
fc = Fsw/5 = 100kHz, f(Istep) = 20mV
517
µF
PCB Copper
0.196W
0.184W
0.176W
IoRMS
Lo(Io) = 0.3µH, VIN = 5.5V
1.34
A
Miscounted and Error
0.32W
0.28W
0.29W
ESR(max)
Istep = 6.5A, f(step) = 20mV
3.07
mΩ
4.655W
4.688W
4.737W
Cin (min)
OUTPUT CAPACITORS
Co(min)
3
TOTAL
Negligible
AN1044.2
April 4, 2006
Application Note 1044
The ISL6558EVAL2 evaluation board as configured is
capable of 30A continuous load current and handling
200A/µs or higher speed load transients. The evaluation
board meets the design specifications indicated in Table 1.
Table 4 summarizes the equipment that was used for the
performance evaluation.
TABLE 4. EQUIPMENT LIST
Equipment
Boards Used
Power Supplies
EQUIPMENT DESCRIPTIONS
ISL6558EVAL2 Rev. A, #1 and #2
1. Hewlett Packard 6653A, 35V, 15A. S/N:
3621A-03425
Oscilloscope
LeCroy LT364L. S/N: 01106
Multimeters
Fluke 8050A. S/N: 2466115 & 3200834
Load
1. Chroma 63103. S/N: 631030002967
2. Chroma 63103. S/N: 631030003051
Current Probe
Amplifier
Fan
LeCroy AP015. SN: 3293
POPST-MOOREN TYP 4600X (4098547)
ISL6558EVAL2 OPERATION AND MODIFICATION TIPS
• Apply the input voltage (VIN) prior to the control voltage
VCC5 (5V). This sequencing results in initializing the
ISL6609 driver before the ISL6558 starts, and retains the
soft-start interval. Vice versa, the ISL6558 could produce
maximum duty cycle PWM drive signal, which results in an
overcurrent or overvoltage trip due to lack of soft-start.
The evaluation board is configured to power up from a
single 5V supply, and it eliminates the problem discussed
above.
• SW1 is used to engage or remove the load transient
generator.
• Droop option is not selected in the reference design since
the required load transient step is not greater than 50% of
the full load. In another word, the droop only helps reduce
the number of output capacitors and still retains the same
transient performance when the load transient step is
greater than 50% of full load.
• For 3-phase operation, add the current sense resistor R17
and place JP4 to ON position (away from TP8). The
compensation gain (R11) should be scaled by 2/3 for
system stability with a reasonable phase margin.
• For 4-phase operation, add the current sense resistors R2
& R17 and place JP4 &JP2 to ON position (away from
TP8 and TP5). The compensation gain (R11) should be
scaled by 1/2 for system stability with a reasonable phase
margin.
• If there is sufficient airflow, use a single LPAK Hitachi
HAT1264 for the upper FET and two SO-8 Siliconix
Si4842DYs for the lower FETs in each channel; but it
comes with the penalty of 1% lower efficiency, as shown in
Table 5. Note that the current sense resistors (R2 and
R17) need to be adjusted to get a proper over current
setpoint.
• For 12V input operation, the jumper JP1 should be
removed to prevent the controller and drivers from
overvoltage damage. A 5V supply is required to power up
the controller and the drivers; the diode D1 is to protect
both the drivers and controller from reversed-bias
damage. The 12V supply should be applied prior to the
5V; otherwise, the output voltage will lack soft-start and
cause an over overcurrent or overvoltage at the output.
Furthermore, the input capacitors should be replaced with
higher voltage rating (16V or above) capacitors. In
addition, the compensation gain (R11) should be scaled
by 5/12 for system stability with a reasonable phase
margin.
• Any change of the output filter will require the
compensation network to change for an optimum transient
response. If very lower ESR capacitors are used at the
output, a type III compensation network is required to
boost up the phase for a better transient performance.
• The feedback resistor (R19) can cause some delay in the
soft-start interval, as discussed in the ISL6557A data
sheet section SOFT-START [3]. It should not be a very
high impedance resistor.
EFFICIENCY
The efficiency data, as plotted in Figure 3, are taken with a
PAPST-MOTOREN TYP 4600X fan turned on 8” away from
the input end of the evaluation board at room temperature
(approximate 200LFM). This figure shows that the converter
operates less efficiently at high line and low-to-medium load
since the switching loss is the dominant portion of the total
losses in that operating condition. As the load increases, the
dominant conduction losses help cut down the difference.
92
91
EFFICIENCY (%)
Experimental Results
5.0V
4.5V
90
89
88
VIN = 5.5V
87
86
85
84
83
5
10
15
20
25
30
Iout (A)
FIGURE 3. EFFICIENCY AT 500kHz AND 200LFM
• Use R25, R26, R28, and R29 to program the load
transient speed. The higher values these resistors, the
slower the transient.
4
AN1044.2
April 4, 2006
Application Note 1044
Figure 4 shows the efficiency for various frequencies and
airflow conditions.
92
FSW = 465K, 200 LFM
EFFICIENCY (%)
91
90
FSW = 500K, 200 LFM
89
88
FSW = 500K, 0 LFM
As shown in Figure 6, the converter is disabled when the
control voltage (VCC5) is pulled below the POR falling
threshold (3.88V nominal) of the ISL6558. The PGOOD
signal falls low indicating the output voltage is out of
regulation. The ISL6609 enters Tri-State® and holds both
upper and lower drive signals low. The L-C resonant tank is
broken and cannot cause negative ringing at the output
since the lower FETs are turned off, blocking any negative
current.
87
86
85
5
IOUT
10
15
20
25
30
VIN=VCC5
Iout (A)
VO
FIGURE 4. EFFICIENCY FOR VARIOUS FREQUENCY AND
AIRFLOW AT VIN=5V
Different combinations of upper and lower MOSFETs have
been evaluated at Vin = 5V and Fsw = 500kHz with 200LFM
airflow, as shown in Table 5. The last combination with one
Hitachi HAT2164 upper FET and two Siliconix Si4842DY
lower FETs provides high efficiency and good thermal
performance with some space and cost reduction.
TABLE 5. EFFICIENCY WITH DIFF. UPPER & LOWER MOSFETs
#
UPPER FET
LOWER FET
EFFICIENCY
1
HAT2168 x2
HAT2164 x2
89.85%
2
HAT2168 x1
HAT2164 x2
87.94%
3
HAT2168 x2
Si4842DY x2
89.50%
4
HAT2164 x1
Si4842DY x2
88.90%
OUTPUT SOFT-START AND TURN-OFF
As the control voltage VCC5 reaches the POR rising
threshold (4.38V nominal) of the ISL6558, the FS/EN pin is
released from ground; the output begins a monotonic rise
comprised of 2048 digital steps, as shown in Figure 4. At the
end of the soft-start interval, the PGOOD signal transitions to
indicate the output voltage is within specification.
PGOOD
FIGURE 6. TURN-OFF WAVEFORMS
TRANSIENT RESPONSES
A transient load generator is populated on the board to
evaluate the response of the converter at high-speed load
transients. Current setting of the generator provides about
6.5A load step with 160A/µs on the rising edge and 210A/µs
on the falling edge without output droop configuration.
The input current rises/falls at a speed limited by the input
inductor and capacitors during step-up/step-down transients.
Figure 7 shows a very low ramping up speed (0.02A/µs) of
the input current at the load transient condition. This is due
to a large effective input inductance seen by the converter.
The effective input inductance is the sum of the on-board
input inductance and the inductance of the long source leads
of the bench power supply.
The transient performance at different operating conditions
has been summarized in Table 6. Little difference is noted for
various line and load conditions. Note that the ripple portion
has been included.
VIN=VCC5
TABLE 6. TRANSIENT RESPONSE (6.5A STEP)
VO
PGOOD
FIGURE 5. SOFT-START WAVEFORMS
5
INPUT VOLTAGE/LOAD CURRENT
STEP-UP/DOWN
4.5V/0A
21.9mV/21.9mV
4.5V/25A
21.9mV/21.9mV
5.0V/0A
21.9mV/23.1mV
5.0V/25A
22.5mV/21.9mV
5.5V/0A
21.9mV/21.2mV
5.5V/25A
23.8mV/24.4mV
AN1044.2
April 4, 2006
Application Note 1044
VIN=5V
VO
VIN=5V
VO
IIN
IO (5A/V)
IIN
IO (5A/V)
FIGURE 7. TRANSIENT RESPONSE AT NO LOAD (VIN = 5.0V)
VIN=5V
FIGURE 10. TRANSIENT RESPONSE AT 25A (VIN = 5.0V)
VIN=5V
VO
VO
IO (5A/V)
IO (5A/V)
FIGURE 8. STEP-UP TRANSIENTS AT NO LOAD (VIN = 5.0V)
VIN=5V
VO
FIGURE 11. STEP-UP TRANSIENTS AT 25A (VIN = 5.0V)
VIN=5V
VO
IO (5A/V)
IO (5A/V)
FIGURE 9. STEP-DOWN TRANSIENTS AT NO LOAD (VIN = 5.0V)
6
FIGURE 12. STEP-DOWN TRANSIENTS AT 25A (VIN = 5.0V)
AN1044.2
April 4, 2006
Application Note 1044
OVER CURRENT AND SHORT CIRCUIT
OVERVOLTAGE SHUTDOWN
When the converter is momentarily shorted or overloaded,
as shown in Figure 13, the converter enters hiccup mode
with a narrow duty cycle and long switching period. PGOOD
stays low during the overcurrent period; it indicates the
output voltage is within regulation limits after the short is
removed and the output completes a soft-start interval.
With the COMP pin momentarily tied to a 4V voltage source
with respect to the ground, the error voltage jumps high and
the duty cycle increases. Thus, the output voltage rises up
immediately until it reaches the overvoltage threshold setting
the OV latch and triggers the PWM outputs low. PGOOD is
pulled low indicating output out of regulation, as shown in
Figure 15.
As shown in Figure 14, the converter can sustain a
permanent short circuit remaining in hiccup mode with a
frequency of 185Hz. The average load current and the
average power dissipation in each power component are
reduced significantly; thus, the converter can stay at a short
without causing any permanent damage or thermal issues.
VO
COMP
VO
IOUT
PGOOD
IO
FIGURE 15. OVERVOLTAGE WAVEFORMS
Conclusion
PGOOD
FIGURE 13. OVER-LOADED OUTPUT WAVEFORMS
The superior performance of Intersil’s ISL6558 four-phase
controller, coupled with Intersil’s ISL6609 driver, has been
demonstrated in the low-profile reference design of a 40W,
500kHz interleaved DC/DC buck converter. An ultra high
efficiency of 90% at 1.35V output and 30A full load has been
achieved.
The extensive experimental results give users a better
understanding of the operation of the converter, the ISL6558
four-phase PWM controller, and the ISL6609 synchronousrectified driver.
VO
IO
PGOOD
FIGURE 14. SHORT-CIRCUIT WAVEFORMS
7
AN1044.2
April 4, 2006
Application Note 1044
Term Definitions
References
Intersil documents are available on the web at
http://www.intersil.com.
Cin
Input Capacitance
Co
Output Capacitance
[1] Intersil’s ISL6558 Data Sheet.
D
Ratio of ON Interval of Upper FET to SingleChannel Switching Period, Duty Cycle
[2] Intersil’s ISL6609 Data Sheet.
∆VIN,CAP
ESR
fc
Fsw
IIN
Allowable Input Voltage Ripple Contributed by the
Input Capacitors
Overall ESR of Output Capacitors
System Closed-Loop Bandwidth
ILO
Current thru Each-Channel Inductor
ILo,PEAK
Peak Current thru Each-Channel Inductor
ILo,PP
Ripple Current thru Each-Channel Inductor
Io
Overall Ripdple Current thru Output Capacitors
Output Load Current
RMS Current thru Upper FET, Q1
IQ2,RMS
RMS Current thru Upper FET, Q2
Load Transient Step
Lin
Input Inductor
Lo
Inductance of Each-Channel Inductor
N
Number of Active Channels
Po
Output Power
η
2. Bill of Materials and Layout of Evaluation Board.
RMS Current thru Each-Channel Inductor
IQ1,RMS
Istep
1. Schematics of Reference Design and Load Transient
Generator.
Input Current
RMS Current thru Input Capacitors
IPP
Appendix
Per-Channel Switching Frequency
IIN,RMS
ILo,RMS
[3] Intersil’s ISL6557A Data Sheet
Output Efficiency
VIN
Input Voltage
Vo
Output Voltage
8
AN1044.2
April 4, 2006
UPPER FETS: HAT2164H, Si4842DY, Si7868DP
C11
1u
GND
1
TP3
REVERSE BIASING
PROTECTION
R37
499K
PWM
6 9
ISL6505CR
JP2
R3
909, DNP
VCC
6
Q4
BOOT
PWM
6 9
ISL6505CR
R38
499K
9
IC_GND
VCC5
5
Q9
4
Q10
20
19
18
17
16
21
909
R14
51.1K
PWM
6 9
ISL6505CR
0
5
5
VCC
C24
1u
3
2
1
Q14
5
4
IC_GND
IC_GND
R40
499K
2
ISL6505CR
6 9
BOOT
PWM
MAKE THIS CONNECTION NEAR THE
VOUT POSITIVE TERMINAL OF C89, TP9
R24
AN1044.2
April 4, 2006
0
IC_GND
GROUND IC TO THE NEGATIVE
TERMINAL OF C89, TP9
GND
C25
VCC5
EN
VCC
6
3
2
1
Q15
5
5
PHASE3
L5
2
3 NC
Q16
4
1
NC 4
300nH
Q17
4
1
2
3
9
IC_GND
PHASE 3
TP8
5
1
IC_GND
U5
5
R20
4
C27
1u
7
0
LGATE PHASE
C26
DNP
4
909, DNP
8
JP4
UGATE
R23
499
R22
22.1k
GND
R41
DNP
R21
750
300nH
10k, DNP
R18
GND9
R17
C100
DNP
3
750
R19
499
VCC5
1
NC 4
22u, DNP
R16
IC_GND
L4
Q13
4
C23
DNP
R15
22.1k
2
3 NC
Q12
4
5
R39
499K
GND
R13
R12
6
EN
PHASE2
C19
22u
3
2
1
Q11
5
4
BOOT
2
ISL6558IR
VCC5
LGATE PHASE
1
U4
7
UGATE
R10
4
C21
1u
8
15
14
13
12
11
3
6
7
8
9
10
R11
6.04k
PHASE 2
TP7
10k, DNP
ISEN1
PWM1
PWM2
ISEN2
ISEN3
GND9
C22
DNP
N/C6
FS/EN
GND8
GND9
PWM3
Jumper, DNP
COMP
N/C2
DROOP
FB
VSEN
9
1
2
3
4
5
JP3
3
2
1
IC_GND
PGD
VCC19
VCC18
PWM4
ISEN4
GND21
IC_GND
C20
10n
5
4
C17
1u
U3
Q8
4
TP6
C18
0.1uF
300nH
5
VCC
1
NC 4
1
2
3
COMP
6
EN
L3
2
3 NC
3
2
1
Q6
5
5
2
TP5
GND
C16
PHASE1
22u
4
1
DNP
VCC5
LGATE PHASE
UGATE
R9
U2
7
8
C15
1u
C14
4
10k,DNP
4
PLACE CR1 ON TOP LAYER
0
2
PGOOD
909
Q7
2N7002
1
RED
4
R8
Q5
Application Note 1044
3
R7
3
2
3
2
1
5
IC_GND
3
1
GREEN
R6
1k
VCC5
PHASE 1
TP4
C12
1u
0
GND9
R5
10k
CR1
DCR=0.54mOhm
4
C13
DNP
R4
1k
VOUT
ETQP2H0R3BFA
Q3
4
5
2
NC 3
300nH
1
2
3
THIS CIRCUITRY GOES OUTSIDE OF THE
IMPLEMENTATION AREA.
R2
9
9
VCC5
EN
Q2
5
1
2
3
MBR0530T1
BOOT
2
VCC5
3
2
1
1
2
3
GND
VCC12
U1
1
2
3
J3
L2
1
4 NC
PHASE4
10k, DNP
R1
5
DNP
1
2
3
DNP
PHASE 4
TP2
C1
22u, DNP
5
DNP
DNPs for 60A and large load
step application
BOTH UPPER AND LOWER FETS USE "LFPAK" FOOTPRINT
3
2
1
4
C9
5
4
C8
8
C7
7
C6
UGATE
C5
LGATE PHASE
C10
100u, 16V
D2
12V
C4
VCC5
MBR0530T1
J4
C3
DNP
JP1
D1
5V B
C2
GND
J2
VIN_F
1
NC 4
4
REMOVE JUMPER
FOR 12V INPUT
300nH
GND9
VIN
Q1
3
L1
2
3 NC
VIN
J1
LOWER FETS: HAT2168H, Si4842DY
INPUT CAPACITORS: PANASONIC
EEFUE0J181R 6.3V, 180uF
1
2
3
INPUT VOLTAGE VIN
> 4.0V DURING
TP1
LOAD TRANSIENT
Pull Down PWM pin during startup so
that the output can rise
monitonically when the input turns
on/off repetitively and rapidly.
C28
1u
PHASE 3 AND 4 ARE USED
FOR 60A APPLICATION
Intersil Corporation
Endura Power Management
4020 Sturrup Creek Drive
Durham, NC 27703
Size
Custom
Date:
Title
Rev
B
ISL6558EVAL2, [email protected], 500kHz
Wednesday, November 20, 2002
Sheet
1
of
2
OUTPUT CAPACITORS: PANASONIC
EEFUE0D391XR 2V, 390uF
MAKE THE FOOTPRINT FIT
FOR SMT1812 TOO
J5
1
VOUT
VOUT
C30
C31
C32
C33
C34
DNP
C35
C36
C37
C38
390uF
390uF
390uF
DNP
C39
C40
C41
C42
J6
1
GND
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
DNP
10
DNPs for 60A and large load step
application
C60
DNP
C61
DNP
C62
22uF
C63
22uF
C64
22uF
C65
22uF
C66
DNP
C67
DNP
C69
DNP
C70
DNP
C71
22uF
C72
DNP
C73
22uF
C74
22uF
C75
22uF
C76
DNP
C77
DNP
C78
DNP
C91
22uF
C92
22uF
C93
22uF
C94
22uF
C95
22uF
C96
22uF
C97
22uF
C98
DNP
C99
DNP
Bleed the current from the boot
resistor (10k) at shutdown mode;
it can be removed for
application with such a similar
resistive load.
C68
51.1 Ohm, DNP
TRANSIENT GENERATOR AND LOAD. THIS CIRCUITRY
GOES OUTSIDE OF THE IMPLEMENTATION AREA.
Application Note 1044
C59
DNP
VDD
HB
HO
HS
LO
VSS
LI
HI
HIP2100IB
VOUT
TP9
C79
1uF
VOUT
TP10
C81
22uF
C82
22uF
C83
22uF
C84
22uF
C85
22uF
C86
22uF
C87
22uF
C88
22uF
1
R27
10k R26 10
SW1
1
3
2
4
R28 3
D4
TURN OFF ONE
C89
1uF
1
R30
10k
VCC12
C80
22uF
D3
R29 10
R31
46.4k
1uF makes load transient worse according the simulation.
R33
DNP
3
6.5A STEP
Q20
2N7002
2
TP11
TRANS. LO
Q19
HUF7_1
R32
0.1
R34 1k
1
Q18
HUF761
3
MOVE C89
CLOSE TO TP13
R25 3
8
7
6
5
3
U6
4
1
2
3
4
4
VCC12
R35
0.1
C90
10uF
R36
DNP
Intersil Corporation
AN1044.2
April 4, 2006
Endura Power Management
4020 Sturrup Creek Drive
Durham, NC 27703
Size
Custom
Date:
Title
Rev
B
ISL6558EVAL2, [email protected], 500kHz
Thursday, December 26, 2002
Sheet
2
of
2
Application Note 1044
Bill of Materials
QUANTITY
REFERENCE
DESCRIPTION
1
CR1
Dual LED
0
C1, C25
22µF
SM/C_1206
0
C2, C3
680µF, 6.3V, AVX, TPS III,
TPSV687M006R0035
CAP_7361
AVX
DNP
3
C4, C5, C6
180µF, 6.3V
CAP_TECAP
PANASONIC
EEFUE0J181XR
0
C7, C8, C9
180µF, 6.3V
CAP_TECAP
PANASONIC
DNP
1
C10
100µ, 16V
PTH
Panasonic
ECA1CHG101
10
C11, C12, C15, C17, C21,
C24, C27, C28, C79, C89
1µ
SM/C_1206
Various
6.3V, X5R
0
C13, C16, C22, C23, C26
DNP
SM/C_0603
1
C18
0.1µF
SM/C_0805
Various
25V, X7R
1
C20
10n
SM/C_0603
Various
25V, X7R
3
C35, C36, C37
390µF, 2V, 10mΩ
CAP_TECAP
PANASONIC
EEFUE0D391XR
0
C30-C34, C38, C39, C40,
C41, C42, C45-C57
DNP
CAP_TECAP
26
C14, C19, C62-C65, C71,
C73-C75, C80-C88,
C91-C97
22µF
SM/C_1206
0
C59-61, C66, C67-C70,
C72, C76-C78, C98-C99
DNP
SM/C_1206
1
C90
10µF
SM/C_1206
Various
6.3V, X5R
2
D2, D1
MBR0530T1
SOD123
On Semiconductor
MBR0530T1
2
D3, D4
BAV99LT1
SOT23
Various
BAV99
2
JP3, JP1
2-pin Header
TP\2P
Berg
68000-236
2
JP2, JP4
3-pin Header
TP\3P
Berg
68000-236
Berg
71363-102
3
PACKAGE
Shunt for JP1, JP2 and JP4
VENDOR
PART NO.
PANASONIC
LN2162C13-(TR)
DNP
DNP
DNP
Various
6.3V, X5R
DNP
1
J1
VIN
BINDING/POST
Johnson Components
111-0702-001
1
J2
5V BIAS
BINDING/POST
Johnson Components
111-0702-001
1
J3
GND
BINDING/POST
Johnson Components
111-0703-001
1
J4
12V BIAS
BINDING/POST
Johnson Components
111-0707-001
1
J5
VOUT
BINDING/POST
Burndy
KPA8CTP
1
J6
GND
BINDING/POST
Burndy
KPA8CTP
4
L1, L2,L3,L4,L5
300nH
SMT
Panasonic
ETQP2H0R3BFA
8
Q1, Q2, Q5, Q6,
Q10, Q11, Q14, Q15
9.4mΩ, 30V
LFPAK
HITACHI
HAT2168H
8
Q3, Q4, Q8, Q9, Q12, Q13,
Q16, Q17
4.4mΩ, 30V
LFPAK
HITACHI
HAT2164H
2
Q20, Q7
2N7002
SOT23
On Semiconductor
2N7002LT1
2
Q18, Q19
HUF76129D3S
DPAK
Fairchild
HUF76129D3S
0
R1, R9, R10, R20
10k
SM/R_0805
Various
DNP
2
R7, R12
909
SM/R_0805
Various
1%
0
R2, R17
909
SM/R_0805
Various
DNP
11
AN1044.2
April 4, 2006
Application Note 1044
Bill of Materials (Continued)
QUANTITY
REFERENCE
DESCRIPTION
PACKAGE
VENDOR
PART NO.
5
R3, R8, R13, R18, R24
0
SM/R_0603
Various
1%
2
R4, R6
1k
SM/R_0805
Various
1%
3
R5, R27, R30
10k
SM/R_0603
Various
1%
1
R11
6.04k
SM/R_0603
Various
1%
1
R14
51.1K
SM/R_0603
Various
1%
2
R22, R15
22.1k
SM/R_0603
Various
1%
1
R16
750 (only 1% on board)
SM/R_0603
Various
0.1%
1
R19
499 (only 1% on board)
SM/R_0603
Various
0.1%
1
R21
750
SM/R_0603
Various
1%
1
R23
499
SM/R_0603
Various
1%
2
R25, R28
3.01
SM/R_0603
Various
1%
2
R26, R29
10
SM/R_0603
Various
1%
1
R31
46.4k
SM/R_0603
Various
1%
2
R32, R35
0.1
SM/R_2512
Panasonic
1%
2
R33, R36
DNP
SM/R_2512
Various
DNP
1
R34
1k
SM/R_0603
Various
1%
1
SW1
DPST SWITCH
Grayhill
76SB02
1
TP1
VIN
TP
Keystone
5002
1
TP2
PHASE 4
TP
Keystone
5002
1
TP3
GND
TP
Keystone
5002
1
TP4
PHASE 1
TP
Keystone
5002
1
TP5
PGOOD
TP
Keystone
5002
1
TP6
COMP
TP
Keystone
5002
1
TP7
PHASE 2
TP
Keystone
5002
1
TP8
PHASE 3
TP
Keystone
5002
1
TP9
VOUT
PROBE-SOCKET
Tektronics
1314353-00
1
TP10
VOUT
TP
Keystone
5002
1
TP11
LOAD CURRENT
PROBE-SOCKET
Tektronics
1314353-00
4
U1, U2, U4, U5
ISL6609CR
MLFP8_3X3
Intersil
ISL6609CR
1
U3
ISL6558IR
MLFP20_5X5
Intersil
ISL6558IR
1
U6
HIP2100IB
SOIC8
Intersil
HIP2100
4
R37-R40
499k
SM/R_0603
Various
1%
0
C100, R41
DNP
SM/R_0603
Various
DNP
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
AN1044.2
April 4, 2006
Application Note 1044
FIGURE 16. TOP LAYER SILK SCREEN
FIGURE 17. BOTTOM LAYER SILK SCREEN
13
AN1044.2
April 4, 2006
Application Note 1044
FIGURE 18. TOP LAYER COMPONENT SIDE
FIGURE 19. LAYER 2
14
AN1044.2
April 4, 2006
Application Note 1044
FIGURE 20. LAYER 3
FIGURE 21. LAYER 4
15
AN1044.2
April 4, 2006
Application Note 1044
FIGURE 22. LAYER 5
FIGURE 23. BOTTOM LAYER COMPONENT SIDE
16
AN1044.2
April 4, 2006
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