Application Note 1773 Author: Jun Liu ISL78205EVAL2Z Evaluation Board Setup Procedure The ISL78205EVAL2Z board is used to demonstrate the compact size and operations of synchronous/asynchronous buck using the ISL78205. The ISL78205EVAL2Z board input voltage range is 3V to 40V. The output voltage is set to 5V and can be changed by using the voltage feedback resistors. Note that to change to a higher output voltage, the output capacitors’ voltage ratings have to be checked. The board output current is 2A typical. The board is set at to a default overcurrent threshold of 3.6A. The OC threshold can be programmed by R15 at the ILIMIT pin. The ISL78205EVAL2Z board has an optional diode D1 for asynchronous buck configuration. The board is set to a default frequency of 500kHz. The frequency can be programmed by R8 at the FS pin. The board can be synchronized to the external clock. Multiple ISL78205EVAL2Z boards can be synchronized simply by connecting their SYNC pins together. Recommended Equipment • 0V to 40V power supply with at least 3A source current capability • Load capable of sinking current up to 3A • Multimeters • Oscilloscope Quick Startup 1. Connect the power source to the input terminals P1(VIN+) and P2(GND). Connect the load terminals to the buck outputs P3(VOUT+) and P4(GND). Make sure the setup is correct prior to applying any power or load to the board. 2. Adjust the power source to 12V and turn it on. 3. Verify the output voltage is 5V and use the oscilloscope to monitor the phase node waveforms through JP2. Asynchronous Buck Configuration To configure the board to asynchronous buck, remove R19 and change R20 (on bottom of the board) to 0Ω to ensure that Q1 is securely off. FIGURE 1A. TOP FIGURE 1B. BOTTOM FIGURE 1. ISL78205EVAL2Z BOARD IMAGES August 6, 2012 AN1773.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright Intersil Americas Inc. 2012. All Rights Reserved. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1773 TABLE 1. CONNECTORS/TEST POINTS DESCRIPTIONS REF DES NAME DESCRIPTION P1 VIN+ Positive terminal of buck inputs. P2 GND Ground terminal of buck inputs. P3 VOUT+ Positive terminal of buck outputs. P4 GND Ground terminal of buck outputs. TP1 VOUT+ TP2 GND TP3 PGOOD TP4 SYNC TP5 VCC Test point used to monitor VCC. TP10 VIN+ Test point for VIN+. TP11 GND Ground test point used for monitoring inputs. JP1 EN JP2 PHASE Test point for VOUT+. Ground test point used for monitoring outputs. Test point used to monitor PGOOD. Used for synchronization configuration. Option 1: to apply external clock for the IC to be synchronized with. Option 2: to synchronize multiple ISL78205, simply connect those SYNC pins together. Use this connector to control IC ON/OFF. Test points used to monitor PHASE node waveforms. For monitoring purposes only. Do not short it with jumper. 2 AN1773.0 August 6, 2012 ISL78205EVAL2Z Board Schematic 8 7 6 5 4 3 2 1 D D TP10 VIN+ P1 BOOT C22 0.1UF U1 1UF C3 ISL78205AVEZ E C12 10UF C11 10UF C10 TP2 PGOOD R5 +5V/2A TP3 E P3 VOUT+ 10UF SQS462EN D1 5 6 7 8 Q1 4 R20 5.1K PDS360-13 0 1 2 3 R2 R19 E 10K EPAD VCC COMP FB R15 FB C8 E 10UH OPEN COMP SS 0.015UF C4 ILIMIT FS C VOUT+ E P4 GND GND B C7 44.2K R4 3.92K 330PF R3 232K E A A DRAWN BY: RELEASED BY: UPDATED BY: JUN LIU TIM KLEMANN DATE: ENGINEER: DATE: TITLE: 02/14/2012 DATE: 03/01/2012 TESTER JUN LIU ISL78205 EVALUATION BOARD SCHEMATIC MASK# FILENAME: ~/ISL78205/ISL78205EVAL2ZA 8 7 6 5 4 FIGURE 2. ISL78205EVAL2Z BOARD SCHEMATIC 3 2 DATE: HRDWR ID SHEET REV. 1 1 OF A 1 Application Note 1773 E E PHASE PGOOD DGND EN B E TP1 L1 OPEN E E SS D1 IS AN OPTIONAL DIODE FOR ASYNCHRONOUS BUCK CONFIGURATION TP4 JP2 PHASE PGOOD NC FS R8 PHASE VCC 4.7UF OPEN VIN SGND C1 EN JP1 NC 10.2K VCC TP5 VIN LGATE SYNC C9 E GND SYNC 150PF GND LGATE BOOT E VIN+ TP11 E E P2 C PGND R7 C21 2.2UF C20 2.2UF 3 VIN+ AN1773.0 August 6, 2012 Application Note 1773 Board Layouts FIGURE 3. SILKSCREEN TOP COMPONENTS FIGURE 4. TOP LAYER FIGURE 5. 2 nd LAYER FIGURE 6. 3 rd LAYER 4 AN1773.0 August 6, 2012 Application Note 1773 Board Layouts (Continued) FIGURE 7. BOTTOM LAYER FIGURE 8. SILKSCREEN BOTTOM COMPONENTS FIGURE 9. TOP COMPONENT ASSEMBLY FIGURE 10. BOTTOM COMPONENT ASSEMBLY (MIRRORED) 5 AN1773.0 August 6, 2012 Application Note 1773 TABLE 2. BILL OF MATERIALS REF DES PART NUMBER QTY DESCRIPTION MANUFACTURER C3 C1608X7R1C105K 1 CAP, SMD, 0603, 1.0µF, 16V, 10%, X7R, ROHS TDK C10, C11, C12 C3216X7R1C106K 3 CAP, SMD, 1206, 10µF, 16V, 10%, X7R, ROHS TDK C1 GRM21BR71A475KA73L 1 CAP, SMD, 0805, 4.7µF, 10V, 10%, X7R, ROHS MURATA C20, C21 GRM31CR71H225KA88L 2 CAP, SMD, 1206, 2.2µF, 50V, 10%, X7R, ROHS MURATA C8 ECU-E1H151KBQ 1 CAP, SMD, 0402, 150pF, 50V, 10%, NP0, ROHS PANASONIC C4 VARIOUS 1 CAP, SMD, 0402, 0.015µF, 16V, 10%, X7R, ROHS VARIOUS C7 VARIOUS 1 CAP, SMD, 0402, 330pF, 50V, 10%, X7R, ROHS VARIOUS C9 N/A 0 CAP, SMD, 0402, DNP-PLACE-HOLDER, ROHS N/A C22 VARIOUS 1 CAP, SMD, 0603, 0.1µF, 50V, 10%, X7R, ROHS VARIOUS L1 SD8350-100-R 1 COIL-PWR INDUCTOR, SMD, 9.5X8.3, 10µH, 20%, 4A, 31.4mΩ, ROHS COILTRONICS D1 PDS360-13 1 DIODE-SCHOTTKY, SMD, POWERDI5, 60V, 3A, ROHS DIODES INC. U1 ISL78205AVEZ 1 IC-2.5A BUCK CONTROLLER, 20P, HTSSOP, ROHS INTERSIL Q1 SQS462EN 1 TRANSISTOR-MOS, N-CHANNEL, 8P, PWRPAK, 60V, 8A, ROHS VISHAY R19 VARIOUS 1 RES, SMD, 0402, 0Ω, 1/16W, 5%,ROHS VARIOUS R2 VARIOUS 1 RES, SMD, 0402, 10k, 1/16W, 1%, ROHS VARIOUS R7 VARIOUS 1 RES,SMD, 0402, 10.2k, 1/16W, 1%, ROHS VARIOUS R3 VARIOUS 1 RES, SMD, 0402, 232k, 1/16W, 1%, ROHS VARIOUS R5 VARIOUS 1 RES,SMD, 0402, 3.92k, 1/16W, 1%, ROHS VARIOUS R4 VARIOUS 1 RES, SMD ,0402, 44.2k, 1/16W, 1%, ROHS VARIOUS R20 VARIOUS 1 RES, SMD, 0402, 5.1k, 1/16W, 1%, ROHS VARIOUS R8, R15 N/A 0 RES, SMD, 0402, DNP-PLACE-HOLDER, ROHS N/A Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 6 AN1773.0 August 6, 2012