IDT74LVCH32245A 3.3V CMOS 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE IDT74LVCH32245A 3.3V CMOS 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD FEATURES: DESCRIPTION: • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range µ W typ. static) • CMOS power levels (0.4µ • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in 96-ball LFBGA package This 32-bit bus transceiver is built using advanced dual metal CMOS technology. This high-speed, low power transceiver is ideal for asynchronous communication between two busses (A and B). The Direction and Output Enable controls are designed to operate the device as either four independent 8-bit transceivers or one 32-bit transceiver. The direction control pins (DIR) control the direction of data flow. The output enable pins (OE) override the direction control and disable both ports. All inputs are designed with hysteresis for improved noise margin. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVCH32245A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance The LVCH32245A has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. DRIVE FEATURES: • Balanced Output Drivers: ±24mA • Reduced system switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1DIR A3 3DIR J3 A4 J4 1OE 1A1 A5 3A1 A2 J2 1B1 TO SEVEN OTHER CHANNNELS 2DIR 3B1 TO SEVEN OTHER CHANNNELS H3 4DIR T3 T4 H4 2OE 2A1 3OE J5 4OE E5 4A1 E2 N5 N2 2B1 TO SEVEN OTHER CHANNNELS 4B1 TO SEVEN OTHER CHANNNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE FEBRUARY 2000 1 ©2000 Integrated Device Technology, Inc. DSC-4767/1 IDT74LVCH32245A 3.3V CMOS 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION 6 1A2 1A4 1A6 1A8 2A2 2A4 2A6 2A7 3A2 3A4 3A6 3A8 4A2 4A4 4A6 4A7 5 1A1 1A3 1A5 1A7 2A1 2A3 2A5 2A8 3A1 3A3 3A5 3A7 4A1 4A3 4A5 4A8 4 1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE 3 1DIR GND VCC GND GND VCC GND 2DIR 3DIR GND VCC GND GND VCC GND 4DIR 2 1B1 1B3 1B5 1B7 2B1 2B3 2B5 2B8 3B1 3B3 3B5 3B7 4B1 4B3 4B5 4B8 1 1B2 1B4 1B6 1B8 2B2 2B4 2B6 2B7 3B2 3B4 3B6 3B8 4B2 4B4 4B6 4B7 B C D E F G H M N R T A L K J LFBGA TOPVIEW 96 BALL LFBGA PACKAGE ATTRIBUTES 1.5 mm Max. 1.4 mm Nom. 1.3 mm Min. 0.8mm 6 5 TOP VIEW 4 3 2 1 A B C D E F G H J K L M N P R T A B C D E F G H J K L M N P R T 1 2 3 5.5mm 4 5 6 13.5mm 2 P IDT74LVCH32245A 3.3V CMOS 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –50 to +50 mA IIK IOK Continuous Clamp Current, VI < 0 or VO < 0 –50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA INDUSTRIAL TEMPERATURE RANGE CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 6.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF NOTE: 1. As applicable to the device type. NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTION TABLE(1) PIN DESCRIPTION Pin Names xOE Inputs Description Output Enable Input (Active LOW) xOE xDIR Outputs xDIR Direction Control Input L L Bus B data to Bus A xAx Side A Inputs or 3-State Outputs(1) L H Bus A data to Bus B xBx Side B Inputs or 3-State Outputs(1) H X Z NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Bus-Hold Input Sustain Current VCC = 3V Bus-Hold Input Sustain Current VCC = 2.3V IBHL IBHHO Bus-Hold Input Overdrive Current Typ.(2) Max. Unit – 75 — — µA VI = 0.8V 75 — — VI = 1.7V — — — VI = 0.7V — — — VI = 0 to 3.6V — — ±500 VI = 2V IBHL IBHH Min. Test Conditions VCC = 3.6V IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3 µA µA IDT74LVCH32245A 3.3V CMOS 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 — — 10 mV µA 3.6 ≤ VIN ≤ 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND — — — — 10 500 µA IIH IIL Quiescent Power Supply Current Variation NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. OUTPUT DRIVE CHARACTERISTICS Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage Min. Max. Unit VCC – 0.2 — V IOH = – 6mA 2 — IOH = – 12mA 1.7 — 2.2 — VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage 2.4 — VCC = 3V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. 4 IDT74LVCH32245A 3.3V CMOS 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance per Transceiver Outputs enabled CPD Power Dissipation Capacitance per Transceiver Outputs disabled Test Conditions Typical Unit CL = 0pF, f = 10Mhz 76 pF 8 SWITCHING CHARACTERISTICS(1) VCC = 2.7V Symbol VCC = 3.3V ± 0.3V Parameter Min. Max. Min. Max. Unit tPLH Propagation Delay 1.5 4.7 1 4 ns 1.5 6.7 1.5 5.5 ns 1.5 7.1 1.5 6.6 ns 1.5 7 1.5 5.5 ns 1.5 7.4 1.5 6.6 ns — — — 500 ps tPHL xAx to xBx, xBx to xAx tPZH Output Enable Time tPZL xOE to xAx or xBx tPHZ Output Disable Time tPLZ xOE to xAx or xBx tPZH Output Enable Time tPZL xDIR to xAx or xBx tPHZ Output Disable Time tPLZ xDIR to xAx or xBx tSK(o) Output Skew(2) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 5 IDT74LVCH32245A 3.3V CMOS 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF Pulse (1, 2) Generator VIN tPZL GND OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH CL tPLZ VLOAD/2 VT VLOAD/2 VLZ VOL tPHZ VOH VHZ 0V VT 0V LVC Link Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. DATA INPUT SWITCH POSITION Test Switch TIMING INPUT Open Drain Disable Low Enable Low VLOAD ASYNCHRONOUS CONTROL Disable High Enable High GND SYNCHRONOUS CONTROL All Other Tests Open tSK (x) tREM tSU tH LOW-HIGH-LOW PULSE VOH VT VOL VT tW HIGH-LOW-HIGH PULSE VT LVC Link Pulse Width tPHL2 tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) tH Set-up, Hold, and Release Times VOH VT VOL OUTPUT 2 tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V LVC Link VIH VT 0V tPHL1 tPLH2 VIH VT 0V LVC Link NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. tSK (x) DISABLE ENABLE DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. OUTPUT 1 VIH VT 0V CONTROL INPUT 500Ω tPLH1 tPHL Propagation Delay D.U.T. Test Circuit for All Outputs INPUT tPLH LVC Link VOUT RT tPHL OPPOSITE PHASE INPUT TRANSITION Open 500Ω tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION LVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 6 IDT74LVCH32245A 3.3V CMOS 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION X LVC IDT XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 BF Low-Profile Fine Pitch Ball Grid Array 245A 32-bit Bus Transceiver with 5 Volt Tolerant I/O 32 32-bit Bus Density, ±24mA H Bus-hold 74 -40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 7 for Tech Support: [email protected] (408) 654-6459