DATASHEET

ISL8011
®
Data Sheet
August 4, 2009
1.2A Integrated FETs, High Efficiency
Synchronous Buck Regulator
FN9254.2
Features
ISL8011 is an integrated FET, 1.2A synchronous buck
regulator for general purpose point-of load applications. It is
optimized for generating low output voltages down to 0.8V.
The supply voltage range is from 2.7V to 5.5V allowing the
use from common 3.3V or 5V supply rails and Lithium ion
battery inputs. It has guaranteed minimum output current of
1.2A. 1.5MHz pulse-width modulation (PWM) switching
frequency allowing the use of small external components.
• High Efficiency Synchronous Buck Regulator with Up to
95% Efficiency
• 2.7V to 5.5V Supply Voltage
• 1.2A Output Current
• 100% Maximum Duty Cycle
• Peak Current Limiting, Short Circuit Protection
• 200ms Power-On Reset
The ISL8011 includes a pair of low ON-resistance P-Channel
and N-Channel internal MOSFETs to maximize efficiency
and minimize external component count. 100% duty-cycle
operation allows less than 200mV dropout voltage at 1.2A.
• 3% Output Accuracy Over-Temperature/Load/Line
The ISL8011 offers a 200ms Power-On-Reset (POR) timer
at power-up. When shutdown, the ISL8011 discharges the
output capacitor. Other features include internal digital
soft-start, enable for power sequence, overcurrent
protection, and thermal shutdown.
• Internal Digital Soft-Start
The ISL8011 is offered in a 10 Ld 3mmx3mm DFN package
with 1mm maximum height. The complete converter
occupies less than 1cm2 area.
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
• Less than 1µA Logic Controlled Shutdown Current
• Internal Loop Compensation
• Over-Temperature Protection
• Enable
• Small 10 Ld 3mmx3mm DFN
• Pb-Free (RoHS Compliant)
Applications
• DC/DC POL Modules
• µC/µP, FPGA and DSP Power
PACKAGE
(Pb-Free)
PKG.
DWG. #
• Plug-in DC/DC Modules for Routers and Switchers
011Z
-40 to +85 10 Ld 3x3 DFN L10.3x3C
• Portable Instruments
ISL8011IRZ-T* 011Z
-40 to +85 10 Ld 3x3 DFN L10.3x3C
Tape and Reel
• Test and Measurement Systems
ISL8011IRZ
Pinout
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
1
ISL8011
(10 LD 3x3 DFN)
TOP VIEW
PVIN
1
10 PHASE
VCC
2
9 PGND
EN
3
8 SGND
POR
4
7 FB
GND
5
6 N/C
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8011
Absolute Maximum Ratings (Reference to SGND)
Thermal Information
Supply Voltage (PVIN, VCC) . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
EN, MODE, PHASE, POR . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3V
FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Thermal Resistance (Notes 1, 2)
θJA (°C/W)
θJC (°C/W)
10 Ld 3x3 DFN Package . . . . . . . . . . .
48
5
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
PVIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.2A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to +85°C
AUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
TA = +25°C, VPVIN = VVCC = 3.6V, EN = VCC, L = 1.8µH, C1 = 10µF, C2 = 10µF, IOUT = 0A (see “Typical
Applications” on page 6); Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Rising
-
2.5
2.7
V
Falling
2.2
2.4
-
V
No load at the output
-
5
8
mA
-
0.1
2
µA
SUPPLY
VCC Undervoltage Lockout Threshold
VUVLO
Quiescent Supply Current
IPVIN
Shut Down Supply Current
ISD
VCC = PVIN = 5.5V, EN = low
VFB
TA = 0°C to +85°C
0.784
0.8
0.816
V
TA = -40°C to +85°C
0.78
0.8
0.82
V
FB = 0.75V
-
0.1
-
µA
Output Voltage Accuracy
PVIN = VO + 0.5V to 5.5V, IO = 0A to 1.2A,
TA = -40°C to +85°C
-3
-
3
%
Line Regulation
PVIN = VO + 0.5V to 5.5V (minimal 2.7V)
-
0.2
-
%/V
1.2
-
-
A
Adjustable version, design info only
-
20
-
µA/V
PVIN = 3.6V, IO = 200mA
-
0.12
0.22
Ω
PVIN = 2.7V, IO = 200mA
-
0.16
0.27
Ω
PVIN = 3.6V, IO = 200mA
-
0.11
0.22
Ω
PVIN = 2.7V, IO = 200mA
-
0.15
0.27
Ω
1.5
2.1
2.6
A
-
100
-
%
1.35
1.6
1.75
MHz
PHASE Minimum On Time
-
-
140
ns
Soft Start-Up Time
-
1.1
-
ms
OUTPUT REGULATION
FB Regulation Voltage
FB Bias Current
IFB
Maximum Output Current
COMPENSATION
Error Amplifier Trans-conductance
PHASE
P-Channel MOSFET On-Resistance
N-Channel MOSFET On-Resistance
P-Channel MOSFET Peak Current Limit
IPK
PHASE Maximum Duty Cycle
PWM Switching Frequency
fS
2
TA = -40°C to +85°C
FN9254.2
August 4, 2009
ISL8011
Electrical Specifications
TA = +25°C, VPVIN = VVCC = 3.6V, EN = VCC, L = 1.8µH, C1 = 10µF, C2 = 10µF, IOUT = 0A (see “Typical
Applications” on page 6); Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
-
0.3
V
150
200
275
ms
-
0.01
0.1
µA
1.2
-
-
V
POR
Output Low Voltage
Sinking 1mA, FB = 0.7V
Delay Time
POR Pin Leakage Current
POR = VCC = 3.6V
Minimum Supply Voltage for Valid POR Signal
Internal PGOOD Low Rising Threshold
Percentage of Nominal Regulation Voltage
89.5
92
94.5
%
Internal PGOOD Low Falling Threshold
Percentage of Nominal Regulation Voltage
85
88
91
%
Internal PGOOD High Rising Threshold
Percentage of Nominal Regulation Voltage
105.5
108
110.5
%
Internal PGOOD High Falling Threshold
Percentage of Nominal Regulation Voltage
102
105
108
%
-
50
-
µs
Logic Input Low
-
-
0.4
V
Logic Input High
1.4
-
-
V
-
0.1
1
µA
Thermal Shutdown
-
150
-
°C
Thermal Shutdown Hysteresis
-
25
-
°C
Internal PGOOD Delay Time
EN
Logic Input Leakage Current
Pulled up to 5.5V
Typical Operating Performance
2.60
100
VOUT = 3.3V
2.55
VOUT = 1.8V
VOUT = 2.5V
80
VOUT (V)
EFFICIENCY (%)
90
2.50
2.45
70
60
50
200
350
500
650
800
950
1100
LOAD CURRENT (mA)
FIGURE 1. EFFICIENCY vs LOAD CURRENT (VIN = 5.0V)
3
2.40
50
250
450
650
850
1050
LOAD CURRENT (mA)
FIGURE 2. VOUT vs LOAD CURRENT (VIN = 5V)
FN9254.2
August 4, 2009
ISL8011
Typical Operating Performance
(Continued)
1.605
7
SWITCHING FREQUENCY (MHz)
VO = 2.8V
INPUT CURRENT (mA)
6
5
4
3
2
1
0
2.9
3.4
3.9
4.4
4.9
1.600
1.595
1.590
1.585
1.580
1.575
1.570
2.7
5.4
3.2
3.7
4.2
4.7
5.2
VIN (V)
VIN VOLTAGE RANGE (2.9V to 5.5V)
FIGURE 3. IQ vs VIN
FIGURE 4. SWITCHING FREQUENCY vs VIN
1.610
1.610
1.608
1.605
VO (V)
VO (V)
1.606
1.604
1.595
1.602
1.600
1.600
2.7
3.7
4.7
5.7
1.590
0
200
400
VIN (V)
600
800
1000
IO (mA)
FIGURE 5. LINE REGULATION (IO = 1A)
FIGURE 6. LOAD REGULATION (VIN = 3.6V)
EN
VOUT
VPHASE
VOUT
OUT
IL
IL
FIGURE 7. SOFT-START
4
FIGURE 8. STEADY-STATE (VIN = 3.6V; VO = 1.6V; IO = 1A)
FN9254.2
August 4, 2009
ISL8011
Typical Operating Performance
(Continued)
VOUT
VPHASE
IO
IL
FIGURE 9. LOAD TRANSIENT (VIN = 3.6V; VO = 1.6V; IO = 0A TO ~1A)
Pin Descriptions
FB
PVIN
Buck regulator output feedback. Connect to the output
through a resistor divider for adjustable the output voltage.
Input supply voltage. Connect a 10µF ceramic capacitor to
power ground.
VCC
Supply voltage for internal analog and digital control circuits,
delivered from PVIN. Bypass with 0.1µF ceramic capacitor to
signal ground.
EN
Regulator enable pin. Force this pin above 1.4V enable the
chip. Force this pin below 0.4V shutdown the chip and
discharge output capacitor when driven to low. Do not leave
this pin floating.
Exposed Pad
The exposed pad must be connected to the PGND pin for
proper electrical performance and optimal thermal
performance.
NC
NC is the No Connect pin. Tie this pin to SGND to prevent
noise.
POR
200ms timer output. At power-up or EN HI, this output is a
200ms delayed Power-Good signal for the output voltage.
GND
Ground. Connect this pin to the exposed pad and SGND.
PHASE
Switching node connection. Connect to one terminal of
inductor.
PGND
Power ground. Connect all power grounds to this pin.
SGND
Analog ground. SGND and PGND should only have one
point connection.
5
FN9254.2
August 4, 2009
ISL8011
Typical Applications
ISL8011
VIN
2.7V TO 5.5V
PVIN
L
PHASE
1.8µH
C1
10µF
VCC
C3
0.1µF
PGND
C2
10µF
VOUT
1.3V, 1.2V
R2
61.9kΩ
SGND
R3
100kΩ
EN
FB
R1
100kΩ
POR
GND
FIGURE 10. TYPICAL APPLICATION FOR ADJUSTABLE VERSION
Block Diagram
VCC
SHUTDOWN
30pF
SOFT-START
50Ω
PVIN
SHUTDOWN
270kΩ
OSCILLATOR
EN
BANDGAP
+
EA
PHASE
+
COMP
-
0.8V
PWM CONTROL
AND DRIVERS
PGND
+
SLOPE
COMPENSATION
FB
+
CSA1
-
0.864V
+
OCP
-
+
0.85V
+
0.736V
ZC
-
+
CSA2
-
POR
200ms
DELAY
0.2V
SCP
+
SGND
GND
FIGURE 11. FUNCTIONAL BLOCK DIAGRAM
6
FN9254.2
August 4, 2009
ISL8011
Theory of Operation
Short-Circuit Protection
ISL8011 is an integrated FET, 1.2A synchronous buck
A short-circuit protection (SCP) comparator monitors the FB
pin voltage for output short-circuit protection. When the FB is
lower than 0.2V, the SCP comparator forces the PWM
oscillator frequency to drop to 1/3 of the normal operation
value. This comparator is effective during start-up or an
output short-circuit event.
regulator for general purpose point-of load applications. The
regulator operates at 1.5MHz fixed switching frequency
under heavy load condition to allow small external inductor
and capacitors to be used for minimal printed-circuit board
(PCB) area. The supply current is typically only 0.1µA when
the regulator is shut down.
PWM Control Scheme
V EAMP
The ISL8011 employs the current-mode pulse-width
modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting. Figure 11
shows the block diagram. The current loop consists of the
oscillator, the PWM comparator COMP, current sensing
circuit, and the slope compensation for the current loop
stability. The current sensing circuit consists of the
resistance of the P-Channel MOSFET when it is turned on
and the current sense amplifier (CSA1). The gain for the
current sensing circuit is typically 0.4V/A. The control
reference for the current loops comes from the error
amplifier EAMP of the voltage loop.
V CSA1
The PWM operation is initialized by the clock from the
oscillator. The P-Channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the MOSFET
starts to ramp up. When the sum of the CSA1 and the
compensation slope (0.675V/µs) reaches the control
reference of the current loop, the PWM comparator COMP
sends a signal to the PWM logic to turn off the P-MOSFET
and to turn on the N-Channel MOSFET. The N-MOSFET
stays on until the end of the PWM cycle. Figure 12 shows
the typical operating waveforms during the PWM operation.
The dotted lines illustrate the sum of the compensation ramp
and the CSA1 output.
The output voltage is regulated by controlling the reference
voltage to the current loop. The bandgap circuit outputs a
0.8V reference voltage to the voltage control loop. The
feedback signal comes from the FB pin. The soft-start block
only affects the operation during the start-up and will be
discussed separately shortly. The error amplifier is a
transconductance amplifier that converts the voltage error
signal to a current output. The voltage loop is internally
compensated with the 25pF and 400kΩ RC network. The
maximum EAMP voltage output is precisely clamped to the
bandgap voltage (1.172V).
Overcurrent Protection
The overcurrent protection is realized by monitoring the
CSA1 output with the OCP comparator, as shown in
Figure 11. The current sensing circuit has a gain of 0.4V/A,
from the N-MOSFET current to the CSA1 output. When the
CSA1 output reaches 1V, which is equivalent to 2.5A for the
switch current, the OCP comparator is tripped to turn off the
P-MOSFET immediately.
7
Duty
Cycle
IL
V OUT
FIGURE 12. PWM OPERATION WAVEFORMS
POR Signal
The ISL8011 offers a power-on reset (POR) signal for
resetting the microprocessor at the power-up. When the
output voltage is not within a power-good window, the POR
pin outputs an open-drain low signal to reset the
microprocessor. The output voltage is monitored through the
FB pin. When the voltage of the monitored node is within the
window of 0.736V and 0.864V, a power-good signal is issued
to turn off the open-drain POR pin. The rising edge of the
POR output is delayed by 200ms.
UVLO
When the input voltage is below the undervoltage lock out
(UVLO) threshold, the regulator is disabled.
Soft Start-Up
The soft start-up eliminates the inrush current during the
start-up. The soft-start block outputs a ramp reference to
both the voltage loop and the current loop. The two ramps
limit the inductor current rising speed as well as the output
voltage speed so that the output voltage rises in a controlled
fashion. At the very beginning of the start-up, the output
voltage is less than 0.2V; hence the PWM operating
frequency is 1/3 of the normal frequency. Figure 7 shows the
start-up waveforms.
Power MOSFETs
The power MOSFETs are optimized for best efficiency. The
ON-resistance for the P-MOSFET is typically 150mΩ and
the ON-resistance for the N-MOSFET is typically 150mΩ.
100% Duty Cycle
The ISL8011 features 100% duty cycle operation to
maximize the battery life. When the battery voltage drops to
FN9254.2
August 4, 2009
ISL8011
a level that the ISL8011 can no longer maintain the
regulation at the output, the regulator completely turns on
the P-MOSFET. The maximum drop out voltage under the
100% duty-cycle operation is the product of the load current
and the ON-resistance of the P-MOSFET.
TABLE 1. OUTPUT CAPACITOR VALUE vs VOUT
VOUT
COUT
L
0.8V
10µF
1.0µH~2.2µH
1.2V
10µF
1.2µH~2.2µH
Enable
1.6V
10µF
1.8µH~2.2µH
The enable (EN) input allows user to control the turning on
or off the regulator for purposes such as power-up
sequencing. The the regulator is enabled, there is typically a
300µs delay for waking up the bandgap reference. Then the
soft start-up begins. When the regulator is disabled, the
P-MOSFET is turned off immediately and the N-MOSFET is
turned on.
1.8V
10µF
1.8µH~3.3µH
2.5V
10µF
1.8µH~3.3µH
3.3V
6.8µF
1.8µH~4.7µH
3.6V
4.7µF
1.8µH~4.7µH
The ISL8011 has built-in thermal protection. When the
internal temperature reaches +150°C, the regulator is
completely shut down. As the temperature drops to +130°C,
the ISL8011 resumes operation by stepping through a soft
start-up.
VCC By-Passing
The VCC is voltage is the supply to the internal control circuit
and is derived from the PVIN pin. An internal 5Ω resistor
connects the two pins and also serves as an filtering resistor.
An external 0.1µF ceramic capacitor is recommended to
by-pass the VCC supply.
Applications Information
Output Inductor and Capacitor Selection
To consider state steady and transient operation, ISL8011
typically uses a 1.8µH output inductor. Higher or lower
inductor values can be used to optimize the total converter
system performance. For example, for higher output voltage
3.3V application, in order to decrease the inductor current
ripple and output voltage ripple, the output inductor value
can be increased as shown in Table 1. The inductor ripple
current can be expressed as shown in Equation 1:
VO ⎞
⎛
V O • ⎜ 1 – ---------⎟
V IN⎠
⎝
ΔI = --------------------------------------L • fS
(EQ. 1)
The inductor’s saturation current rating needs be at least
larger than the peak current. The maximum peak current of
ISL8011 is 2.1A. The saturation current needs be over 2.1A
for maximum output current application.
ISL8011 uses internal compensation network and the output
capacitor value is dependent on the output voltage. The
ceramic capacitor is recommended to be X5R or X7R. The
recommended minimum output capacitor values are shown
in Table 1.
8
600
OUTPUT CAPACITOR VALUE (µF)
Thermal Shut Down
In Table 1, the minimum output capacitor value is given for
different output voltage to make sure the whole converter
system stable. Due to the limitation on power dissipation
when the regulator disable and discharge output capacitor,
there is the maximum output capacitor value. The maximum
output capacitor value is variable with the output voltage.
The plot curve is shown in Figure 13.
505
410
315
220
125
30
0.8
1.27
1.73
2.2
2.67
OUTPUT VOLTAGE (V)
3.13
3.6
FIGURE 13. THE MAXIMUM CAP vs THE OUTPUT VOLTAGE
Input Capacitor Selection
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current flowing back to the
supply rail. A 10µF X5R or X7R ceramic capacitor is a good
starting point for the input capacitor selection.
Output Voltage Setting Resistor Selection
The resistors R2 and R3 shown in Figure 10 set the output
voltage for the adjustable version. The output voltage can be
calculated by using Equation 2:
R 2⎞
⎛
V O = 0.8 • ⎜ 1 + -------⎟
R 3⎠
⎝
(EQ. 2)
where the 0.8V is the reference voltage. To minimize the
accuracy impact on the output voltage, select the R2 and R3
no larger than 100kΩ.
FN9254.2
August 4, 2009
ISL8011
Layout Recommendation
The layout is a very important converter design step to make
sure the designed converter works well. For ISL8011 buck
converter, the power loop is composed of the output inductor
L, the output capacitor COUT, Phase pin and PGND pin. It is
necessary to make the power loop as small as possible. In
order to make the output voltage regulate well and avoid the
noise coupling from the power loop, SGND pin should be
connected with PGND pin at the terminals of the load.
The heat of the IC is mainly dissipated through the thermal
pad. Maximizing the copper area connected to the thermal
pad is preferable. In addition, a solid ground plane is helpful
for EMI performance.
9
FN9254.2
August 4, 2009
ISL8011
Dual Flat No-Lead Plastic Package (DFN)
L10.3x3C
2X
0.10 C A
A
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.10 C B
E
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.85
0.90
0.95
-
A1
-
-
0.05
-
A3
6
INDEX
AREA
b
0.20 REF
0.20
D
TOP VIEW
B
D2
//
A
C
SEATING
PLANE
D2
6
INDEX
AREA
0.08 C
7
8
D2/2
1
2.33
2.38
2.43
7, 8
1.69
7, 8
3.00 BSC
1.59
e
1.64
-
0.50 BSC
-
k
0.20
-
-
-
L
0.35
0.40
0.45
8
N
10
2
Nd
5
3
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
E2
E2/2
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
NX L
N
N-1
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX b
e
(Nd-1)Xe
REF.
BOTTOM VIEW
5
0.10 M C A B
(A1)
9 L
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
CL
NX (b)
5, 8
Rev. 1 4/06
2
(DATUM A)
8
0.30
3.00 BSC
E
E2
A3
SIDE VIEW
(DATUM B)
0.10 C
0.25
-
9. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.
e
SECTION "C-C"
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN9254.2
August 4, 2009
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