an1528

Application Note 1528
ISL8120EVAL3Z Evaluation Board Setup Procedure
Description
Recommended Equipment
The ISL8120 integrates two voltage mode synchronous buck
PWM controllers. It can be used either for dual independent
outputs or a 2-phase single output regulator.
• 0V to 22V power supply with at least 20A source current
capability, battery, or notebook AC adapter.
The ISL8120EVAL3Z evaluation board is for performance demo
of the dual independent outputs and DDR applications.
• Digital multimeters (DMMs).
The ISL8120EVAL4Z evaluation board is used for performance
demo of 2/n-phase single-output applications. Refer to
application note AN1607 “ISL8120EVAL4Z Evaluation Board
Setup Procedure” for details of the ISL8120EVAL4Z board.
• Two electronic loads capable of sinking current up to 30A
• 100MHz quad-trace oscilloscope.
References
• ISL8120 Datasheet
• AN1607, “ISL8120EVAL4Z Evaluation Board Setup Procedure”
Preset Specifications
Ordering Information
VIN
(V)
FREQUENCY
(kHz)
VOUT1
VOUT2
12
500
1.2V/25A
1.2V/25A
PART NUMBER
ISL8120EVAL3Z
DESCRIPTION
ISL8120 Evaluation Board for
Performance Demo
FIGURE 1. ISL8120EVAL3Z EVALUATION BOARD
June 25, 2015
AN1528.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2010, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Application Note 1528
Circuits Description
J1 and J2 are the input power terminals.
Two input electrolytic capacitors are used to handle the input
current ripples.
Two upper and two lower Renesas “speed” series LFPAK
MOSFETs are used for each channel. Q1 and Q2 are footprint
options for low current applications where a SO8 package
integrating dual MOSFET can be used.
320nH PULSE surface mount inductors are used for each
channel. Under the 500kHz setup, the inductor current
peak-to-peak ripple is 7.5A at 12V input.
Two SANYO POSCAP 2R5TPF470M7L (7mΩ) are used as output
E-caps for each channel. Also, through-hole electrolytic capacitor
footprints C123 ~ C126 are available for the user to evaluate
different output capacitors.
J7, J8, J9 and J10 are output lugs for load connections.
TP19, TP26, TP28 and TP31 are remote sense posts. These pins
can be used to monitor and evaluate the system voltage
regulations. If the user wants to use these test posts for remote
sense, the R109, R120, R155 and R161 need to be changed to
higher values, such as 10Ω. Also, the related voltage sense
divider needs to be increased to a higher resistance, such as 1k.
Q26, Q27, R126, R156, R122, R131, R151, R153 are circuit footprint
options to add an on-board transient load to the regulator. Use a
signal generator to apply a clock signal at TP22 (TP30) to
generate step-up and step-down transient load. Make sure that
the duty cycle of the clock is small enough to avoid burning load
resistors R126 and R156.
JP11 or JP12 are the jumpers used to disable the channels
independently.
TP27 is a post that can be used to inject a clock signal for the
controller to be synchronized with.
JP7 and JP8 are jumpers for rDS(ON) sensing configuring. Also,
these jumpers can be used to monitor the DCR sensing capacitor
voltage.
R94, C74, R163 and C108 are optional footprints for snubbers,
which are used to filter the ringing at phase nodes.
R99, R100, R125, R130, R132, LED4 and Q32 are useless footprints.
R121 and C86 are small added filters for the VIN pin. R145 is used
to isolate the noise at PVCC caused by driving. In 3.3V
applications, R121 and R145, it is recommended to short to 0 to
prevent VCC from going below POR under low input voltage. Also,
it is recommended to add a 2k resistor from LGATE to GND to
discharge the low gate at the state of LGATE OFF.
Evaluating the Other Output
Voltage
The ISL8120EVAL3Z kit outputs are preset to 1.2V/25A, VOUT1
can also be adjusted between 0.6V to 3V by changing the value
of R119 and R116 for VOUT1 as given by Equation 1. The same rule
applies for VOUT2.
R 116
R 119 = ------------------------------------------------ V OUT  V REF  – 1
where VREF = 0.6V
1. Ensure that the circuit is correctly connected to the supply and
loads prior to applying any power.
2. Adjust the input supply to be 12V. Turn on the input power
supply.
2
(EQ. 1)
rDS(ON) Sense Configuration
If the desired output voltage is higher than 3V, the current sense
has to be configured as rDS(ON) sensing because of the common
mode voltage limitation of the current sense differential
amplifier. The default setup of ISL8120EVAL3Z is DCR sensing.
The following steps show how to change to rDS(ON) sensing for
Channel 2:
1. Remove R5 and R6 to be open.
2. Change R4 and R8 to be 0Ω.
3. Short jumper JP1.
Programming the Input Voltage
UVLO and its Hysteresis
By programming the voltage divider at the EN/FF pin connected
to the input rail, the input UVLO and its hysteresis can be
programmed. The ISL8120EVAL3Z has R129 (R136) 13.7k and
R135 (R141) 4.42k; the IC will be disabled when input voltage
drops below 3.38V and will restart until VIN recovers to be above
4.42V.
For 12V applications, it is suggested to have R129 (R136) 33k and
R135 (R141) 5.1k, of which the IC is disabled when the input
voltage drops below 6V and will restart until VIN recovers to be
above 7V.
Refer to equations on page 22 of the ISL8120 datasheet to
program the UVLO falling threshold and hysteresis. The equations
are restated in Equations 2 and 3, where RUP and RDOWN are the
upper and lower resistors of the voltage divider at EN/FF pin.
VHYS is the desired UVLO hysteresis and VFTH is the desired UVLO
falling threshold.
V HYS
R UP = --------------I HYS
where IHYS = 30µA
R UP  V ENREF
R DOWN = -------------------------------------------- where RENREF = 0.8V
V FTH – V ENREF
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3. Verify that the two output voltages are correct. If the PGOOD
is set high, the LED3 will be green. If the PGOOD is set low, the
LED3 will be red. TP24 is the test post to monitor PGOOD.
(EQ. 2)
(EQ. 3)
Note the ISL8120 EN/FF pin is a triple function pin and the
voltages applied to the EN/FF pins are also fed to adjust the
amplitude of each channel’s individual sawtooth.
AN1528.1
June 25, 2015
Application Note 1528
DDR Application
The ISL8120 can be used as a DDR controller. The Typical
Application II schematic in the ISL8120 datasheet shows its
configuration. Channel 1 is used for VDDQ. VDDQ output is fed to
the REFIN pin of Channel 2, thus Channel 2 can track VDDQ at
start-up and supplies as VTT.
Please note the configuration of EN/FF pins for start-up timing.
The VDDQ channel (Channel 1) start-up should be delayed to VTT
(Channel 2) by adding more filtering at EN/FF1 than EN/FF2. This
is to start up the internal SS ramp of Channel 2 and make it
invalid because EN/FF2 is still 0 coming from VDDQ (Channel 1).
Figure 2 shows the reference configurations and parameters of
the EN/FF pins. RA is a resistor externally added as a filter
resistor for EN/FF1.
With the configuration of Figure 2, VDDQ is 1.8V and VTT is 0.9V.
The gain of the resistor divider from VDDQ (Channel 1) to REFIN
pin should have the same value with the resistor divider of VTT
(Channel 2). RB is an externally added resistor for the upper
resistor of the divider from VDDQ output to REFIN.
FIGURE 2. DDR CONFIGURATION
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AN1528.1
June 25, 2015
R94
2.2_DNP
1
VOUT2
2
R95
6.49k
VCC
R96
0
R98
1K
JP7
RED
DNP
C79
DNP
C80
DNP
C123
C124
6SEPC680M
6SEPC680M
1
J7
GND(VOUT2-)
C115
10uF
R103
249
[email protected]
OC=32.5A
GREEN
2
1
C78
DNP
680uF, 7mOhm
R102
0
J8
VOUT2
LED3
Q2A
2
4.7uF_25V_X5R
C77
3
1
5
C76
0.1uF
Q24
RJK0301DPB
34
Q22
RJK0305DPB
Q23
RJK0301DPB
1
2
3
4
3
5
4
3
2
1
5
TP20
VOUT2
1
R97
1K
Q2B
4
C75
C74
2.2nF_DNP
L6
320nH
1
2
3
4
6
5
Q21
RJK0305DPB
4
5
3
2
1
8
7
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ISL8120EVAL3Z Schematic
Q25
2N7002LT1
1
2
DNP
C81
19
PHASE2 (O)
LGATE2
20
LGATE2 (O)
PVCC 21
C102
1500uF
PHASE1
23
9
COMP2 (I/O)
10
11
13
12
14
16
15
VIN (I)
FB2 (I/O)
CLKOUT/REFIN (I/O)
7
R123
10K
VCC
R124
DNP
C103
DNP
R128
DNP
VMON1
TP25
CLKOUT
EN/FF2 (I/O)
6
FSYNC (I/O)
5
ISHARE (O)
3
ISET (O)
2
2. Pin7 connected to VMON1 through a voltage divider R128 and R124
will set the controller in DDR mode(Vout1-VDDQ, Vout2-VTT).
R133
76.8k
R135
4.42k
JP12
C94
10nF
R136
13.7k
R141
4.42k
C93
C96
1nF
C98
680pF
FB1 (I/O)
R140
10k
R129(R136)=13.7k, R135(R141)=4.42k: UVLO_RISE=4V; UVLO_FALL= 3.38V
C97
1nF
VCC
R143
10k
R142
4.02k
R100
DNP
R132
DNP
C99
8.2nF
R99
DNP
32
VMON1 (I/O)
31
VSEN1- (I)
30
VSEN1+ (I)
29
ISEN1A (I)
ISEN1B (I)
28
27
VCC (I)
R129(R136)=33k, R135(R141)=5.1k: UVLO_RISE=7V; UVLO_FALL= 6V
R129(R136)=8.25k, R135(R141)=3.09k: UVLO_RISE=3.2V; UVLO_FALL= 2.94V
1
COMP1 (I/O)
BOOT1 (I/O)
R145
5.1
UGATE1 (O)
26
10uF_25V_X5R
UGATE1
24
C95
10uF_16V
PHASE1 (O)
VIN
R129
13.7k
C88
10nF
JP11
TP27
FSYNC
4ENABLE1
EN/FF1 (I/O)
LGATE1 (O)
1. Pin7 pulled to be in voltage range between 29%Vcc and Vcc will set
the controller to be in dual independant o/ps mode. And the phase shift
between the 2 phase can be programmed by the voltage on this pin.
ENABLE2
SYNC
ISL8120IRZ
PVCC (I/O)
PGND (PAD)
C92
22
25
C91
LGATE1
8
Enlarge the pad slightly
so that a probe tip can be
placed close to the IC
33
C90
C128
1500uF
PGOOD (O)
3
PHASE2
VMON2 (I/O)
UGATE2 (O)
VSEN2- (I)
18
ISEN2B (I)
UGATE2
VSEN2+ (I)
BOOT2 (I/O)
ISEN2A (I)
17
TP24
PGOOD3
TP26
VSEN_REM2+
1
VIN
BOOT2
VSEN_REM2+
R120
0
LED4
DNP
VMON1
R152
0
VMON1
R125
DNP
VCC
TP28
VSEN_REM1-
R154
100
C106
0.1uF
R158
6.49k
TP31
VSEN_REM1+
VOUT1
R161
0
TP29
TRAN1
1
Q27
DNP
TP30
External Step Signal_1
C108
2.2nF_DNP
1
C110
C111
6
5
1
DNP
DNP
C125
C114
DNP
TP23
TRAN2
TP22
External Step Signal_2
R122
DNP
DNP
J10
VOUT1
C126
C113
DNP
Q26
DNP
R151
VOUT1
R163
2.2_DNP
5
R159
100
1
2
3
4
L7
320nH
R160
0
1
2
3
4
8
7
VOUT2
VSEN_REM1+
C107
0.1uF
Q1A
DNP
2
34
VSEN_REM1-
JP8
2
C109
4.7uF_25V_X5R
Q32
DNP
Circuits DNP and No Use
R157
249
5
5
5
Q30
RJK0305DPB
4
5
3
2
Q31
1
RJK0305DPB
R149
RDSON1_DNP
R130
DNP
1
R155
0
C104
2.2u
Q29
RJK0301DPB
4
3
2
1
5
VCC
4
3
2
1
4
3
2
1
Q28
RJK0301DPB
C101
15nF
R147
1k
2
R146
45.3
BOOT1
C100
0.22u
GREEN
2
RED
TP32
VOUT1
C112
10uF
R156
DNP
R153
DNP
R126
DNP
R131
DNP
Q1B
6SEPC680M
6SEPC680M
1
J9
GND(VOUT1-)
3
4
Optional dual MOSFET(SO8) footprint for
low load current applications.
680uF, 7mOhm
AN1528.1
June 25, 2015
FIGURE 3. ISL8120EVAL3Z SCHEMATIC
[email protected]
OC=32.5A
Footprints for on-board transient load
Application Note 1528
C87
0.22u
C116
0.1uF
R119
100
U3
TP3
VIN
R116
100
C85
8.2nF
VIN1
C86
1.5uF_25V_X5R
R121
2
J2
VIN
C82
680pF
TP21
VIN1
TP1
GND
J1
GND
TP19
VSEN_REM2VSEN_REM2-
R118
45.3
15nF
R109
0
R111
4.02k
R115
1k
4
R107
RDSON2_DNP
Dual MOSFET(SO8) footprint for
low load current applications.
Application Note 1528
ISL8120EVAL3Z Bill of Materials
REFERENCE DESCRIPTION
PART NUMBER
QTY
C123-C126
DNP
0
C96, C97
GRM188R71H102KA
2
MURATA
CAP, SMD, 0603, 1000pF, 50V, 10%, X7R, ROHS
C88, C94
06032R103K8B20
2
PHILLIPS
CAP, SMD, 0603, 0.01µF, 25V, 10%, X7R, ROHS
C76, C106, C107, C116
GRM39X7R104K025AD
4
MURATA
CAP, SMD, 0603, 0.1µF, 25V, 10%, X7R, ROHS
C81, C101
ECJ-1VB1H153K
2
PANASONIC
CAP, SMD, 0603, 0.015µF, 50V, 10%, X7R, ROHS
C87, C100
C1608X7R1E224K
2
TDK
C82, C98
GMC10CG681J50NT
2
CAL-CHIP
CAP, SMD, 0603, 680pF, 50V, 5%, NPO, ROHS
C85, C99
ECJ-1VB1H822K
2
PANASONIC
CAP, SMD, 0603, 8200pF, 50V, 10%, X7R, ROHS
C74, C103, C108
DNP
0
C95
C0805X5R160-106KNE
1
VENKEL
CAP, SMD, 0805, 10µF, 16V, 10%, X5R, ROHS
C86
GRM21BF51E155ZA01L
1
MURATA
CAP, SMD, 0805, 1.5µF, 25V,+80-20,Y5V, ROHS
C104
ECJ-2FB1E225K
1
PANASONIC
CAP, SMD, 0805, 2.2µF, 25V, 10%, X5R, ROHS
C112, C115
C1206X5R250-106KNE
2
VENKEL
CAP, SMD, 1206, 10µF, 25V, 10%, X5R, ROHS
C75, C109
C1206C475K3PACTU
2
KEMET
CAP, SMD, 1206, 4.7µF, 25V, 10%, X5R, ROHS
C79, C80, C113, C114
DNP
0
C90, C91, C92, C93
ECJ-4YB1E106M
4
PANASONIC
C102, C128
25ZL1500M12.5X25
2
RUBYCON
C77, C78, C110, C111
2R5TPF470M7L
4
SANYO
CAP, POSCAP, SMD, 7.3X4.3, 470µF, 2.5V, 20%, 7mΩ,
ROHS
L6, L7
PA1513.321NLT
2
PULSE
COIL-PWR INDUCTOR, SMD, 13mm, 320nH, 20%,
45A, Pb-free
J2
111-0702-001
1
JOHNSON COMPONENTS
CONN-GEN, BIND.POST, INSUL-RED,
THMBNUT-GND
J1
111-0703-001
1
JOHNSON COMPONENTS
CONN-GEN,BIND.POST,INSUL-BLK,
THMBNUT-GND
TP20, TP32
131-4353-00
2
TEKTRONIX
CONN-SCOPE PROBE TEST PT, COMPACT, PCB MNT,
ROHS
TP1, TP3, TP19, TP21, TP22,
TP24, TP25, TP26, TP27,
TP28, TP30, TP31
5002
12
KEYSTONE
CONN-MINI TEST POINT, VERTICAL, WHITE, ROHS
JP7, JP8, JP11, JP12
69190-202
4
BERG/FCI
CONN-HEADER, 1x2, RETENTIVE, 2.54mm, ST, ROHS
LED4
DNP
0
LED3
SSL-LXA3025IGC-TR
1
LUMEX
U3
ISL8120IRZ
1
INTERSIL
Q25
2N7002-7-F
1
DIODES, INC.
Q1, Q2
DNP
0
DNP-PLACE HOLDER, TRANSIST-DUAL MOS, N-CHAN,
8P, SOIC, 30V, 6A, ROHS
Q26, Q27
DNP
0
DNP-PLACE HOLDER, TRANSIST-MOSFET, N-CHAN,
5P, LFPAK, 30V, 9.4mΩ, ROHS
Q32
DNP
0
DNP-PLACE HOLDER
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MANUFACTURER
DESCRIPTION
CAP, SMD, 0603, 0.22µF, 25V, 10%, X7R, ROHS
CAP, SMD, 0603, DNP-PLACE HOLDER, ROHS
CAP, SMD, 1206, DNP-PLACE HOLDER, ROHS
CAP, SMD, 1210, 10µF, 25V, 20%, X5R, ROHS
CAP, RADIAL, 12.5X25, 1500µF, 25V, 20%,
ALUM.ELEC., ROHS
LED, SMD, 3mmx2.5mm, 4P, RED/GREEN,
12/20MCD, 2V
IC-DUAL PHASE PWM CONTROLLER, 32P, QFN, 5X5,
ROHS
TRANSISTOR, N-CHANNEL, 3LD, SOT-23, 60V,
115mA, ROHS
AN1528.1
June 25, 2015
Application Note 1528
ISL8120EVAL3Z Bill of Materials (Continued)
REFERENCE DESCRIPTION
PART NUMBER
QTY
MANUFACTURER
Q23, Q24, Q28, Q29
RJK0301DPB
4
RENESAS TECHNOLOGY
TRANSISTOR, N-CHANNEL, 5P, LFPAK, 30V, 60A,
ROHS
Q21, Q22, Q30, Q31
RJK0305DPB
4
RENESAS TECHNOLOGY
TRANSISTOR, N-CHANNEL, 5P, LFPAK, 30V, 30A,
ROHS
R145
CRCW06035R10FNEA
1
VISHAY/DALE
RES, SMD, 0603, 5.1Ω, 1/10W, 1%, TF, ROHS
8
Various
RESISTOR, SMD, 0603, 0Ω, 1/10W, TF, ROHS
R96, R102, R109, R120,
R152, R155, R160, R161
DESCRIPTION
R116, R119, R154, R159
RK73H1JT1000F
4
KOA
RES, SMD, 0603, 100Ω, 1/10W, 1%, TF, ROHS
R97, R98, R115, R147
RK73H1JTTD1001F
4
KOA
RES, SMD, 0603, 1k, 1/10W, 1%, TF, ROHS
R123, R140, R143
RK73H1JT1002F
3
KOA
RES, SMD, 0603, 10k, 1/10W, 1%, TF, ROHS
R129, R136
RC0603FR-0713K7L
2
YAGEO
RESISTOR, SMD, 0603, 13.7k, 1/10W, 1%, TF, ROHS
R103, R157
CR0603-10W-2490FT
2
VENKEL
RES, SMD, 0603, 249Ω, 1/10W, 1%, TF, ROHS
R111, R142
ERJ-3EKF4021V
2
PANASONIC
R135, R141
RC0603FR-074K42L
2
YAGEO
RES, SMD, 0603, 4.42k, 1/10W, 1%, TF, ROHS
R118, R146
CR0603-10W-45R3FT
2
VENKEL
RES, SMD, 0603, 45.3Ω, 1/10W, 1%, TF, ROHS
R95, R158
ERJ-3EKF6491V
2
PANASONIC
RES, SMD, 0603, 6.49k, 1/10W, 1%, TF, ROHS
R133
CR0603-10W-7682FT
1
VENKEL
RES, SMD, 0603, 76.8k, 1/10W, 1%, TF, ROHS
R99, R100, R107, R122,
R124, R125, R128, R130 to
R132, R149, R151, R153.
DNP
0
RES, SMD, 0603, DNP-PLACE HOLDER, ROHS
R94, R163
DNP
0
RES, SMD, 0805, DNP-PLACE HOLDER, ROHS
R121
CR1206-4W-02R0
1
R126, R156
DNP
0
J7, J8, J9, J10
KPA8CTP
4
TP23, TP29
DNP
0
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6
VENKEL
RES, SMD, 0603, 4.02kΩ, 1/10W, 1%, TF, ROHS
RES, SMD, 1206, 2Ω, 1/4W, 1%, TF, ROHS
RES, SMD, 2512, PLACE HOLDER, TF, ROHS
BERG/FCI
HDWARE, MTG, CABLE TERMINAL, 6-14AWG,
LUG&SCREW, ROHS
DNP-PLACE HOLDER
AN1528.1
June 25, 2015
Application Note 1528
ISL8120EVAL3Z Board Layout
FIGURE 4. TOP SILKSCREEN
FIGURE 5. TOP LAYER
FIGURE 6. 2nd LAYER
FIGURE 7. 3rd LAYER
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7
AN1528.1
June 25, 2015
Application Note 1528
ISL8120EVAL3Z Board Layout (Continued)
FIGURE 8. BOTTOM LAYER
FIGURE 9. BOTTOM SILKSCREEN (MIRRORED)
FIGURE 10. BOTTOM SILKSCREEN
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8
AN1528.1
June 25, 2015
Application Note 1528
Test Data for ISL8120EVAL3Z
Efficiency
100
100
VOUT 1
80
80
70
70
60
50
40
30
60
50
40
30
20
20
10
10
0
0
2
4
6
8 10 12 14 16 18
OUTPUT CURRENT (A)
20
22
24
VOUT 2
90
EFFICIENCY (%)
EFFICIENCY (%)
90
0
26
0
2
4
6
8 10 12 14 16 18
OUTPUT CURRENT (A)
20
22
24
26
FIGURE 12. CHANNEL 2 EFFICIENCY(12V VIN AND 1.2V VOUT)
FIGURE 11. CHANNEL 1 EFFICIENCY (12V VIN AND 1.2V VOUT)
1.200
1.200
1.199
1.199
1.198
CURRENT LOAD AT 25A
1.197
1.196
1.195
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
VOLTAGE OUTPUT (V)
VOLTAGE OUTPUT (V)
Line Regulation
CURRENT LOAD AT 25A
1.198
1.197
1.196
1.195
7
8
9
10 11
FIGURE 13. CHANNEL 1 LINE REGULATION
Start-up
12 13 14 15 16 17 18 19 20 21 22 23
VOLTAGE INPUT (V)
VOLTAGE INPUT (V)
FIGURE 14. CHANNEL 1 LINE REGULATION
Load Transient
VOUT1
VOUT1
VOUT2
VOUT2
FIGURE 15. POWER-UP UNDER FULL LOAD (25A FOR EACH
CHANNEL)
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FIGURE 16. LOAD TRANSIENT (0A TO 25A STEP,
SLEW_RATE = 1.6A/µs)
AN1528.1
June 25, 2015
Application Note 1528
Test Data for ISL8120EVAL3Z (Continued)
Output Ripple
VOUT1
VOUT2
FIGURE 17. OUTPUT RIPPLES UNDER 25A LOAD FOR EACH CHANNEL
DDR Application Waveforms
VDDQ
VDDQ
PH_VDDQ
VTT
VTT
PH_VTT
FIGURE 18. VDDQ AND VTT START-UP TRACKING (DDR3)
FIGURE 19. PHASE AND VOUTs (DDR3)
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the document is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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AN1528.1
June 25, 2015
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