DATASHEET

Compact Synchronous Buck Regulator
ISL8023, ISL8024
Features
The ISL8023, ISL8024 are highly efficient, monolithic,
synchronous step-down DC/DC converters that can deliver 3A
(ISL8023) or 4A (ISL8024) of continuous output current from a
2.7V to 5.5V input supply. The devices use current mode control
architecture to deliver very low duty cycle operation at high
frequency with fast transient response and excellent loop stability.
• 2.7V to 5.5V input voltage range
• Very low on-resistance FET’s - P-Channel 45mΩ and
N-Channel 19mΩ typical values
• High efficiency synchronous buck regulator with up to 95%
efficiency
• 0.8% reference accuracy over-temperature/load/line
The ISL8023 and ISL8024 integrate a very low On-resistance
P-Channel (45mΩ) high side FET and N-Channel (19mΩ) low
side FET to maximize efficiency and minimize external
component count. The 100% duty-cycle operation allows less
than 200mV dropout voltage at 4A output current. The
operation frequency of the pulse-width modulator (PWM) is
adjustable from 500kHz to 4MHz. The default switching
frequency of 1MHz is set by connecting the FS pin high, which
allows for the use of small external components.
• Complete BOM with as few as 3 external parts
• Start-up with pre-biased output
• Internal soft-start - 1ms or adjustable
• Soft-stop output discharge during disabled
• Adjustable frequency from 500kHz to 4MHz - default at
1MHz (8023/24), 2MHz (8023A/24A)
• External synchronization up to 4MHz
The ISL8023, ISL8024 can be configured for discontinuous or
forced continuous operation at light load. Forced continuous
operation reduces noise and RF interference while
discontinuous mode provides higher efficiency by reducing
switching losses at light loads.
• Over-temperature, Overcurrent, Overvoltage and negative
overcurrent protection
• Tiny 3x3 QFN package
Applications
Fault protection is provided by internal hiccup mode current
limiting during short circuit and overcurrent conditions. Other
protection, such as overvoltage and over-temperature are also
integrated into the device. A power-good output voltage
monitor indicates when the output is in regulation.
• DC/DC POL modules
• μC/µP, FPGA and DSP power
• Plug-in DC/DC modules for routers and switchers
• Portable instruments
The ISL8023, ISL8024 offer a 1ms Power-Good (PG) timer at
power-up. When in shutdown, ISL8023, ISL8024 discharges
the output capacitor through an internal soft-stop switch. Other
features include internal fixed or adjustable soft-start and
internal/external compensation.
• Test and measurement systems
• Li-ion battery powered devices
Related Literature
• See AN1759, “3A/4A Low Quiescent Current High Efficiency
Synchronous Buck Regulator”
The ISL8023 and ISL8024 are offered in a space saving 16 Ld
3x3 Pb-free QFN package with an exposed pad for improved
thermal performance and 1mm maximum height. The
complete converter occupies less than 0.22 in2 area.
Various fixed output voltages are available upon request. See
the “Ordering Information” on page 4 for more details.
100
EFFICIENCY (%)
90
3.3VOUT PFM
80
70
3.3VOUT PWM
60
50
40
0.0 0.5
1.0
1.5 2.0 2.5
IOUT (A)
3.0
3.5
4.0
FIGURE 1. EFFICIENCY T = +25°C, VIN = 5V
March 24, 2014
FN7812.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011, 2012, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL8023, ISL8024
NOTE: Full solution in size board. The full schematic and Gerber files are available for down load from Intersil.com.
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FN7812.3
March 24, 2014
ISL8023, ISL8024
Pin Configuration
16
15
14
PHASE
PHASE
PHASE
VIN
ISL8023, ISL8024
(16 LD TQFN)
TOP VIEW
13
11
PGND
PG 3
10
SGND
SYNC 4
9
FB
5
6
7
8
COMP
VDD 2
SS
PGND
FS
12
EN
VIN 1
Pin Descriptions
PIN NUMBER
SYMBOL
1, 16
VIN
DESCRIPTION
2
VDD
3
PG
Power-good is an open-drain output. Use 10kΩ to 100kΩ pull-up resistor connecting between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms upon output reached within regulation.
4
SYNC
Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case
of SYNIN pin float.
5
EN
Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output
capacitor when driven to low. There is an internal 1MΩ pull-down resistor to prevent an undefined logic
state in case of EN pin float.
6
FS
This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz
and configured for internal compensation if FS is connected to VIN.
7
SS
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor from
SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
8, 9
COMP, FB
The feedback network of the regulator, VFB, is the negative input to the transconductance error
amplifier. COMP is the output of the amplifier if FS resistor is used. Otherwise COMP is disconnected
thru a MOSFET for internal compensation. Recommend connecting COMP to SGND in internal
compensation mode. The output voltage is set by an external resistor divider connected to VFB. With
a properly selected divider, the output voltage can be set to any voltage between the power rail
(reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a
typical application. Additional external network across COMP and SGND might be required to improve
the loop compensation of the amplifier operation.
In addition, the regulator power-good and undervoltage protection circuitry use VFB to monitor the
regulator output voltage.
10
SGND
Signal ground.
Input supply voltage. Connect two 22µF ceramic capacitors to power ground.
Input supply voltage for the logic. Connect VIN PIN.
11, 12
PGND
Power ground.
13, 14, 15
PHASE
Switching node connection. Connect to one terminal of the inductor.
Exposed Pad
-
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The exposed pad must be connected to the SGND pin for proper electrical performance. Place as
much vias as possible under the pad connecting to SGND plane for optimal thermal performance.
FN7812.3
March 24, 2014
ISL8023, ISL8024
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
OUTPUT VOLTAGE
(V)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL8023IRTAJZ
023A
Adjustable
-40 to +85
16 Ld 3x3 TQFN
L16.3x3D
ISL8024IRTAJZ
024A
Adjustable
-40 to +85
16 Ld 3x3 TQFN
L16.3x3D
ISL8023AIRTAJZ
23AA
Adjustable
-40 to +85
16 Ld 3x3 TQFN
L16.3x3D
ISL8024AIRTAJZ
24AA
Adjustable
-40 to +85
16 Ld 3x3 TQFN
L16.3x3D
ISL8023EVAL3Z
Evaluation Board
ISL8024EVAL3Z
Evaluation Board
ISL8023AEVAL3Z
Evaluation Board
ISL8024AEVAL3Z
Evaluation Board
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8023, ISL8024. For more information on MSL, please see tech brief
TB363.
Typical Application Diagram
INPUT
2.7V TO 5.5V
VIN
PHASE
VDD
C2
2 x 22µF
EN
C1
22µF
R1
100k
R2
200k
PGND
PG ISL8023, ISL8024
C3*
4.7pF
R3
100k
SGND
SYNC
OUTPUT
1.8V/4A
L
1µH
VFB
COMP
VIN
FS
SS
SGND
* C3 is optional. Recommend to
put a placeholder for it. Check
loop analysis first before use.
FIGURE 2. TYPICAL APPLICATION DIAGRAM
TABLE 1. COMPONENT SELECTION TABLE
VOUT
0.8V
1.2V
1.5V
1.8V
2.5V
3.3V
3.6
C1
22µF
22µF
22µF
22µF
22µF
22µF
22µF
C2
4X22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
C3
4.7pF
4.7pF
4.7pF
4.7pF
4.7pF
4.7pF
4.7pF
L1
0.47~1µH
0.47~1µH
0.47~1µH
0.68~1.5µH
0.68~1.5µH
1~2.2µH
1~2.2µH
R2
33k
100k
150k
200k
316k
450k
500k
R3
100k
100k
100k
100k
100k
100k
100k
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FN7812.3
March 24, 2014
ISL8023, ISL8024
COMP
SS
SHUTDOWN
SYNC
55pF
Soft
SOFT
START
SHUTDOWN
100kΩ
VDD
+
BANDGAP VREF
+
EN
FS
+
COMP
-
EAMP
-
VIN
OSCILLATOR
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
HS DRIVER
3pF
+
P
PHASE
LS
DRIVER
N
PGND
VFB
Slope
SLOPE
COMP
6k
0.6V
+
OV
0.85*VREF
PG
+
CSA
-
-
+
UV
+
OCP
-
+
SKIP
-
ISET
THRESHOLD
1ms
DELAY
NEG CURRENT
SENSING
SGND
ZERO-CROSS
SENSING
0.5V
SCP
+
100Ω
SHUTDOWN
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
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FN7812.3
March 24, 2014
ISL8023, ISL8024
Absolute Maximum Ratings (Reference to GND)
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V (DC) or 7V (20ms)
EN, FS, PG, SYNC, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3V (100ns)/(DC) to 6.5V (DC)
COMP, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
Thermal Resistance
θJA (°C/W) θJC (°C/W)
16 LD TQFN Package (Notes 4, 5) . . . . . . .
45
6.5
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 4A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise noted, all parameter limits are established over the recommended operating conditions and
the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are
at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
2.5
2.7
V
INPUT SUPPLY
VIN Undervoltage Lockout Threshold
VUVLO
Rising, no load
Falling, no load
Quiescent Supply Current
IVIN
Shutdown Supply Current
ISD
2.2
2.4
V
SYNC = GND, no load at the output
50
µA
SYNC = GND, no load at the output and no
switches switching
50
60
µA
SYNC = VIN, FS = 1MHz, no load at the output
8
15
mA
SYNC = GND, VIN = 5.5V, EN = low
5
7
µA
0.600
0.605
V
OUTPUT REGULATION
Reference Voltage - ISL8023IRZ, ISL8024IRZ
VREF
VFB Bias Current - ISL8023IRZ, ISL8024IRZ
IVFB
0.595
VFB = 0.75V
0.01
µA
Line Regulation
VIN = VO + 0.5V to 5.5V (minimal 2.7V)
0.2
%/V
Soft-Start Ramp Time Cycle
SS = SGND
1
ms
Soft-Start Charging Current
ISS
VSS = 0.1V
1.2
1.6
2.0
µA
OVERCURRENT PROTECTION
Current Limit Blanking Time
tOCON
17
Clock
pulses
Overcurrent and Auto Restart Period
tOCOFF
8
SS cycle
Positive Peak Current Limit
IPLIMIT
Peak Skip Limit
ISKIP
Zero Cross Threshold
5.2
6.5
7.8
A
3A application
3.9
4.8
5.9
A
4A application (test at 3.6V)
0.9
1.2
1.5
A
3A application (test at 3.6V)
0.65
0.9
1.15
A
200
mA
-1.8
A
-200
Negative Current Limit
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4A application
INLIMIT
6
-3.0
-2.4
FN7812.3
March 24, 2014
ISL8023, ISL8024
Electrical Specifications
Unless otherwise noted, all parameter limits are established over the recommended operating conditions and
the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are
at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
COMPENSATION
Error Amplifier Trans-Conductance
Trans-Resistance
FS = VIN
80
µA/V
FS with Resistor
150
µA/V
RT
0.15
0.2
0.25
Ω
VIN = 5V, IO = 200mA
35
45
55
mΩ
VIN = 2.7V, IO = 200mA
50
70
90
mΩ
VIN = 5V, IO = 200mA
12
19
25
mΩ
VIN = 2.7V, IO = 200mA
20
28
37
mΩ
PHASE
P-Channel MOSFET ON-Resistance
N-Channel MOSFET ON-Resistance
PHASE Maximum Duty Cycle
%
100
PHASE Minimum On-Time
SYNC = High
140
ns
1200
kHz
OSCILLATOR
Nominal Switching Frequency
Fsw
FS = VIN
800
1000
FS with RS = 402kΩ
490
kHz
FS with RS = 42.2kΩ
4200
kHz
SYNC Logic Low to High Transition Range
0.70
SYNC Hysteresis
0.75
0.80
0.15
3.6
V
5
µA
0.3
V
1
2
ms
PG Pin Leakage Current
0.01
0.1
µA
OVP PG Rising Threshold
0.80
SYNC Logic Input Leakage Current
VIN = 3.6V
V
PG
Output Low Voltage
Delay Time (Rising Edge)
0.5
UVP PG Rising Threshold
80
85
V
90
%
UVP PG Hysteresis
5
%
PGOOD Delay Time (Falling Edge)
15
µs
EN
Logic Input Low
0.4
Logic Input High
0.9
V
V
EN Logic Input Leakage Current
0.1
1
µA
Thermal Shutdown
150
°C
Thermal Shutdown Hysteresis
25
°C
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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FN7812.3
March 24, 2014
ISL8023, ISL8024
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN,
SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A.
100
100
90
1.2VOUT
80
1.5VOUT
1.8VOUT
EFFICIENCY (%)
EFFICIENCY (%)
90
2.5VOUT
70
60
50
0.5
1.0
1.5
2.0
IOUT (A)
2.5
3.0
3.5
1.8VOUT
2.5VOUT
70
60
40
0.0
4.0
FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3 VIN PWM)
0.5
1.0
1.5
2.0
IOUT (A)
2.5
3.0
3.5
4.0
FIGURE 5. EFFICIENCY vs LOAD (1MHz 3.3 VIN PFM)
100
100
90
90
1.2VOUT
80
1.5VOUT
1.8VOUT
2.5VOUT
EFFICIENCY (%)
EFFICIENCY (%)
1.5VOUT
50
40
0.0
3.3VOUT
70
60
50
80 1.2VOUT
1.5VOUT
1.8VOUT
2.5VOUT
3.3VOUT
70
60
50
40
0.0
0.5
1.0
1.5
2.0
IOUT (A)
2.5
3.0
3.5
40
0.0
4.0
FIGURE 6. EFFICIENCY vs LOAD (1MHz 5VIN PWM)
1.08
1.244
0.90
1.238
0.72
1.232
3.3VIN PWM MODE
0.54
5VIN PWM MODE
0.36
1.226
1.220
0.18
0
0.0
0.5
1.0
1.5
2.0
IOUT (A)
2.5
3.0
3.5
4.0
FIGURE 7. EFFICIENCY vs LOAD (1MHz 5VIN PFM)
vOUT (V)
POWER DISSIPATION (W)
1.2VOUT
80
3.3VIN PFM MODE
5VIN PFM MODE
1.214
0.5
1.0
1.5
2.0
IOUT (A)
2.5
3.0
3.5
4.0
FIGURE 8. POWER DISSIPATION vs LOAD (1MHz, VOUT = 1.8V)
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3.3VIN PWM MODE
1.208
0.0
0.5
1.0
1.5
2.0
IOUT (A)
5VIN PWM MODE
2.5
3.0
3.5
4.0
FIGURE 9. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V)
FN7812.3
March 24, 2014
ISL8023, ISL8024
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN,
SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued)
1.529
1.830
1.524
1.824
1.519
1.818
3.3VIN PFM MODE
3.3VIN PFM MODE
1.514
VOUT (V)
VOUT (V)
5VIN PFM MODE
5VIN PFM MODE
1.812
1.806
1.509
3.3VIN PWM MODE
3.3VIN PWM MODE
1.800
1.504
5VIN PWM MODE
1.499
0.0
0.5
1.0
1.5
2.0
IOUT (A)
2.5
3.0
3.5
1.794
0.0
4.0
1.0
1.5
2.0
IOUT (A)
2.5
3.0
3.5
4.0
3.354
2.540
2.532
3.345
3.3VIN PFM MODE
3.336
2.524
5VIN PFM MODE
VOUT (V)
VOUT (V)
0.5
FIGURE 11. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V)
FIGURE 10. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V)
2.516
2.508
5VIN PFM MODE
3.327
3.318
3.3VIN PWM MODE
3.309
2.500
5VIN PWM MODE
2.492
0.0
0.5
1.0
1.5
2.0
IOUT (A)
2.5
3.0
3.5
3.300
0.0
4.0
FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V)
1.836
1.810
1.828
0A LOAD
VOUT (V)
2A LOAD
1.790
1.785
2.0
3.0
3.5
4.0
VIN (V)
4.5
9
1.5
2.0
IOUT (A)
2.5
3.0
3.5
4.0
0A LOAD
1.812
2A LOAD
1.796
5.0
5.5
6.0
FIGURE 14. OUTPUT VOLTAGE REGULATION vs VIN (PWM VOUT = 1.8 )
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1.0
1.804
4A LOAD
2.5
0.5
1.820
1.800
1.795
5VIN PWM MODE
FIGURE 13. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V)
1.815
1.805
VOUT (V)
5VIN PWM MODE
1.788
2.0
4A LOAD
2.5
3.0
3.5
4.0
VIN (V)
4.5
5.0
5.5
6.0
FIGURE 15. OUTPUT VOLTAGE REGULATION vs VIN (PFM VOUT = 1.8V)
FN7812.3
March 24, 2014
ISL8023, ISL8024
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN,
SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued)
PHASE 2V/DIV
VOUT RIPPLE 20mV/DIV
PHASE 2V/DIV
VOUT RIPPLE 20mV/DIV
IL 1A/DIV
IL 1A/DIV
FIGURE 16. STEADY STATE OPERATION AT NO LOAD (PWM)
PHASE 2V/DIV
FIGURE 17. STEADY STATE OPERATION AT NO LOAD (PFM)
VOUT RIPPLE 50mV/DIV
IL 2A/DIV
IL 2A/DIV
VOUT RIPPLE 20mV/DIV
FIGURE 18. STEADY STATE OPERATION WITH FULL LOAD
VOUT RIPPLE 50mV/DIV
FIGURE 19. LOAD TRANSIENT (PWM)
EN 2V/DIV
VOUT 1V/DIV
IL 2A/DIV
IL 1A/DIV
PG 5V/DIV
FIGURE 20. LOAD TRANSIENT (PFM)
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10
FIGURE 21. SOFT-START WITH NO LOAD (PWM)
FN7812.3
March 24, 2014
ISL8023, ISL8024
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN,
SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued)
EN 2V/DIV
EN 2V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 1A/DIV
IL 1A/DIV
PG 2V/DIV
PG 5V/DIV
FIGURE 22. SOFT-START AT NO LOAD (PFM)
EN 2V/DIV
FIGURE 23. SOFT-START WITH PRE-BIASED 1V
EN 2V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 1A/DIV
IL 2A/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 24. SOFT-START AT FULL LOAD
PHASE 5V/DIV
VOUT RIPPLE 20mV/DIV
PHASE 5V/DIV
VOUT RIPPLE 20mV/DIV
IL 0.5A/DIV
IL 2A/DIV
SYNC 5V/DIV
SYNC 5V/DIV
FIGURE 26. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 2MHz
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FIGURE 25. SOFT-DISCHARGE SHUTDOWN
11
FIGURE 27. STEADY STATE OPERATION AT FULL LOAD WITH
FREQUENCY = 2MHz
FN7812.3
March 24, 2014
ISL8023, ISL8024
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN,
SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL 1A/DIV
IL 0.2A/DIV
SYNC 5V/DIV
FIGURE 28. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 4MHz
SYNC 5V/DIV
FIGURE 29. STEADY STATE OPERATION AT FULL LOAD (PWM) WITH
FREQUENCY = 4MHz
PHASE 5V/DIV
PHASE 5V/DIV
IL 2A/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 2A/DIV
SYNC 5V/DIV
SYNC 5V/DIV
FIGURE 30. OUTPUT SHORT CIRCUIT
FIGURE 31. OUTPUT SHORT CIRCUIT RECOVERY
Typical Operating Performance for A Part
Unless otherwise noted, operating conditions are:
TA = +25°C, VVIN = 5V, EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A.
PHASE 2V/DIV
VOUT RIPPLE 20mV/DIV
PHASE 2V/DIV
VOUT RIPPLE 20mV/DIV
IL 0.5A/DIV
IL 1A/DIV
FIGURE 32. STEADY STATE OPERATION AT NO LOAD (PWM)
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12
FIGURE 33. STEADY STATE OPERATION AT NO LOAD (PFM)
FN7812.3
March 24, 2014
ISL8023, ISL8024
Typical Operating Performance for A Part
Unless otherwise noted, operating conditions are:
TA = +25°C, VVIN = 5V, EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued)
EN 2V/DIV
PHASE 2V/DIV
VOUT 1V/DIV
IL 2A/DIV
IL 1A/DIV
VOUT RIPPLE 20mV/DIV
PG 5V/DIV
FIGURE 34. STEADY STATE OPERATION WITH FULL LOAD
FIGURE 35. SOFT-START WITH NO LOAD (PWM)
EN 2V/DIV
EN 2V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 1A/DIV
IL 1A/DIV
PG 5V/DIV
FIGURE 36. SOFT-START AT NO LOAD (PFM)
PG 5V/DIV
FIGURE 37. SOFT-START AT FULL LOAD
EN 2V/DIV
VOUT 1V/DIV
IL 1A/DIV
PG 5V/DIV
FIGURE 38. SOFT-DISCHARGE SHUTDOWN
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13
FN7812.3
March 24, 2014
ISL8023, ISL8024
Theory of Operation
The ISL8023, ISL8024 is a step-down switching regulator
optimized for battery-powered handheld applications. The
regulator operates at 1MHz fixed default switching frequency,
when FS is connected to VIN, under heavy load conditions to
allow smaller external inductors and capacitors to be used for
minimal printed-circuit board (PCB) area. By connecting a
resistor from FS to SGND, the operational frequency adjustable
range is 500kHz to 4MHz. At light load, the regulator reduces the
switching frequency, unless forced to the fixed frequency, to
minimize the switching loss and to maximize the battery life. The
quiescent current when the output is not loaded is typically only
50µA. The supply current is typically only 5µA when the regulator
is shutdown.
PWM Control Scheme
Pulling the SYNC pin HI (>0.8V) forces the converter into PWM
mode, regardless of output current. The ISL8023, ISL8024
employs the current-mode pulse-width modulation (PWM) control
scheme for fast transient response and pulse-by-pulse current
limiting. Figure 3 on page 5 shows the Functional Block Diagram.
The current loop consists of the oscillator, the PWM comparator,
current sensing circuit and the slope compensation for the
current loop stability. The slope compensation is 440mV/Ts,
which changes with frequency. The gain for the current sensing
circuit is typically 200mV/A. The control reference for the current
loops comes from the error amplifier's (EAMP) output.
The PWM operation is initialized by the clock from the oscillator.
The P-Channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA and the slope compensation
reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
P-FET and turn on the N-Channel MOSFET. The N-FET stays on
until the end of the PWM cycle. Figure 39 shows the typical
operating waveforms during the PWM operation. The dotted lines
illustrate the sum of the slope compensation ramp and the
current-sense amplifier’s CSA output.
The output voltage is regulated by controlling the VEAMP voltage
to the current loop. The bandgap circuit outputs a 0.6V reference
voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during the
start-up and will be discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage error signal
to a current output. The voltage loop is internally compensated
with the 55pF and 100kΩ RC network. The maximum EAMP
voltage output is precisely clamped to 1.6V.
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14
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
FIGURE 39. PWM OPERATION WAVEFORMS
SKIP Mode
Pulling the SYNC pin LO (<0.4V) forces the converter into PFM
mode. The ISL8023, ISL8024 enters a pulse-skipping mode at
light load to minimize the switching loss by reducing the
switching frequency. Figure 40 illustrates the skip-mode
operation. A zero-cross sensing circuit shown in Figure 3 on
page 5 monitors the N-FET current for zero crossing. When 8
consecutive cycles of the inductor current crossing zero are
detected, the regulator enters the skip mode. During the eight
detecting cycles, the current in the inductor is allowed to become
negative. The counter is reset to zero when the current in any
cycle does not cross zero.
Once the skip mode is entered, the pulse modulation starts being
controlled by the SKIP comparator shown in Figure 3 on page 5.
Each pulse cycle is still synchronized by the PWM clock. The
P-FET is turned on at the clock's rising edge and turned off when
the output is higher than 1.5% of the nominal regulation or when
its current reaches the peak Skip current limit value. Then the
inductor current is discharging to 0A and stays at zero. The
internal clock is disabled. The output voltage reduces gradually
due to the load current discharging the output capacitor. When
the output voltage drops to the nominal voltage, the P-FET will be
turned on again at the rising edge of the internal clock as it
repeats the previous operations.
The regulator resumes normal PWM mode operation when the
output voltage drops 1.5% below the nominal voltage.
FN7812.3
March 24, 2014
ISL8023, ISL8024
PWM
PFM
PWM
CLOCK
8 CYCLES
PFM CURRENT LIMIT
IL
LOAD CURRENT
0
NOMINAL +1.5%
VOUT
NOMINAL -1.5%
NOMINAL
FIGURE 40. SKIP MODE OPERATION WAVEFORMS
Frequency Adjust
Negative Current Protection
The frequency of operation is fixed at 1MHz and internal
compensation when FS is tied to VIN. Adjustable frequency range
from 500kHz to 4MHz via simple resistor connecting FS to SGND
according to Equation 1:
Similar to the overcurrent, the negative current protection is
realized by monitoring the current across the low-side N-FET, as
shown in Figure 3 on page 5. When the valley point of the inductor
current reaches -3A for 4 consecutive cycles, both P-FET and N-FET
are off. The 100Ω in parallel to the N-FET will activate discharging
the output into regulation. The control will begin to switch when
output is within regulation. The regulator will be in PFM for 20µs
before switching to PWM if necessary.
220 ⋅ 10 3
R T [ kΩ ] = ------------------------------ – 14
f OSC [ kHz ]
(EQ. 1)
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA
output with the OCP comparator, as shown in Figure 3. The current
sensing circuit has a gain of 200mV/A, from the P-FET current to
the CSA output. When the CSA output reaches the threshold, the
OCP comparator is trippled to turn off the P-FET immediately. The
overcurrent function protects the switching converter from a
shorted output by monitoring the current flowing through the
upper MOSFET.
Upon detection of an overcurrent condition, the upper MOSFET
will be immediately turned off and will not be turned on again
until the next switching cycle. Upon detection of the initial
overcurrent condition, the overcurrent fault counter is set to 1. If,
on the subsequent cycle, another overcurrent condition is
detected, the OC fault counter will be incremented. If there are
17 sequential OC fault detections, the regulator will be shutdown
under an overcurrent fault condition. An overcurrent fault
condition will result in the regulator attempting to restart in a
hiccup mode within the delay of eight soft-start periods. At the
end of the eight soft-start wait period, the fault counters are reset
and soft-start is attempted again. If the overcurrent condition
goes away during the delay of eight soft-start periods, the output
will resume back into regulation point after hiccup mode expires.
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15
PG
PG is an open-drain output of a window comparator that
continuously monitors the buck regulator output voltage. PG is
actively held low when EN is low and during the buck regulator
soft-start period. After 1ms delay of the soft-start period, PG
becomes high impedance as long as the output voltage is within
nominal regulation voltage set by VFB. When VFB drops 15% below
or raises 0.8V above the nominal regulation voltage, the ISL8023,
ISL8024 pulls PG low. Any fault condition forces PG low until the
fault condition is cleared by attempts to soft-start. For logic level
output voltages, connect an external pull-up resistor, R1, between
PG and VIN. A 100kΩ resistor works well in most applications.
UVLO
When the input voltage is below the undervoltage lock-out (UVLO)
threshold, the regulator is disabled.
FN7812.3
March 24, 2014
ISL8023, ISL8024
Soft Start-Up
Applications Information
The soft start-up reduces the in-rush current during the start-up.
The soft-start block outputs a ramp reference to the input of the
error amplifier. This voltage ramp limits the inductor current as
well as the output voltage speed so that the output voltage rises
in a controlled fashion. When VFB is less than 0.1V at the
beginning of the soft-start, the switching frequency is reduced to
200kHz so that the output can start-up smoothly at light load
condition. During soft-start, the IC operates in the SKIP mode to
support pre-biased output condition.
Output Inductor and Capacitor Selection
Tie SS to SGND for internal soft-start approximately 1ms.
Connect a capacitor from SS to SGND to adjust the soft-start
time. This capacitor, along with an internal 1.6µA current source,
sets the soft-start interval of the converter, TSS as shown by
Equation 2.
C SS [ μF ] = 3.33 ⋅ T SS [ s ]
(EQ. 2)
Css must be less than 33nF to insure proper soft-start reset after
fault condition.
Enable
The enable (EN) input allows the user to control the turning on or
off the regulator for purposes such as power-up sequencing.
When the regulator is enabled, there is typically a 600µs delay
for waking up the bandgap reference and then the soft-start-up
begins.
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs or the VIN UVLO is
set, the outputs discharge to GND through an internal 100Ω
switch.
Power MOSFETs
The power MOSFETs are optimized for best efficiency. The
ON-resistance for the P-FET is typically 45mΩ and the
ON-resistance for the N-FET is typically 19mΩ.
100% Duty Cycle
The ISL8023, ISL8024 features 100% duty cycle operation to
maximize the battery life. When the battery voltage drops to a
level that the ISL8023, ISL8024 can no longer maintain the
regulation at the output, the regulator completely turns on the
P-FET. The maximum dropout voltage under the 100% duty-cycle
operation is the product of the load current and the
ON-resistance of the P-FET.
Thermal Shut-Down
The ISL8023, ISL8024 has built-in thermal protection. When the
internal temperature reaches +150°C, the regulator is completely
shutdown. As the temperature drops to +125°C, the ISL8023,
ISL8024 resumes operation by stepping through the soft-start.
To consider steady state and transient operations, ISL8023,
ISL8024 typically uses a 1.0µH output inductor. The higher or
lower inductor value can be used to optimize the total converter
system performance. For example, for higher output voltage 3.3V
application, in order to decrease the inductor current ripple and
output voltage ripple, the output inductor value can be increased.
It is recommended to set the ripple inductor current
approximately 30% of the maximum output current for optimized
performance. The inductor ripple current can be expressed as
shown in Equation 3:
VO ⎞
⎛
V O • ⎜ 1 – ---------⎟
V
⎝
IN⎠
ΔI = --------------------------------------L • fS
(EQ. 3)
The inductor’s saturation current rating needs to be at least
larger than the peak current. The ISL8023, ISL8024 protects the
typical peak current 4.8A/6.5A. The saturation current needs be
over 7A for maximum output current application.
ISL8023, ISL8024 uses internal compensation network and the
output capacitor value is dependent on the output voltage. The
ceramic capacitor is recommended to be X5R or X7R. The
recommended X5R or X7R minimum output capacitor values are
shown in Table 1.
In Table 1, the minimum output capacitor value is given for the
different output voltage to make sure that the whole converter
system is stable. Additional output capacitance should be added
for better performances in applications where high load transient
or low output ripple is required. It is recommended to check the
system level performance along with the simulation model.
Output Voltage Selection
The output voltage of the regulator can be programmed via an
external resistor divider that is used to scale the output voltage
relative to the internal reference voltage and feed it back to the
inverting input of the error amplifier. Refer to Figure 2.
The output voltage programming resistor, R2, will depend on the
value chosen for the feedback resistor and the desired output
voltage of the regulator. The value for the feedback resistor is
typically between 10kΩ and 100kΩ, as shown in Equation 4.
VO
R 2 = R 3 ⎛ ------------ – 1⎞
⎝ VFB
⎠
(EQ. 4)
If the output voltage desired is 0.6V, then R3 is left unpopulated
and R2 is shorted. There is a leakage current from VIN to PHASE.
It is recommended to preload the output with 10µA minimum.
For better performance, add 15pF in parallel with R2 (100kΩ).
Check loop analysis before use in application.
Input Capacitor Selection
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current flowing back to the
battery rail. At least two 22µF X5R or X7R ceramic capacitors are
a good starting point for the input capacitor selection.
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16
FN7812.3
March 24, 2014
ISL8023, ISL8024
Loop Compensation Design
Power Stage Transfer Functions
When there is an external resistor connected from FS to SGND,
the COMP pin is active for external loop compensation. The
ISL8023, ISL8024 uses constant frequency peak current mode
control architecture to achieve fast loop transient response. An
accurate current sensing pilot device in parallel with the upper
MOSFET is used for peak current control signal and overcurrent
protection. The inductor is not considered as a state variable
since its peak current is constant, and the system becomes
single order system. It is much easier to design a type II
compensator to stabilize the loop than to implement voltage
mode control. Peak current mode control has inherent input
voltage feed-forward function to achieve good line regulation.
Figure 41 shows the small signal model of the synchronous buck
regulator.
Transfer function F1(S) from control to output voltage is:
+
^
i in
^
Vin
ILd^
1:D
^
iL
LP
RLP
(EQ. 8)
C
1
1
Where ω esr = --------------- ,Q p ≈ R o ------o- ,ω o = ------------------Rc Co
LP
LP Co
Transfer function F2(S) from control to inductor current is given
by Equation 9:
S
1 + -----ˆI
V in
ωz
o
F 2 ( S ) = ---= ------------------------- --------------------------------------R o + R LP 2
dˆ
S
S
------- + --------------- + 1
2 ω Q
o
p
ωo
(EQ. 9)
1
where ω z = --------------- .
Vin d^
Ro Co
+
RT
GAIN (VLOOP (S(fi))
^
vo
S
1 + -----------ω esr
v̂ o
- = V in --------------------------------------F 1 ( S ) = ----2
dˆ
S
S
------- + --------------- + 1
2 ω Q
o p
ωo
Current loop gain Ti(S) is expressed as Equation 10:
Rc
T i ( S ) = R t F m F 2 ( S )H e ( S )
Ro
Co
(EQ. 10)
The voltage loop gain with open current loop is Equation 11:
Ti(S)
d^
K
T v ( S ) = KF m F 1 ( S )A v ( S )
(EQ. 11)
Fm
+
The Voltage loop gain with current loop closed is given by
Equation 12:
Tv (S)
He(S)
v^comp
Tv ( S )
L v ( S ) = -----------------------1 + Ti ( S )
-Av(S)
V FB
K = ----------- , V
FIGURE 41. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
FB is the feedback voltage of the voltage
Where
Vo
error amplifier. If Ti(S)>>1, then Equation 12 can be simplified as
Equation 13:
PWM Comparator Gain Fm:
The PWM comparator gain Fm for peak current mode control is
given by Equation 5:
1
dˆ
F m = ----------------- = -------------------------------( S e + S n )T s
v̂ comp
(EQ. 5)
Where Se is the slew rate of the slope compensation and Sn is
given by Equation 6:
(EQ. 6)
V in – V o
S n = R t --------------------L
(EQ. 12)
S
1 + -----------V FB R o + R LP
ω esr A v ( S )
1
L v ( S ) = ----------- ------------------------- ---------------------- ---------------- , ω p ≈ --------------Rt
Vo
Ro Co
S He ( S )
1 + ------ωp
(EQ. 13)
Equation 13 shows that the system is a single order system,
which has a single pole located at ω p before the half switching
frequency. Therefore, a simple type II compensator can be easily
used to stabilize the system.
P
where Rt is trans-resistance, which is the gain of the current
amplifier.
CURRENT SAMPLING TRANSFER FUNCTION He(S):
In current loop, the current signal is sampled every switching
cycle. It has the following transfer function in Equation 7:
2
(EQ. 7)
S
S
H e ( S ) = ------- + --------------- + 1
2 ω Q
n n
ωn
2
π
where Qn and ωn are given by Q n = – ---, ω n = πf s
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17
FN7812.3
March 24, 2014
ISL8023, ISL8024
Example: VIN = 5V, Vo = 1.8V, Io = 4A, fs = 1MHz,
Co = 2X22µF/3mΩ, L = 1µH, GM = 150µs, Rt = 0.20V/A,
VFB = 0.6V, Se = 440mV/µs, Sn = 6.4×105V/s, fc = 100kHz, then
compensator resistance R6 = 100kΩ.
Vo
C3
R2
V FB
R3
GM
V REF
Put the compensator zero at 8kHz, and put the compensator pole
at either half of switching frequency or ESR zero. We choose
500kHz here, then the compensator capacitors are:
V COMP
+
C6 = 220pF, C7 = 3pF (There is approximately 3pF parasitic
capacitance from VCOMP to GND; Therefore, C7 optional).
R6
C7
Figure 43 shows the simulated voltage loop gain. It is shown that
it has 90kHz loop bandwidth with 70° phase margin and 10dB
gain margin.
C6
60
Figure 42 shows the type II compensator and its transfer function
is expressed as Equation 14:
45
S ⎞⎛
S
⎛ 1 + ------------ 1 + -------------⎞
⎝
ω cz1⎠ ⎝
ω cz2⎠
v̂ comp
GM
A v ( S ) = ----------------- = --------------------- --------------------------------------------------------C6 + C7
S
v̂ FB
S ⎛ 1 + ----------⎞
⎝
ω cp⎠
(EQ. 14)
where,
GAIN (VLOOP (S(fi))
FIGURE 42. TYPE II COMPENSATOR
30
15
0
-15
C6 + C7
1
1
ω cz1 = --------------- , ω cz2 = ---------------, ω cp = ----------------------R6 C6 C7
R6 C6
R2 C3
-30
100
1k
Compensator design goal:
10k
100k
1M
f (fi)
High DC gain
⎛1
1⎞
180
Gain margin: >10dB
150
Phase margin: 40°
The compensator design procedure is as follows:
1
Put compensator zero ω cz1 = ( 1to3 ) -------------R C
o o
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower. An
optional zero can boost the phase margin. ωCZ2 is a zero due to
R2 and C3.
1
Put compensator zero ω cz2 = ( 5to8 ) -------------R2 C3
120
90
60
30
0
100
1k
10k
100k
1M
f (fi)
The loop gain Tv(S) at crossover frequency of fc has unity gain.
Therefore, the compensator resistance R6 is determined by
Equation 15.
2πf c V o C o R t
R 6 = ---------------------------------GM ⋅ V FB
PHASE (VLOOP (S(fi))
- f
Loop bandwidth fc: ⎝ --4- to ----10⎠ s
FIGURE 43. SIMULATED LOOP GAIN
(EQ. 15)
where GM is the sum of the trans-conductance, gm, of the
voltage error amplifier in each phase. Compensator capacitor C6
is then given by Equation 16.
1
1
C 6 = --------------------- , C 7 = ------------------------R 6 ω cz1
2πR 6 f esr
Submit Document Feedback
(EQ. 16)
18
FN7812.3
March 24, 2014
ISL8023, ISL8024
PCB Layout Recommendation
The PCB layout is a very important converter design step to make
sure the designed converter works well. For ISL8023, ISL8024,
the power loop is composed of the output inductor L’s, the output
capacitor COUT, the PHASE’s pins, and the PGND pin. It is
necessary to make the power loop as small as possible and the
connecting traces among them should be direct, short and wide.
The switching node of the converter, the PHASE pins, and the
traces connected to the node are very noisy, so keep the voltage
feedback trace away from these noisy traces. The input capacitor
should be placed as close as possible to the VIN pin. The ground
of input and output capacitors should be connected as closely as
possible. The heat of the IC is mainly dissipated through the
thermal pad. Maximizing the copper area connected to the
thermal pad is preferable. In addition, a solid ground plane is
helpful for better EMI performance. It is recommended to add at
least 5 vias ground connection within the pad for the best
thermal relief.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
March 24, 2014
FN7812.3
Electrical spec table: “OUTPUT REGULATION” on page 6, under VFB Bias Current section, changed the typical
value from 0.1µA to 0.01µA.
Added ISL8023EVAL3Z, ISL8024EVAL3Z and ISL8023AEVAL3Z, ISL8024AEVAL3Z Evaluation Boards to
Ordering Information table on page 4.
May 7, 2012
FN7812.2
Page 2: Updated with new silkscreen to show the correct placement of U1-Pin1.
Page 3: Pin Descriptions , COMP, FB Changed the description from "Must connect COMP to SGND in internal
compensation mode " to "Recommend connect COMP to SGND in internal compensation mode".
Updated Figure 2 to show the COMP pin tied to GND
Page 18: Put compensator zero ωcz2 = (5to8) R0C0" changed to "..... R2C3"
Figure 43, Simulated Loop Gain: Added Y-axis title to the top graph: GAIN (VLOOP(S(fi)))
February 15, 2012
FN7812.1
In the “Absolute Maximum Ratings” on page 6, changed “VIN” from “-0.3V” to “-0.3V to 6.5V (DC) or 7V (20ms)"
February 1, 2012
December 22, 2011
CHANGE
Revised description, Features and Applications on page 1. Added Figure 2.
FN7812.0
Initial Release.
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19
FN7812.3
March 24, 2014
ISL8023, ISL8024
Package Outline Drawing
L16.3x3D
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 3/10
4X 1.50
3.00
A
12X 0.50
B
13
6
PIN 1
INDEX AREA
16
6
PIN #1
INDEX AREA
12
3.00
1
1.60 SQ
4
9
(4X)
0.15
0.10 M C A B
5
8
16X 0.40±0.10
TOP VIEW
4 16X 0.23 ±0.05
BOTTOM VIEW
SEE DETAIL “X”
0.10 C
0.75 ±0.05
C
0.08 C
SIDE VIEW
(12X 0.50)
(2.80 TYP) (
1.60)
(16X 0.23)
C
0 . 2 REF
5
0 . 02 NOM.
0 . 05 MAX.
(16X 0.60)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.25mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
JEDEC reference drawing: MO-220 WEED.
either a mold or mark feature.
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20
FN7812.3
March 24, 2014
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