an1934

Application Note 1934
ISL85415EVAL2Z Wide VIN Negative VOUT Sync
Buck-Boost Regulator up to 500mA
Description
Key Features
The ISL85415EVAL2Z kit is intended for use for point-of-load
applications sourcing from 3V to 36V. The kit is used to
demonstrate the performance of the ISL85415 wide VIN low
quiescent current high efficiency sync buck regulator in
negative output configuration with up to 500mA output
current.
• Wide input voltage range 3V to 36V
The ISL85415 is offered in a 4mmx3mm 12 Ld DFN package
with 1mm maximum height. The converter occupies
2.418cm2 area.
• Continuous output current up to 500mA (refer to Figure 7)
• Internal or external soft-start
Specifications
• Power-good and enable functions available
This board has been configured and optimized for the following
operating conditions:
• VIN = 3V to 31V
• Synchronous operation for high efficiency
• Integrated high-side and low-side NMOS devices
• Programmable switching frequency (fixed or externally
synchronized)
• Minimal external components required
• On-board jumper for selecting PFM or forced PWM at light
loads
• On-board EN switch
• VOUT = -5V
Recommended Equipment
• IMAX = 700mA (at VIN = 31V)
The following materials are recommended to perform testing:
• Peak efficiency: >85.6% at 250mA, VIN = 12V
• Board temperature: +25°C
• 0V to 50V power supply with at least 2A source current
capability
References
• Electronic loads capable of sinking current up to 1.5A
• Digital Multimeters (DMMs)
ISL85415 Datasheet
• 100MHz quad-trace oscilloscope
Ordering Information
PART NUMBER
ISL85415EVAL2Z
May 13, 2014
AN1934.0
1
DESCRIPTION
Wide VIN (3V-31V) Negative VOUT Sync
Buck-Boost Integrated FET Regulator up
to 500mA
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright Intersil Americas LLC 2014. All Rights Reserved.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Application Note 1934
TABLE 1. EXTERNAL COMPONENT SELECTION
VOUT
(V)
L1
(µH)
C5+C6
(µF)
R1
(k)
R2
(k)
C4
(pF)
RFS
(k)
R3
(k)
C7
(pF)
-12
45
10
90.9
4.75
22
115
51.1
470
-5
22
2x22
90.9
12.4
100
120
51.1
470
-3.3
22
2x22
90.9
20
100
120
51.1
470
PCB Layout Guidelines
Evaluating the Other Output Voltages
The ISL85415EVAL2Z PCB layout has been optimized for
electrical and thermal performance. Proper layout of the power
converter will minimize EMI and noise while insuring first pass
success of the design.
The ISL85415VAL1Z kit output is preset to -5V, however the
output can be adjusted from -3.3V to -12V. The output voltage
programming resistor, R2, will depend on the desired output
voltage of the regulator and the value of the feedback resistor
R1, as shown in Equation 1.
PCB layouts are provided in multiple formats on the Intersil web
site. In addition, Figures 3 to 6 will clarify the important points in
PCB layout. In reality, PCB layout of the ISL85415EVAL2Z is quite
simple.
A multi-layer printed circuit board with GND plane is
recommended. Figure 3 shows the connections of the critical
components in the converter. The most critical connections are to
tie the PGND pin to the package GND pad and then use vias to
directly connect the GND pad to the system GND plane. This
connection of the GND pad to system plane insures a low
impedance path for all return current, as well as an excellent
thermal path to dissipate heat.
With this connection made, place the high frequency MLCC input
capacitors C1, C2 near the VIN pin and use vias directly at the
capacitor pads to tie the capacitors to the system GND plane.
Also use vias directly at the C5, C6 output capacitor pads to tie
the capacitors to the system GND plane. These measures will
minimize the high dV/dt and dI/dt loops.
Minimize the PHASE connection by placing L1 close to the IC and on
the same side. Place the BOOT capacitor (C3) very close to the IC.
Place a 1µF MLCC near the VCC pin and directly connect its
return with a via to the system GND plane.
Keep the power components path (L1, C1, C2, C3, C5, C6)
separated from the small signal nodes (FB, COMP) and the
control components path (FS, SS) by placing the feedback divider
close to the FB pin and do not route any feedback components
near PHASE or BOOT. If external components are used for SS,
COMP or FS, the same advice applies. Connect these control
components and small signal noise components to system GND.
Keep the small signal nodes traces (FB, COMP) as short as
possible.
Quick Setup Guide
1. Ensure that the circuit is correctly connected to the supply and
loads prior to applying any power.
2. Connect the bias supply to VIN, the plus terminal to VIN (P4)
and the negative return to GND (P5).
0.6
R 2 = R 1  ---------------------------
V
– 0.6
(EQ. 1)
OUT
Table 1 shows the component selection that should be used for
the respective VOUTs of -3.3V, -5V and -12V.
The curves in Figure 7 indicate the maximum output current the
converter can deliver as a function of the input voltage and the
selected output voltage configuration.
Figures 8, 9 and 10 show the efficiency for different input
voltage, output voltage and load combinations. Figures 11, 12
and 13 show the output regulation with load while Figures 14, 15
and 16 show the output regulation with input voltage, for
different output voltages. Figures 17 to 21 show some
performance curves of the board during start-up, shutdown,
steady state, and load transient.
Frequency Control
The ISL85415 has an FS pin that controls the frequency of
operation. Programmable frequency allows for optimization
between efficiency and external component size. It also allows
low frequency operation for low VOUTs when minimum on time
would limit the operation otherwise. Default switching frequency
is 500kHz when FS is tied to VCC (R10 = 0). By removing R10, the
switching frequency could be changed from 300kHz (R12 =
340k) to 2MHz (R12 = 32.4k). Please refer to the ISL85415
datasheet for calculating the value of R10. Do not leave this pin
floating.
Disabling/Enabling Function
The ISL85415EVAL2Z evaluation board contains a SW1 switch
that enables or disables the part, thus allowing low quiescent
current state. Table 2 details this function.
TABLE 2. SWITCH SETTINGS
SW1
ON/OFF CONTROL
ON
Enable VOUT
OFF
Disable VOUT
3. Verify that the position is ON for SW1.
4. Turn on the power supply.
5. Verify the output voltage is -5V for -VNEG (P7).
Submit Document Feedback
2
AN1934.0
May 13, 2014
Application Note 1934
SYNC Control
The ISL85415EVAL2Z evaluation board has a SYNC pin that
allows external synchronization frequency to be applied. Default
board configuration has R6 = 200k to VCC, which defaults to
PWM operation mode and also to the pre-selected switching
frequency set by R12 (see datasheet and previous section
“Frequency Control” on page 2 for details). If this pin is tied to
GND the IC will operate in PFM mode. JP1 switch allows to force
the PFM or PWM modes.
Soft-Start /COMP Control
R15 selects between internal (R15 = 0) and external soft-start.
R11 selects between internal (R11 = 0) and external
compensation. Please refer to the Pin Description Table (Page 3)
of the ISL85415 datasheet.
FIGURE 1. FRONT OF EVALUATION BOARD ISL85415EVAL2Z
FIGURE 2. BACK OF EVALUATION BOARD ISL85415EVAL2Z
Submit Document Feedback
3
AN1934.0
May 13, 2014
Submit Document Feedback
ISL85415EVAL2Z Schematic
9&&
9&&
3
3
6<1&
66
4
91(*
PWM
5
ISL85415FRZ
7.66
)6
5 91(*
5)6
N
)VZ N+]
5
&66 '13
&
6<1&
-3
6<1&
&203
&
X)
&
X)
&
X)
91(*
P9
9&&
/
& X+
X)
9
9
91(*
5
N
X)
3+$6(
3*
3*1'
'HYLFHPXVWEH
FRQQHFWHGWR*1'
SODQHZLWK9,$V
(1
91(*
91(*
5
NOTE: The input electrolytic capacitor C10 is optional and it is used to prevent transient voltages when the input
test leads have large parasitic inductance. It can be removed if the IC is used in a system application.
9ULVLQJ9IDOOLQJW\S
N
-5V
91(*
3
3*
2SHQ'UDLQDGG38//83
3*
5
23(1
91(*
5
N
&
9,1
3
91(*
91(*
-
91(*
5
&
9 N S)
(1
237,21$/
3
3*1'
9,1
*1'
&
X)
&
X)
3
9&&
91(*
-
23(1
9&&
9,1
3
3*1'
)%
3
9,1
%227
23(1
2))
21
6:
*706&%( 5
.
5
& S)
3
(1
Application Note 1934
91(*
PFM
3
3*1'
U1
5
66
'13
AN1934.0
May 13, 2014
Application Note 1934
ISL85415EVAL2ZA Bill of Materials
PART NUMBER
QTY
REF-DES
DESCRIPTION
MANUFACTURER
ISL85415EVAL2ZREVAPCB
1
N/A
PCB - ISL85415 NEGATIVE VOUT EVALUATION BOARD
INTERSIL
EEV-HA1H330UP/PCE3303CT-ND
1
C10
Capacitor Elect 33µF 50V CASE SMD
PANASONIC/DIGIKEY
H1045-00101-50V5-T
1
C4
CAP, SMD, 0603, 100pF, 50V, 5%, C0G, ROHS
PANASONIC
H1045-00104-50V10-T
1
C3
CAP, SMD, 0603, 0.1µF, 50V, 10%, X7R, ROHS
AVX
H1045-00105-16V10-T
1
C9
CAP, SMD, 0603, 1µF, 16V, 10%, X5R, ROHS
MURATA
H1045-00471-50V5-T
1
C7
CAP, SMD, 0603, 470pF, 50V, 5%, NP0, ROHS
PANASONIC
H1065-00106-50V10-T
2
C1, C2
CAP, SMD, 1206, 10µF, 50V, 10%, X5R, ROHS
TDK
H1065-00226-6R3V20-T
2
C5, C6
CAP, SMD, 1206, 22µF, 6.3V, 20%, X5R, ROHS
PANASONIC
131-4353-00
2
J1, J2
CONN-SCOPE PROBE TEST PT, COMPACT, PCB MNT
TEKTRONIX
68000-236LF
1
JP1
CONN HEADER 3POS VERT, 100 GOLD
TYCO ELECTRONICS
1514-2
5
P4, P5, P3,
P7, P9
CONN-TURRET, TERMINAL POST, TH
KEYSTONE
5002
5
P1, P2, P6,
P8, P10
CONN-MINI TEST POINT,VERTICAL,WHITE
KEYSTONE
H2511-00200-1/10W1-T
1
R4
RES, SMD, 0603, 20Ω, 1/10W, 1%, TF, ROHS
PANASONIC
H2511-00R00-1/10W-T
1
R15
RES, SMD, 0603, 0Ω, 1/10W, TF, ROHS
VENKEL
CR0603-10W-5112FT
1
R3
RES, SMD, 0603, 51.1k, 1/10W, 1%, TF, ROHS
VENKEL
RC0603FR-0712K4L
1
R2
RES, SMD, 0603, 12.4k, 1/10W, 1%, TF, ROHS
YAGEO
H2511-09092-1/10W1-T
1
R1
RES, SMD, 0603, 90.9k, 1/10W, 1%, TF, ROHS
PANASONIC
H2511-01203-1/10W1-T
1
R12
RES, SMD, 0603, 120k, 1/10W, 1%, TF, ROHS
VISHAY/DALE
ITT INDUSTRIES/C and K DIVISION
GT11MSCBE
1
SW1
SWITCH-TOGGLE, SMD, 6PIN, SPDT, 2POS, ON-ON
DR73-220-R
1
L1
COIL-PWR INDUCTOR, SMD, 7.6mm, 22µH, 20%, 1.62A, COOPER/COILTRONICS
ROHS
ISL85415FRZ
1
U1
IC-500mA BUCK REGULATOR, 12P DFN 3X4
INTERSIL
H1045-DNP
1
C8
CAP, SMD, 0603, DNP-PLACE HOLDER, ROHS
DNI
H2511-DNP
3
R8, R10,
R11
RES, SMD, 0603, DNP-PLACE HOLDER, ROHS
DNI
H1045-DNP
1
CSS
CAP, SMD, 0603, 33000pF, 16V, 10%, X7R, ROHS
DNI
LABEL-RENAME BOARD
1
Submit Document Feedback
5
ISL85415EVAL2Z.
AN1934.0
May 13, 2014
Application Note 1934
ISL85415EVAL2Z Board Layout
FIGURE 3. TOP
Submit Document Feedback
6
AN1934.0
May 13, 2014
Application Note 1934
ISL85415EVAL2Z Board Layout (Continued)
FIGURE 4. BOTTOM
FIGURE 5. LAYER 2
Submit Document Feedback
7
AN1934.0
May 13, 2014
Application Note 1934
ISL85415EVAL2Z Board Layout (Continued)
FIGURE 6. LAYER 3
Submit Document Feedback
8
AN1934.0
May 13, 2014
Application Note 1934
Typical Performance Curves
800
90
700
85
VOUT = -3.3V
500
VOUT = -5V
400
80
EFFICIENCY (%)
IOUT (mA)
600
VOUT = -12V
300
VIN = 12V
75
VIN = 31V
70
VIN = 5V
65
200
60
100
55
VIN = 3V
50
0
0
5
10
15
20
25
30
35
0
100
200
300
400
500
FIGURE 7. MAXIMUM IOUT vs VIN, -VOUT
700
800
FIGURE 8. PFM EFFICIENCY, VOUT = -5V
90
100
95
85
VIN = 12V
90
EFFICIENCY (%)
80
EFFICIENCY (%)
600
IOUT (mA)
VIN (V)
75
70
VIN = 5V
65
VIN = 33V
VIN = 3V
60
VIN = 12V
85
VIN = 24V
80
75
VIN = 5V
70
VIN = 3V
65
60
55
55
50
0
100
200
300
400
500
600
700
50
800
0
100
200
300
FIGURE 9. PFM EFFICIENCY, VOUT = -3.3V
600
3.330
3.325
5.020
VIN = 5V
5.010
VIN = 3V
3.320
VIN = 12V
-VOUT (V)
-VOUT (V)
500
FIGURE 10. PFM EFFICIENCY, VOUT = -12V
5.030
5.000
4.990
4.980
400
IOUT (mA)
IOUT (mA)
VIN = 5V
3.315
VIN = 12V
3.310
3.305
VIN = 33V
VIN = 3V
3.300
VIN = 31V
4.970
3.295
3.290
4.960
0
100
200
300
400
500
600
700
IOUT (mA)
FIGURE 11. PFM LOAD REGULATION, VOUT = -5V
Submit Document Feedback
9
800
0
100
200
300
400
500
600
700
800
IOUT (mA)
FIGURE 12. PFM LOAD REGULATION, VOUT = -3.3V
AN1934.0
May 13, 2014
Application Note 1934
Typical Performance Curves
12.800
5.005
12.790
5.004
12.780
5.003
12.770
5.002
VIN = 24V
-VOUT (V)
-VOUT (V)
(Continued)
12.760
12.750
12.740
IOUT = 200mA
5.000
4.999
4.998
VIN = 12V
12.730
5.001
4.997
12.720
4.996
4.995
12.710
0
100
200
300
400
500
0
600
5
10
15
IOUT (mA)
20
25
30
35
VIN (V)
FIGURE 13. PFM LOAD REGULATION, VOUT = -12V
FIGURE 14. PFM LINE REGULATION, VOUT = -5V, IOUT = 200mA
12.800
3.314
3.312
12.750
3.308
-VOUT (V)
-VOUT (V)
3.310
IOUT = 300mA
3.306
IOUT = 100mA
12.700
12.650
3.304
12.600
3.302
12.550
3.300
0
5
10
15
20
VIN (V)
25
30
FIGURE 15. PFM LINE REGULATION, VOUT = -3.3V, IOUT = 300mA
Submit Document Feedback
10
35
0
5
10
15
VIN (V)
20
25
30
FIGURE 16. PFM LINE REGULATION, VOUT = -12V, IOUT = 100mA
AN1934.0
May 13, 2014
Application Note 1934
Typical Performance Curves
VIN = 24V, VOUT = -5V, MODE = PWM, FSW = 800kHz, TA = +25ºC
PHASE 20V/DIV
PHASE 20V/DIV
VOUT 5V/DIV
VOUT 5V/DIV
IL 500mA/DIV
IL 500mA/DIV
5ms/DIV
100µs/DIV
FIGURE 17. START-UP AT 500mA
FIGURE 18. SHUTDOWN AT 500mA
VOUT 100mV/DIV
PHASE 20V/DIV
VOUT 20mV/DIV
IL 500mA/DIV
IL 500mA/DIV
1µs/DIV
50µs/DIV
FIGURE 19. STEADY STATE AT 500mA LOAD
FIGURE 20. LOAD TRANSIENT
VOUT
100mV/DIV
VOUT
100mV/DIV
IL 500mA/DIV
IL 500mA/DIV
200µs/DIV
FIGURE 21. LOAD TRANSIENT
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback
11
AN1934.0
May 13, 2014
Similar pages