DATASHEET

ISL88705, ISL88706, ISL88707,
ISL88708, ISL88716, ISL88813
Data Sheet
November 30, 2015
FN8092.6
µP Supervisor with Watchdog Timer,
Power-Fail Comparator, Manual Reset and
Adjustable Power-On Reset
Features
Designed with high reset threshold accuracy and low power
consumption, the ISL88705, ISL88706, ISL88707,
ISL88708, ISL88716 and ISL88813 devices are
microprocessor supervisors that are designed to monitor
power-supply and battery functions in microprocessor
systems. They can help to lower system cost, reduce board
space requirements and increase the reliability of systems.
• Additional Voltage Monitor for Power-Fail Detection or
Low-Battery Warning
- Monitors Voltages Down to 1.25V
- Adjustable Power-Fail Input Threshold
These devices provide essential functions such as supply
voltage supervision by asserting a reset output during
power-up and power-down as well as during brownout
conditions. An auxiliary voltage monitor is provided for
detecting power failures warning the system of low battery
conditions or presence detection. In addition, an
independent watchdog timer helps to monitor
microprocessor activity every 1.6s (typical). An active-low
manual reset is offered and reset signals remain asserted
until VDD returns to proper operating levels.
• 140ms Minimum Reset Pulse Width with Option to
Customize Using an External Capacitor
Users can increase the nominal 200ms power-on reset
time-out delay by adding an external capacitor to the CPOR
pin on the ISL88707 and ISL88708.
• Fixed-Voltage Options Allow Precise Monitoring of +3.0V,
+3.3V, and +5.0V Power Supplies
• Watchdog Timer Capability With 1.6s Time-out
• Both RST and RST Outputs Available
• Manual Reset Input on all Devices
• Reset Signal Valid Down to VDD = 1V
• Accurate ±1.8% Voltage Threshold
• Immune to Power-Supply Transients
• Ultra Low 10µA Maximum Supply Current at 3V
• Pb-Free (RoHS Compliant)
Applications
• Portable/Battery Powered Equipment
• Notebook/Desktop Computer Systems
• Designs Using DSPs, Microcontrollers or Microprocessors
• Controllers
• Intelligent Instruments
• Communications Systems
• Industrial Equipment
Pinouts
ISL88705, ISL88706
(8 LD SOIC)
(PDIP - NO LONGER AVAILABLE)
TOP VIEW
ISL88716, ISL88813
(8 LD SOIC)
(PDIP - NO LONGER AVAILABLE)
TOP VIEW
ISL88707, ISL88708
(8 LD SOIC)
(PDIP - NO LONGER AVAILABLE)
TOP VIEW
MR
1
8
WDO
MR
1
8
WDO
MR
1
8
RST
VDD
2
7
RST
VDD
2
7
RST
VDD
2
7
RST
GND
3
6
WDI
GND
3
6
WDI
GND
3
6
CPOR
PFI
4
5
PFO
PFI
4
5
PFO
PFI
4
5
PFO
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas LLC.
Copyright Intersil Americas LLC. 2005, 2006, 2008, 2009, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Ordering Information
PART NUMBER
(Note)
PART
MARKING
VTH
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG. DWG. #
ISL88705IP846Z (No longer available, recommended
replacement: ISL88705IB846Z)
88705 I46Z 4.64V
-40 to +85
8 Ld PDIP**
MDP0031
ISL88813IP846Z (No longer available, recommended
replacement: ISL88813IB846Z)
88813 I46Z 4.64V
-40 to +85
8 Ld PDIP**
MDP0031
ISL88707IP846Z (No longer available, recommended
replacement: ISL88707IB846Z)
88707 I46Z 4.64V
-40 to +85
8 Ld PDIP**
MDP0031
ISL88706IP844Z (No longer available, recommended
replacement: ISL88706IB844Z)
88706 I44Z 4.38V
-40 to +85
8 Ld PDIP**
MDP0031
ISL88708IP844Z (No longer available, recommended
replacement: ISL88708IB844Z)
88708 I44Z 4.38V
-40 to +85
8 Ld PDIP**
MDP0031
ISL88706IP831Z (No longer available, recommended
replacement: ISL88706IB831Z)
88706 I31Z 3.09V
-40 to +85
8 Ld PDIP**
MDP0031
ISL88708IP831Z (No longer available, recommended
replacement: ISL88708IB831Z)
88708 I31Z 3.09V
-40 to +85
8 Ld PDIP**
MDP0031
ISL88706IP829Z (No longer available, recommended
replacement: ISL88706IB829Z)
88706 I29Z 2.92V
-40 to +85
8 Ld PDIP**
MDP0031
ISL88708IP829Z (No longer available, recommended
replacement: ISL88708IB829Z)
88708 I29Z 2.92V
-40 to +85
8 Ld PDIP**
MDP0031
ISL88706IP826Z (No longer available, recommended
replacement: ISL88706IB826Z)
88706 I26Z 2.63V
-40 to +85
8 Ld PDIP**
MDP0031
ISL88716IP826Z (No longer available, recommended
replacement: ISL88716IB826Z)
88716 I26Z 2.63V
-40 to +85
8 Ld PDIP**
MDP0031
ISL88708IP826Z (No longer available, recommended
replacement: ISL88708IB826Z)
88708 I26Z 2.63V
-40 to +85
8 Ld PDIP**
MDP0031
ISL88705IB846Z*
88705 I46Z 4.64V
-40 to +85
8 Ld SOIC
M8.15
ISL88813IB846Z*
88813 I46Z 4.64V
-40 to +85
8 Ld SOIC
M8.15
ISL88707IB846Z*
88707 I46Z 4.64V
-40 to +85
8 Ld SOIC
M8.15
ISL88706IB844Z*
88706 I44Z 4.38V
-40 to +85
8 Ld SOIC
M8.15
ISL88708IB844Z*
88708 I44Z 4.38V
-40 to +85
8 Ld SOIC
M8.15
ISL88706IB831Z*
88706 I31Z 3.09V
-40 to +85
8 Ld SOIC
M8.15
ISL88708IB831Z*
88708 I31Z 3.09V
-40 to +85
8 Ld SOIC
M8.15
ISL88706IB829Z*
88706 I29Z 2.92V
-40 to +85
8 Ld SOIC
M8.15
ISL88708IB829Z*
88708 I29Z 2.92V
-40 to +85
8 Ld SOIC
M8.15
ISL88706IB826Z*
88706 I26Z 2.63V
-40 to +85
8 Ld SOIC
M8.15
ISL88716IB826Z*
88716 I26Z 2.63V
-40 to +85
8 Ld SOIC
M8.15
ISL88708IB826Z*
88708 I26Z 2.63V
-40 to +85
8 Ld SOIC
M8.15
ISL88705EVAL1
Evaluation Board
*Add “-TK” suffix for Tape and Reel Packaging. Please refer to TB347 for details on reel specifications.
**Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
2
FN8092.6
November 30, 2015
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Functional Block Diagrams
VDD
VDD
VDD
RST
± VREF
RST
POR
± VREF
MR
RST
POR
± VREF
MR
PB
WDO
WDI
WDO
WDT
PFI
WDI
PF
PFO
± VREF
GND
ISL88705, ISL88706
3
RST
MR
PB
PB
POR
OSC
CPOR
PF
PFO
WDT
PFI
PF
± VREF
ISL88716, ISL88813
PFO
GND
PFI
± VREF
GND
ISL88707, ISL88708
FN8092.6
November 30, 2015
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Pin Descriptions
ISL88705, ISL88716, ISL88707,
ISL88706 ISL88813 ISL88708 NAME
DESCRIPTION
1
1
1
MR
Manual Reset Input. A reset signal is generated when this input is pulled low. The MR input is an
active low debounced input to which a user can connect a push-button to add manual reset capability
or drive with a signal. The MR pin has an internal 20kpull-up.
2
2
2
VDD
Power Supply Terminal. The voltage at this pin is compared against an internal factory-programmed
voltage trip point, VTH1. A reset is first asserted when the device is initially powered up to ensure that
the power supply has stabilized. Thereafter, reset is again asserted whenever VDD falls below VTH1.
The device is designed with hysteresis to help prevent chattering due to noise and is immune to brief
power-supply transients. The voltage threshold VTH1 is specified in the part number suffix.
3
3
3
GND
Ground Connection
4
4
4
PFI
Power-Fail Input This is an auxiliary monitored voltage input with a 1.25V threshold that causes PFO
state to follow the PFI input state.
5
5
5
PFO
Power-Fail Output. This output goes high if the voltage on PFI is greater than 1.25V, otherwise PFO
stays low.
6
6
CPOR Adjustable POR Time-out Delay Input. Connecting an external capacitor from CPOR to ground
allows the user to increase the Power-On Reset time-out (tPOR) from the nominal 200ms.
6
7
7
WDI
Watchdog Input. The Watchdog Input takes an input from a microprocessor and ensures that it
periodically toggles the WDI pin, otherwise the internal nominal 1.6s watchdog timer runs out, then
reset is asserted and WDO is pulled low. The internal Watchdog Timer is cleared whenever the WDI
sees a rising or falling edge or the device is manually reset. Floating WDI or connecting WDI to a
high-impedance three-state buffer disables the watchdog feature.
RST
Active-Low Reset Output. The RST output is an active low output with an internal PMOS pull-up
that is pulled low to GND when reset is asserted. Reset is asserted whenever:
1. The device is first powered up
2. VDD falls below its minimum voltage sense level or
3. MR is asserted.
The reset output continues to be asserted for typically 200ms after VDD rises above the reset
threshold or MR input goes from low to high. A watchdog time-out will not trigger a reset unless WDO
is connected to MR.
7
8
8
8
4
RST
Active-High Reset Output. The RST pin functions identically to its complementary RST output but
is an active high push-pull output. RST is set high to VDD when reset is asserted. See the RST in “Pin
Descriptions” on page 4 for more details on conditions that cause a reset.
WDO
Watchdog Output. This output is pulled low when the nominal 1.6s internal Watchdog Timer expires
and periodically resets until the watchdog is cleared. WDO also goes low during low VDD conditions.
Whenever VDD is below the reset threshold, WDO stays low. However, unlike RESET, WDO does
not have a minimum pulse width. As soon as VDD rises above the reset threshold, WDO goes high
with no delay.
FN8092.6
November 30, 2015
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Absolute Maximum Ratings
Thermal Information
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any Pin with Respect to GND . . . . . . . . . . . -1.0V to +7V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Thermal Resistance (Typical, Note 1)
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . .-40°C to +85°C
JA (°C/W)
PDIP Package* (4-layer test board) . . . . . . . . . . . . .
83
SOIC Package (4-layer test board) . . . . . . . . . . . . .
110
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
SYMBOL
VDD
Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
PARAMETER
CONDITIONS
Supply Voltage Range
IDD
MIN
TYP
2.0
MAX
UNITS
5.5
V
VDD = 5V, WDT Inactive
10
19
µA
VDD = 3V, WDT Inactive
8
10
µA
ILI
Input Leakage Current (PFI)
100
nA
ILO
Output Leakage Current
100
nA
VOLTAGE THRESHOLDS
VTH1
VTH1HYST
Fixed VDD Voltage Trip Point
Hysteresis at VTH1 Input
Temperature = +25°C
4.556
4.640
4.724
V
4.301
4.380
4.459
V
3.034
3.090
3.146
V
2.867
2.920
2.973
V
2.583
2.630
2.677
V
VTH1 = 4.64V
46
mV
VTH1 = 4.38V
44
mV
VTH1 = 3.09V
37
mV
VTH1 = 2.92V
29
mV
VTH1 = 2.63V
31
mV
RST AND RST
VOL
VOH
Reset Output Voltage Low
RST Output Voltage High
RST Output Voltage High
tRPD
VTH to Reset Asserted Delay
tPOR
POR Time-Out Delay
CLOAD
Load Capacitance on Reset Pins
5
VDD  3.3V, Sinking 2.5mA
0.05
0.40
V
VDD < 3.3V, Sinking 1.5mA
0.05
0.40
V
VDD  3.3V, Sourcing 2.5mA
VDD - 0.6
VDD - 0.4
V
VDD < 3.3V, Sourcing 1.5mA
VDD - 0.6
VDD - 0.4
V
VDD  3.3V, Sourcing 0.8mA
VDD - 0.6
VDD - 0.4
V
VDD < 3.3V, Sourcing 0.5mA
VDD - 0.6
VDD - 0.4
V
45
µs
CPOR is open
140
200
5
260
ms
pF
FN8092.6
November 30, 2015
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Electrical Specifications
SYMBOL
Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested. (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.8
V
MANUAL RESET
VMRL
MR Input Voltage Low
VMRH
MR Input Voltage High
tMR
MR Minimum Pulse Width
RPU
Internal MR Pull-Up Resistor
VDD - 0.6
V
550
ns
20
k
WATCHDOG TIMER (Note 2)
tWDT
Watchdog Time-out Period
1.0
tWDPS
WDI Minimum Pulse Width
100
VIL
Watchdog Input Voltage Low
VIH
Watchdog Input Voltage High
VWDOL
VWDOH
IWDT
WDO Output Voltage Low
WDO Output Voltage High
1.6
2.0
s
ns
0.3 x VDD
V
0.7 x VDD
V
VDD  3.3V, Sinking 2.5mA
0.05
0.40
V
VDD < 3.3V, Sinking 1.5mA
0.05
0.40
V
VDD  3.3V, Sourcing 2.5mA
VDD - 0.6
VDD - 0.4
V
VDD < 3.3V, Sourcing 1.5mA
VDD - 0.6
VDD - 0.4
V
Watchdog Input Current
1
µA
1.30
V
POWER-FAIL DETECTION
VTHPFI
PFI Input Threshold Voltage
MR = Open
1.20
1.25
PFIVTHHYST Hysteresis Voltage
VPFOL
VPFOH
PFO Output Voltage Low
PFO Output Voltage High
20
mV
VDD  3.3V, Sinking 2.5mA
0.05
0.40
V
VDD < 3.3V, Sinking 1.5mA
0.05
0.40
V
VDD  3.3V, Sourcing 2.5mA
VDD - 0.6
VDD - 0.4
V
VDD < 3.3V, Sourcing 1.5mA
VDD - 0.6
VDD - 0.4
V
NOTE:
2. Applies to ISL88705, ISL88706, ISL88716, and ISL88813.
Principles of Operation
Power-On Reset (POR)
The ISL88705, ISL88706, ISL88707, ISL88708, ISL88716,
ISL88813 devices provide those functions needed for
monitoring critical voltages such as power-supply and battery
functions in microprocessor systems. Features of these
supervisors include Power-On Reset control, Supply Voltage
Supervision, Power-Fail Detection and Manual Reset
Assertion. The integration of all these features along with high
reset threshold accuracy and low power consumption make
these devices ideal for portable or battery-powered equipment.
Applying power to the device activates a POR circuit which
asserts reset (i.e. RST goes high while RST goes low). These
signals provide several benefits:
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
• It prevents the processor from operating prior to stabilization
of the oscillator.
• It ensures that the monitored device is held out of operation
until internal registers are properly loaded.
• It allows time for an FPGA to download its configuration prior
to initialization of the circuit.
The reset signals remain active until VDD rises above the
minimum voltage sense level for time period tPOR. This
ensures that the supply voltage has stabilized to sufficient
operating levels.
6
FN8092.6
November 30, 2015
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
VTH1
VDD
1V
>tMR
MR
tPOR
tRPD
tPOR
tPOR
RST
RST
FIGURE 1. POWER-SUPPLY MONITORING TIMING DIAGRAM (WDI TRI-STATED)
Low Voltage Monitoring
.
These devices monitor both the voltage level of VDD and an
auxiliary voltage on PFI.
When IC is initially biased reset is asserted until the VDD
voltage is greater than the specific IC fixed-voltage trip point
for the tPOR duration of 200ms. At any subsequent time that
VDD does not exceed its voltage threshold, reset is once
again asserted, i.e. RST is high and RST is low (see
Figure 1).
Power Failure Monitor
.
These devices also have a Power-Failure Monitor that helps
to monitor an additional critical voltage on the Power-Fail
Input (PFI) pin. For example, the PFI pin could be used to
provide an early power-fail warning, detect a low-battery
condition, presence detection or simply monitor a power
supply other than +5V. The 1.25V threshold detector can be
adjusted using an external resistor divider network to provide
custom voltage monitoring of voltages greater than 1.25V,
according to Equation 1 (see Figure 2).
 R 1 + R 2
PFI VTH = 1.25  ---------------------
 R2 
(EQ. 1)
R1
VIN
PFI
R2
ISL8870x
FIGURE 2. CUSTOM VTH WITH RESISTOR DIVIDER ON PFI
If using a voltage divider on the PFI input to critique an
external voltage and intending to use the MR input to initiate
resets then avoid having the PFI voltage less than PFI Vth
+2.2V as unintended PFO transition may occur when MR is
transitioning high.
Adjusting tPOR
On the ISL88707 and ISL88708, users can adjust the
Power-On Reset time-out delay (tPOR) to many times the
nominal tPOR of 200ms. To do this, connect a capacitor
between CPOR and ground (see Figure 3). For example,
connecting a 50pF capacitor to CPOR will increase tPOR from
200ms to ~1.4s. Care should be taken in PCB layout and
capacitor placement in order to reduce stray capacitance as
much as possible, which contributes to tPOR error.
PFO goes low whenever PFI is less than the 1.25V (or
user-set) threshold voltage.
7
FN8092.6
November 30, 2015
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Watchdog Timer
.
The Watchdog Timer circuit checks microprocessor activity
by monitoring the WDI input pin. The microprocessor must
periodically toggle the WDI pin within tWDT (typically ~1.6s),
otherwise the WDO pin pulls low (see Figure 5). The WDO
then signals reset periodically (typically ~1.9s) for ~220ms
until the WDI is again toggled. Internally, the 1.6s timer is
cleared by either a reset or by toggling the WDI input, which
can detect pulses longer than 50ns.
CPOR
Whenever there is a low-voltage VDD condition, WDO goes
low. Unlike the reset outputs, however, WDO does not have
a minimum reset pulse width (tPOR). WDO goes high as
soon as VDD rises above its voltage trip point (see Figure 5).
With WDI open or connected to a tristated high impedance
input, the Watchdog Timer is disabled and only pulls low
when VDD < VTH1.
ISL88707, ISL88708
14
NORMALIZED tPOR vs CPOR (pF)
OPEN = 200ms
12
10
8
6
4
2
0
0
10
20
30
40
50
60
70
80
90
100
CPOR (pF)
FIGURE 3. ADJUSTING tPOR WITH A CAPACITOR
Manual Reset
The manual-reset input (MR) allows the user to trigger a
reset by using a push-button switch. The MR input is an
active low debounced input. By connecting a push-button
directly from MR to ground, the designer adds manual
system reset capability (see Figure 4). Reset is asserted if
the MR pin is pulled low to less than 100mV for the minimum
MR pulse width or longer while the push-button is closed.
After MR is released, the reset outputs remain asserted for
tPOR (200ms) and then released.
20k
MR
PB
ISL8870x
FIGURE 4. CONNECTING A MANUAL RESET PUSH-BUTTON
8
FN8092.6
November 30, 2015
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
VTH1
VDD
1V
< tWDT
< tWDT
< tWDT
WDI
tWDT
tWDT
>tWDPS
WDO
tPOR
tPOR
tRPD
RST
tPOR
FIGURE 5. WATCHDOG TIMING DIAGRAM
Typical Performance Curves
4.70
11.0
4.65
VDD = 5V
10.0
4.60
9.50
4.55
9.00
4.50
VTH1 (V)
IDD (µA)
10.5
8.50
8.00
7.50
VDD = 3.3V
4.45
4.40
4.30
6.50
4.25
-40 -30 -20 -10
VTH = 4.38V
4.36
7.00
6.00
VTH = 4.64V
0
10
20
30
40
50
60
70
4.20
90
-40 -30 -20 -10
10
20
30
40
50
60
70
90
FIGURE 7. VTH1 vs TEMPERATURE FOR 5V SUPPLY
FIGURE 6. IDD vs TEMPERATURE
1.2530
3.2
3.1
1.2525
VTHPFI (V)
VTH = 3.09V
3.0
VTH1 (V)
0
TEMPERATURE (°C)
TEMPERATURE (°C)
2.9
2.8
VTH = 2.92V
2.7
1.2520
1.2515
1.2510
2.6
1.2505
2.5
2.4
VTH = 2.63V
-40 -30 -20 -10
0
10
20
30
1.2500
40
50
60
70
TEMPERATURE (°C)
FIGURE 8. VTH1 vs TEMPERATURE < 5V SUPPLY
9
90
-40 -30 -20 -10
0
10
20
30
40
50
60
70
90
TEMPERATURE (°C)
FIGURE 9. VTHPFI vs TEMPERATURE
FN8092.6
November 30, 2015
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Typical Performance Curves (Continued)
VDD
VDD
RESET
OPEN
172ms
RESET
tPOR = 213ms
15pF
588ms
RESET
50pF
1.5s
4.7pF
312ms
33pF
1.1s
CPOR = OPEN
FIGURE 10. RESET AND RESET ASSERTION
FIGURE 11. RESET ASSERTION vs CPOR
VDD
PFO
RESET
RESET
PFI
FIGURE 12. RESET AND RESET DEASSERTION
10
PFI VTH
FIGURE 13. 5V PFI TO PFO RESPONSE
FN8092.6
November 30, 2015
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Typical Performance Curves (Continued)
VDD
5.5V OV
RESET
FIGURE 14. 5V OV/UV MONITORING
ISL88705EVAL1 and Applications
The ISL88705EVAL1 supports all six of the ISL88705,
ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
devices, enabling evaluation of basic functional operation
and common application implementations. Figures 15 and
17 illustrate the ISL88705EVAL1 in photographic and
schematic forms respectively.
The ISL88705EVAL1 is divided into two banks; each bank
having one each of the three available pinouts. The top bank
is fully populated and immediately usable whereas the
bottom bank is unpopulated. Samples of other sample
variants can be evaluated singularly or in combination with
any other variant to provide a specific voltage monitoring
solution. The left position has the ISL88705IB846Z
monitoring the VDD rail voltage for a minimum of 4.64V with
reset signaling. In addition, the power fail input (PFI) is being
compared to the internal PFI voltage reference of 1.25V and
the power fail output (PFO) will report the PFI condition. This
feature can be used for monitoring an auxiliary voltage,
providing an early warning of a brown-out or power failure or
presence detection in a system.
The middle position has the ISL88813IB846Z installed and is
set-up as a 5V window detector with jumper J1 installed. The
VDD monitors for UV and the PFI for OV via the R3, R4
divider. The PFO output is inverted and connected to the
manual reset input (MR) via U4. Hence, a reset signal is
generated when 4.64V < VDD > 5.38V. With J1 removed, the
PFO will be an OV indicator but no reset signal will be
generated. Both of these positions share a common
Watchdog input (WDI) signal although each has its own
Watchdog output (WDO).
11
The right position has the ISL88707IB846Z and is set-up as
a +12V and +5V UV monitor with reset signal. The PFI
allows monitoring of any voltage above the 1.25V PFI
reference and with a resistor divider this is used to monitor
the 12V. The ISL88707 and ISL88708 have the unique
feature of an adjustable time to reset (tPOR) signal
generation capability via the CPOR pin with an external
capacitor to GND. This evaluation platform has an adjustable
SMD capacitor, C4 (8pF to 45pF) that allows easy evaluation
of this feature. Also unique to the ISL88707 and ISL88708
are both the RESET and RESET outputs, all other variants
having only one or the other.
Figures 10, 11, 12, 13 and 14 illustrate the basic IC functions
and performance of the 3 implementations.
FIGURE 15. ISL88705EVAL1
FN8092.6
November 30, 2015
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Bipolar Voltage Sensing
Special Application Considerations
Any of the ISL88705, ISL88706, ISL88707, ISL88708,
ISL88716, ISL88813 devices can be used to sense and
report the presence of both a positive and negative voltage
via the PFI and PFO, as shown in Figure 16. The VDD
monitors the positive voltage as normal and the PFI monitors
the presence of the negative supply. As the differential
voltage across the R1, R2 divider is increased, the resistor
values must be chosen such that the PFI node is <1.25V
when the -V supply is satisfactory and the positive supply is
at its maximum specified value. This allows the positive
supply to fluctuate within its acceptable range without
signaling a reset. Driving the MR with the inverted PFO
signal as shown provides for reset generation when -V is not
satisfactorily present. Reset will remain asserted as long as
PFO is high.
Using good decoupling practices will prevent transients
(i.e., due to switching noises and short duration droops in the
supply voltage) from causing unwanted resets.
When using the CPOR pin, avoid stray capacitance during
layout as much as possible in order to minimize its effect on
the tPOR timing.
If using a voltage resistor divider on the PFI input to critique
an external voltage and intending to use the MR input to
initiate resets then avoid having the PFI voltage less than
PFI Vth +2.2V as unintended PFO transition may occur
when MR is transitioning high.
+5V
100k
VDD
R1
MR
100k
PFO
PFI
2N3904
R2
RST
-5V
ISL8870x, ISL88716, ISL88813
RESET
V+
V-
FIGURE 16. ±5V MONITORING
12
FN8092.6
November 30, 2015
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
FIGURE 17. ISL88705EVAL1 SCHEMATIC (TOP BANK)
13
FN8092.6
November 30, 2015
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
November 30, 2015
FN8092.6
CHANGE
Updated Ordering Information table on page 2.
Added Revision History and About Intersil sections.
Updated Package Outline Drawing M8.15 to the latest revision. Changes are as follows:
-Updated to new POD format by removing table and moving dimensions onto drawing and adding land
pattern.
-Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
-Changed Note 1 “1982” to “1994”.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN8092.6
November 30, 2015
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Plastic Dual-In-Line Packages (PDIP)
E
D
A2
SEATING
PLANE
L
N
A
PIN #1
INDEX
E1
c
e
b
A1
NOTE 5
1
eA
eB
2
N/2
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
TOLERANCE
A
0.210
0.210
0.210
0.210
0.210
MAX
A1
0.015
0.015
0.015
0.015
0.015
MIN
A2
0.130
0.130
0.130
0.130
0.130
±0.005
b
0.018
0.018
0.018
0.018
0.018
±0.002
b2
0.060
0.060
0.060
0.060
0.060
+0.010/-0.015
c
0.010
0.010
0.010
0.010
0.010
+0.004/-0.002
D
0.375
0.750
0.750
0.890
1.020
±0.010
E
0.310
0.310
0.310
0.310
0.310
+0.015/-0.010
E1
0.250
0.250
0.250
0.250
0.250
±0.005
e
0.100
0.100
0.100
0.100
0.100
Basic
eA
0.300
0.300
0.300
0.300
0.300
Basic
eB
0.345
0.345
0.345
0.345
0.345
±0.025
L
0.125
0.125
0.125
0.125
0.125
±0.010
N
8
14
16
18
20
Reference
NOTES
1
2
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
15
FN8092.6
November 30, 2015
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
16
FN8092.6
November 30, 2015
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