DATASHEET

DATASHEET
High Speed, Dual Channel, 6A, Power MOSFET Driver
with Enable Inputs
ISL89163, ISL89164, ISL89165
Features
The ISL89163, ISL89164, and ISL89165 are high-speed, 6A,
dual channel MOSFET drivers with enable inputs. These parts are
very similar to the ISL89160, ISL89161, ISL89162 drivers but
with an added enable input for each channel occupying NC pins 1
and 8 of the ISL89160, ISL89161, ISL89162.
• Dual output, 6A peak currents, can be paralleled
Precision thresholds on all logic inputs allow the use of external
RC circuits to generate accurate and stable time delays on both
the main channel inputs, INA and INB, and the enable inputs,
ENA and ENB. The precision delays capable of these precise logic
thresholds makes these parts very useful for dead time control
and synchronous rectifiers. Note that the ENable and INput logic
inputs can be interchanged for alternate logic implementations.
• Very low thermal impedance (JC = 3°C/W)
Three input logic thresholds are available: 3.3V (CMOS), 5.0V
(CMOS or TTL compatible), and CMOS thresholds that are
proportional to VDD.
Applications
At high switching frequencies, these MOSFET drivers use very
little internal bias currents. Separate, non-overlapping drive
circuits are used to drive each CMOS output FET to prevent
shoot-thru currents in the output stage.
• Switch mode power supplies
The start-up sequence is design to prevent unexpected glitches
when VDD is being turned on or turned off. When VDD < ~1V, an
internal 10kΩ resistor between the output and ground helps to
keep the output voltage low. When ~1V < VDD < UV, both outputs
are driven low with very low resistance and the logic inputs are
ignored. This insures that the driven FETs are off. When
VDD > UVLO, and after a short delay, the outputs now respond to
the logic inputs.
• Dual AND-ed input logic, (INput and ENable)
• Typical ON-resistance <1Ω
• Specified Miller plateau drive currents
• Hysteretic Input logic levels for 3.3V CMOS, 5V CMOS, TTL and
Logic levels proportional to VDD
• Precision threshold inputs for time delays with external RC
components
• 20ns rise and fall time driving a 10nF load.
• Synchronous Rectifier (SR) Driver
• Motor Drives, Class D amplifiers, UPS, Inverters
• Pulse Transformer driver
• Clock/Line driver
Related Literature
• AN1603 “ISL6752/54EVAL1Z ZVS DC/DC Power Supply with
Synchronous Rectifiers User Guide”
3.0
ENB
ENA
INA
GND
INB
1
8
2
7
3
EPAD
6
5
4
OUTA
OUTB
4.7µF
POSITIVE THRESHOLD LIMITS
OPTION B THRESHOLDS (5.0V)
V DD
2.5
2.0
1.5
1.0
0.5
0.0
-40 -25 -10
FIGURE 1. TYPICAL APPLICATION
September 30, 2015
FN7707.4
1
NEGATIVE THRESHOLD LIMITS
5
20 35 50 65 80
TEMPERATURE (°C)
95 110 125
FIGURE 2. TEMP STABLE LOGIC THRESHOLDS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC. 2010-2012, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL89163, ISL89164, ISL89165
Block Diagram
VDD
FOR CLARITY, ONLY ONE
CHANNEL IS SHOWN
FOR OPTIONS A AND B, THE UV
COMPARATOR HOLDS OFF THE
OUTPUTS UNTIL VDD ~> 3.3VDC.
FOR OPTION C, THE UV RELEASE
IS ~> 6.5V
SEPARATE FET DRIVES, WITH NON-OVERLAPPING
OUTPUTS, PREVENT SHOOT-THRU CURRENTS IN
THE OUTPUT CMOS FETS RESULTING WITH VERY
LOW HIGH FREQUENCY OPERATING CURRENTS.
ENx
ISL89163
ENX AND INX INPUTS ARE
IDENTICAL AND MAY BE
INTERCHANGED FOR
ALTERNATE LOGIC
OUTx
INx
10k
ISL89164, ISL89165
GND
EPAD
FOR PROPER THERMAL AND ELECTRICAL
PERFORMANCE, THE EPAD MUST BE
CONNECTED TO THE PCB GROUND PLANE.
Pin Configurations
ISL89164FR, ISL89164FB
(8 LD TDFN, EPSOIC)
TOP VIEW
ISL89163FR, ISL89163FB
(8 LD TDFN, EPSOIC)
TOP VIEW
ENA 1
INA 2
GND 3
INB 4
Pin Descriptions
8 ENB
ENA 1
8 ENB
7 OUTA
/INA 2
7 OUTA
6 VDD
GND 3
6 VDD
5 OUTB
/INB 4
5 OUTB
ISL89165FR, ISL89165FB
(8 LD TDFN, EPSOIC)
TOP VIEW
ENA 1
8 ENB
/INA 2
7 OUTA
GND 3
6 VDD
INB 4
DESCRIPTION
(See Truth Table for
Logic Polarities)
PIN
NUMBER
SYMBOL
1
ENA
2
INA, /INA
3
GND
4
INB, /INB
5
OUTB
Channel B output
6
VDD
Power input, 4.5V to 16V
7
OUTA
Channel A output, 0V to VDD
8
ENB
Channel B enable, 0V to VDD
EPAD
Power Ground, 0V
ENx
INx
5 OUTB
Channel A enable, 0V to VDD
Channel A input, 0V to VDD
Power Ground, 0V
Channel B enable, 0V to VDD
OUTx
ENx
/INx
OUTx
NON-INVERTING
INVERTING
UV
ENx*
INx*
OUTx*
UV
ENx*
/INx*
OUTx*
0
x
x
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
0
*SUBSTITUTE A OR B FOR x
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FN7707.4
September 30, 2015
ISL89163, ISL89164, ISL89165
Ordering Information
PART NUMBER
(Notes 1, 2, 3, 4)
PART MARKING TEMP RANGE (°C) INPUT CONFIGURATION
ISL89163FRTAZ
163A
-40 to +125
ISL89163FRTBZ
163B
-40 to +125
ISL89164FRTAZ
164A
-40 to +125
ISL89164FRTBZ
164B
-40 to +125
ISL89165FRTAZ
165A
-40 to +125
ISL89165FRTBZ
165B
-40 to +125
ISL89163FBEAZ
89163 FBEAZ
-40 to +125
ISL89163FBEBZ
89163 FBEBZ
-40 to +125
ISL89164FBEAZ
89164 FBEAZ
-40 to +125
ISL89164FBEBZ
89164 FBEBZ
-40 to +125
ISL89165FBEAZ
89165 FBEAZ
-40 to +125
ISL89165FBEBZ
89165 FBEBZ
-40 to +125
non-inverting
INPUT LOGIC
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
3.3V
8 Ld 3x3 TDFN
L8.3x3I
5.0V
8 Ld 3x3 TDFN
L8.3x3I
inverting
3.3V
8 Ld 3x3 TDFN
L8.3x3I
5.0V
8 Ld 3x3 TDFN
L8.3x3I
inverting + non-inverting
3.3V
8 Ld 3x3 TDFN
L8.3x3I
5.0V
8 Ld 3x3 TDFN
L8.3x3I
non-inverting
3.3V
8 Ld EPSOIC
M8.15D
5.0V
8 Ld EPSOIC
M8.15D
inverting
3.3V
8 Ld EPSOIC
M8.15D
5.0V
8 Ld EPSOIC
M8.15D
3.3V
8 Ld EPSOIC
M8.15D
5.0V
8 Ld EPSOIC
M8.15D
inverting + non-inverting
NOTES:
1. Add “-T*”, suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. Input Logic Voltage: A = 3.3V, B = 5.0V.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL89163, ISL89164, ISL89165. For more information on MSL, please
see Technical Brief TB363.
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ISL89163, ISL89164, ISL89165
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD Relative to GND . . . . . . . . . . . . . . . . . . . . -0.3V to 18V
Logic Inputs (INA, INB, ENA, ENB) . . . . . . . . . . . . GND - 0.3v to VDD + 0.3V
Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3v to VDD + 0.3V
Average Output Current (Note 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150mA
ESD Ratings
Human Body Model Class 2 (Tested per JESD22-A114E) . . . . . . 2000V
Machine Model Class B (Tested per JESD22-A115-A) . . . . . . . . . . 200V
Charged Device Model Class IV . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V
Latch-Up
(Tested per JESD-78B; Class 2, Level A)
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld TDFN Package (Notes 5, 6). . . . . . . . .
44
3
8 Ld EPSOIC Package (Notes 5, 6) . . . . . . .
42
3
Max Power Dissipation at +25°C in Free Air . . . . . . . . . . . . . . . . . . . . . 2.27W
Max Power Dissipation at +25°C with Copper Plane . . . . . . . . . . . . . 33.3W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Operating Junction Temp Range . . . . . . . . . . .-40°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Options A and B
Supply Voltage, VDD Relative to GND. . . . . . . . . . . . . . . . . . . .4.5V to 16V
Logic Inputs (INA, INB, ENA, ENB) . . . . . . . . . . . . . . . . . . . . . . 0V to VDD
Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD
Option C
Supply Voltage, VDD Relative to GND. . . . . . . . . . . . . . . . . . . .7.5V to 16V
Logic Inputs (INA, INB, ENA, ENB) . . . . . . . . . . . . . . . . . . . . . . 0V to VDD
Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output current. The peak output
currents of this driver are self limiting by trans conductance or rDS(ON) and do not required any external components to minimize the peaks. If the
output is driving a non-capacitive load, such as an LED, maximum output current must be limited by external means to less than the specified
absolute maximum.
DC Electrical Specifications VDD = 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits apply
over the operating junction temperature range, -40°C to +125°C.
TJ = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
TJ = -40°C to +125°C
MIN
TYP
MAX
MIN
(Note 8)
MAX
(Note 8)
UNITS
POWER SUPPLY
Voltage Range (Option A and B)
VDD
-
-
-
4.5
16
V
Voltage Range (Option C)
VDD
-
-
-
7.5
16
V
VDD Quiescent Current
IDD
ENx = INx = GND
-
5
-
-
-
mA
INA = INB = 1MHz, square wave
-
25
-
-
mA
-
3.3
-
-
UNDERVOLTAGE
VDD Undervoltage Lock-out
(Options A and B) (Note 12,
Figure 9)
VUV
ENA = ENB = True
INA = INB = True
VDD Undervoltage Lock-out
(Option C) (Note 12, Figure 9)
VUV
ENA = ENB = True
INA = INB = True (Note 9)
-
V
-
6.5
-
-
-
Hysteresis (Option A or B)
-
~25
-
-
-
mV
Hysteresis (Option C)
-
~0.95
-
-
-
V
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4
V
FN7707.4
September 30, 2015
ISL89163, ISL89164, ISL89165
DC Electrical Specifications VDD = 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits apply
over the operating junction temperature range, -40°C to +125°C. (Continued)
TJ = +25°C
PARAMETERS
SYMBOL
TJ = -40°C to +125°C
MIN
TYP
MAX
MIN
(Note 8)
MAX
(Note 8)
UNITS
Option A, B, or C
-
-
-
GND
VDD
V
Option A, nominally 37% x 3.3V
-
1.22
-
1.12
1.32
V
Option B, nominally 37% x 5.0V
-
1.85
-
1.70
2.00
V
Option C, nominally 20% x 12V
(Note 9)
-
2.4
-
2.00
2.76
V
Option A, nominally 63% x 3.3V
-
2.08
-
1.98
2.18
V
Option B, nominally 63% x 5.0V
-
3.15
-
3.00
3.30
V
Option C, nominally 80% x 12V
(Note 9)
-
9.6
-
9.24
9.96
V
-
2
-
-
-
pF
-
-
-
-10
+10
µA
TEST CONDITIONS
INPUTS
Input Range
for INA, INB, ENA, ENB
VIN
Logic 0 Threshold
for INA, INB, ENA, ENB
(Note 11)
VIL
Logic 1 Threshold
for INA, INB, ENA, ENB
(Note 11)
VIH
Input Capacitance of INA, INB,
ENA, ENB (Note 10)
CIN
Input Bias Current
for INA, INB, ENA, ENB
IIN
GND < VIN < VDD
OUTPUTS
High Level Output Voltage
VOHA VOHB
-
-
-
VDD - 0.1
VDD
V
Low Level Output Voltage
VOLA
VOLB
-
-
-
GND
GND + 0.1
V
Peak Output Source Current
IO
VO (initial) = 0V, CLOAD = 10nF
-
-6
-
-
-
A
Peak Output Sink Current
IO
VO (initial) = 12V, CLOAD = 10nF
-
+6
-
-
-
A
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. The nominal 20% and 80% thresholds for option C are valid for any value within the specified range of VDD.
10. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated by the PCB parasitic
capacitance.
11. The true state input voltage for the non-inverted inputs is greater than the Logic 1 threshold voltage. The true state input voltage for the inverted
inputs is less than the logic 0 threshold voltage.
12. A 400µs delay further inhibits the release of the output state when the UV positive going threshold is crossed. See Figure 9.
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FN7707.4
September 30, 2015
ISL89163, ISL89164, ISL89165
AC Electrical Specifications
VDD = 12V, GND = 0V, No Load on OUTA or OUTB, unless otherwise specified. Boldface limits apply
over the operating junction temperature range, -40°C to +125°C.
PARAMETERS
SYMBOL
TEST CONDITIONS
/NOTES
TJ = +25°C
TJ = -40°C to +125°C
MIN
TYP
MAX
MIN
MAX
UNITS
Output Rise Time (see Figure 4)
tR
CLOAD = 10nF,
10% to 90%
-
20
-
-
40
ns
Output Fall Time (see Figure 4)
tF
CLOAD = 10nF,
90% to 10%
-
20
-
-
40
ns
VDD = 12V
options A and B
-
25
-
-
50
ns
VDD = 8V
option C
-
25
-
-
50
ns
VDD = 12V
options A and B
-
25
-
-
50
ns
VDD = 8V
option C
-
25
-
-
50
ns
VDD = 12V
options A and B
-
25
-
-
50
ns
VDD = 8V
option C
-
25
-
-
50
ns
VDD = 12V
options A and B
-
25
-
-
50
ns
VDD = 8V
option C
-
25
-
-
50
ns
Output Rising Edge Propagation Delay for
Non-Inverting Inputs (Note 13)
(see Figure 3)
Output Rising Edge Propagation Delay with Inverting
Inputs (Note 13)
(see Figure 3)
Output Falling Edge Propagation Delay with
Non-Inverting Inputs (Note 13)
(see Figure 3)
Output Falling Edge Propagation Delay with Inverting
Inputs (Note 13)
(see Figure 3)
tRDLYn
tRDLYi
tFDLYn
tFDLYi
Rising Propagation Matching (see Figure 3)
tRM
No load
-
<1
-
-
-
ns
Falling Propagation Matching (see Figure 3)
tFM
No load
-
<1
-
-
-
ns
-IMP
VDD = 10V,
VMILLER = 5V
-
6
-
-
-
A
-IMP
VDD = 10V,
VMILLER = 3V
-
4.7
-
-
-
A
-IMP
VDD = 10V,
VMILLER= 2V
-
3.7
-
-
-
A
IMP
VDD = 10V,
VMILLER = 5V
-
5.2
-
-
-
A
IMP
VDD = 10V,
VMILLER = 3V
-
5.8
-
-
-
A
IMP
VDD = 10V,
VMILLER = 2V
-
6.9
-
-
-
A
Miller Plateau Sink Current
(See Test Circuit Figure 5)
Miller Plateau Source Current
(See Test Circuit Figure 6)
NOTE:
13. Propagation delays for option C are typically the same for the recommended operating range (7.5V ≤ VDD ≤ 16V).
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ISL89163, ISL89164, ISL89165
Test Waveforms and Circuits
VDD
80%
Option C
INA, INB,
ENA, ENB
50%
INA, INB,
ENA, ENB
20%
0V
t RDLY
3.3V Option A
5.0V Option B
50%
Option A or B
0V
90%
t FDLY
/OUTA
OUTA
t RDLY
OUTA
OR
OUTB
t FDLY
/OUTB
10%
tR
tF
OUTB
t RM
t FM
LOGIC LEVELS: OPTION A = 3.3V, OPTION B = 5.0V, OPTION C = VDD
FIGURE 3. PROP DELAYS AND MATCHING
FIGURE 4. RISE/FALL TIMES
10V
10V
ISL8916x
ISL8916x
0.1µF
10k
0.1µF
10k
VMILLER
VMILLER
10µF
200ns
10µF
200ns
10nF
+ISENSE
+ISENSE
10nF
50m
50m
-ISENSE
-ISENSE
FIGURE 5. MILLER PLATEAU SINK CURRENT TEST CIRCUIT
10V
FIGURE 6. MILLER PLATEAU SOURCE CURRENT TEST CIRCUIT
IM P
CURRENT THROUGH 0.1
RESISTOR
0A
V M ILLER
V OUT
V OUT
V M ILLER
-I M P
CURRENT THROUGH 0.1
RESISTOR
0
0V
200ns
FIGURE 7. MILLER PLATEAU SINK CURRENT
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7
200ns
FIGURE 8. MILLER PLATEAU SOURCE CURRENT
FN7707.4
September 30, 2015
ISL89163, ISL89164, ISL89165
Test Waveforms and Circuits
Rising VDD
This duration is dependant
on rise time of VDD
UV Threshold
This duration is
independent on
rise time of VDD
~1V
10k to
ground
outputs controlled by
logical inputs
outputs
active low
OUTA, OUTB
OUTPUT STATE
Up to 400µs
<1 to ground
FIGURE 9. START-UP OUTPUT CHARACTERISTIC
Typical Performance Curves
3.5
35
+125°C
1MHz BIAS CURRENT (mA)
STATIC BIAS CURRENT (mA)
+125°C
3.0
+25°C
-40°C
2.5
2.0
4
8
12
VDD
FIGURE 10. IDD vs VDD (STATIC)
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8
16
30
+25°C
25
-40°C
20
15
10
5
4
8
12
16
VDD
FIGURE 11. IDD vs VDD (1MHz)
FN7707.4
September 30, 2015
ISL89163, ISL89164, ISL89165
Typical Performance Curves (Continued)
50
1.1
16V
NO LOAD
0.9
10V
30
rDS(ON) ()
IDD (mA)
40
VOUT LOW
1.0
12V
20
5V
0.7
10
0
VOUT HIGH
0.8
0.6
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.5
-45
2.0
-20
5
FREQUENCY (MHz)
FIGURE 12. IDD vs FREQUENCY (+25°C)
INPUT LOGIC THRESHOLDS (3.3V)
INPUT LOGIC THRESHOLDS (3.3V)
105
130
2.5
2.0
POSITIVE THRESHOLD
1.5
NEGATIVE THRESHOLD
1.0
0.5
-20
5
30
55
80
105
105
130
2.5
2.0
NEGATIVE THRESHOLD
1.5
1.0
0.5
0.0
-45
130
POSITIVE THRESHOLD
3.0
-20
5
TEMPERATURE (°C)
30
55
80
TEMPERATURE (°C)
FIGURE 14. OPTION A THRESHOLDS
FIGURE 15. OPTION B THRESHOLDS
25
30
PROPAGATION DELAY (ns)
FALL TIME, CLOAD = 10nF
RISE/FALL TIME (ns)
80
3.5
3.0
20
RISE TIME, CLOAD = 10nF
15
-45
55
FIGURE 13. rDS(ON) vs TEMPERATURE
3.5
0.0
-45
30
TEMPERATURE (°C)
-20
5
30
55
80
TEMPERATURE (°C)
FIGURE 16. OUTPUT RISE/FALL TIME
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9
105
130
OUTPUT FALLING PROP DELAY
25
OUTPUT RISING PROP DELAY
20
15
5
7
9
11
VDD
13
15
FIGURE 17. PROPAGATION DELAY vs VDD
FN7707.4
September 30, 2015
ISL89163, ISL89164, ISL89165
Functional Description
ENx
D
Overview
INx
The ISL89163, ISL89164, ISL89165 MOSFET drivers incorporate
several features optimized for Synchronous Rectifier (SR) driver
applications including precision input logic thresholds, enable
inputs, undervoltage lock-out, and high amplitude output drive
currents.
The precision input thresholds facilitate the use of an external RC
network to delay the rising or falling propagation of the driver
output. This is a useful feature for adjusting when the SRs turn on
relative to the primary side FETs. In a similar manner, these
drivers can also be used to control the turn-on/off timing of the
primary side FETs.
The Enable inputs (ENA, ENB) are used to emulate diode
operation of the SRs by disabling the driver output when it is
necessary to prevent negative currents in the output filter
inductors. An example is turning off the SRs when the power
supply output is turned off. This prevents the output capacitor
from being discharged through the output inductor. If this is
allowed to happen, the voltage across the output capacitor will
ring negative possibly damaging the capacitor (if it is polarized)
and probably damaging the load. Another example is preventing
circulating currents between paralleled power supplies during no
or light load conditions. During light load conditions (especially
when active load sharing is not active), energy will be transferred
from the paralleled power supply that has a higher voltage to the
paralleled power supply with the lower voltage. Consequently, the
energy that is absorbed by the low voltage output is then
transferred to the primary side causing the bus voltage to
increase until the primary side is damaged by excessive voltage.
The start-up sequence for input threshold options A, B, and C is
designed to prevent unexpected glitches when VDD is being
turned on or turned off. When VDD < ~1V, an internal 10kΩ
resistor connected between the output and ground, help to keep
the gate voltage close to ground. When ~1V < VDD < UV, both
outputs are driven low while ignoring the logic inputs. This low
state has the same current sinking capacity as during normal
operation. This insures that the driven FETs are held off even if
there is a switching voltage on the drains that can inject charge
into the gates via the Miller capacitance. When VDD > UVLO, and
after a 400µs delay, the outputs now respond to the logic inputs.
See Figure 9 for complete details.
For the negative transition of VDD through the UV lockout voltage,
the outputs of input threshold options A or B are active low when
VDD < ~3.2VDC regardless of the input logic states. Similarly, the
C option outputs are active low when VDD < ~6.5VDC.
Application Information
Precision Thresholds for Time Delays
Three input logic voltage levels are supported by the ISL89163,
ISL89164, ISL89165. Option A is used for 3.3V logic, Option B is
used for 5.0V logic, and Option C is used for higher voltage logic
when it is desired to have voltage thresholds that are
proportional to VDD. The A and B options have nominal
thresholds that are 37% and 63% of 3.3V and 5.0V respectively
and the C option is 20% and 80% of VDD.
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10
Rdel
OUTx
cdel
FIGURE 18. DELAY USING RCD NETWORK
In Figure 18, Rdel and Cdel delay the rising edge of the input
signal. For the falling edge of the input signal, the diode shorts
out the resistor resulting in a minimal falling edge delay.
The 37% and 63% thresholds of options A and B were chosen to
simplify the calculations for the desired time delays. When using
an RC circuit to generate a time delay, the delay is simply
T (secs) = R (ohms) x C (farads). Please note that this equation
only applies if the input logic voltage is matched to the 3.3V or 5V
threshold options. If the logic high amplitude is not equal to 3.3V
or 5V, then the equations in Equation 1 can be used for more
precise delay calculations.
VH  10V
High level of the logic signal into the RC
Vthres  63%  5V
Positive going threshold for 5V logic (B option)
VL  .3V
Low level of the logic signal into the RC
Rdel  100
C del  1nF
Timing values

 VL  Vthres
tdel   Rdel C del  ln
 1
V H  VL


tdel  34.788 ns
nominal delay time for this example
(EQ. 1)
In this example, the high logic voltage is 10V, the positive
threshold is 63% of 5V and the low level logic is 0.3V. Note the
rising edge propagation delay of the driver must be added to this
value.
The minimum recommended value of C is 100pF. The parasitic
capacitance of the PCB and any attached scope probes will
introduce significant delay errors if smaller values are used.
Larger values of C will further minimize errors.
Acceptable values of R are primarily effected by the source
resistance of the logic inputs. Generally, 100Ω resistors or larger are
usable.
Paralleling Outputs to Double the Peak Drive
Currents
The typical propagation matching of the ISL8963 and ISL89164
is less than 1ns. The matching is so precise that carefully
matched and calibrated scopes probes and scope channels must
be used to make this measurement. Because of this excellent
performance, these driver outputs can be safely paralleled to
double the current drive capacity. It is important that the INA and
INB inputs be connected together on the PCB with the shortest
possible trace. This is also required of OUTA and OUTB. Note that
the ISL89165 cannot be paralleled because of the
complementary logic.
FN7707.4
September 30, 2015
ISL89163, ISL89164, ISL89165
Power Dissipation of the Driver
Equation 2 shows calculating the power dissipation of the driver:
The power dissipation of the ISL89163, ISL89164, ISL89165 is
dominated by the losses associated with the gate charge of the
driven bridge FETs and the switching frequency. The internal bias
current also contributes to the total dissipation but is usually not
significant as compared to the gate charge losses.
R gate
P D = 2  Q c  freq  V GS  --------------------------------------------- + I DD  freq   V DD
R
+r
(EQ. 2)
where:
freq = Switching frequency,
12
Vgs GATE-SOURCE VOLTAGE (V)
DS  ON 
gate
VGS = VDD bias of the ISL89163, ISL89164, ISL89165
10
Qc = Gate charge for VGS
VDS = 64V
8
IDD(freq) = Bias current at the switching frequency (see Figure 10)
VDS = 40V
rDS(ON) = ON-resistance of the driver
6
Rgate = External gate resistance (if any).
Note that the gate power dissipation is proportionally shared with
the external gate resistor. Do not overlook the power dissipated
by the external gate resistor.
4
2
0
Typical Application Circuits
0
2
4
6
8
10
12
14
16
18
20
22
24
This drive circuit provides primary to secondary line isolation. A
controller, on the primary side, is the source of the SR control
signals OUTLLN and OUTLRN signals. The secondary side signals,
V1 and V2 are rectified by the dual diode, D9, to generate the
secondary side bias for U4. V1 and V3 are also inverted by Q100
and Q101 and the rising edges are delayed by R27/C10 and
R28/C9 respectively to generate the SR drive signals, LRN and
LLN. For more complete information on this SR drive circuit, and
other applications for the ISL89163, ISL89164, ISL89165, refer
to AN1603 “ISL6752/54EVAL1Z ZVS DC/DC Power Supply with
Synchronous Rectifiers User Guide”.
Qg, GATE CHARGE (nC)
FIGURE 19. MOSFET GATE CHARGE vs GATE VOLTAGE
Figure 19 illustrates how the gate charge varies with the gate
voltage in a typical power MOSFET. In this example, the total gate
charge for Vgs = 10V is 21.5nC when VDS = 40V. This is the
charge that a driver must source to turn-on the MOSFET and
must sink to turn-off the MOSFET.
PWM
L
R
L
Primary to Secondary side self
biasing, Isolated SR drive
VBIAS
/OUTLLN
R27
D9
ENABLE
V2
/OUTLRN
OUTLLN
V1
V1
C123
V2
U4
R28
R-SR
V4
EL7212
LLN
LRN
Q100
ISL89163
OUTLRN
LSR
Q101
U4
V3
T6
V3
Red dashed lines point out the
turn-on delay of the SRs when
PWM goes low
V4
LRN
C9
C10
LLN
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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ISL89163, ISL89164, ISL89165
General PCB Layout Guidelines
The AC performance of the ISL89163, ISL89164, ISL89165
depends significantly on the design of the PC board. The
following layout design guidelines are recommended to achieve
optimum performance:
• Place the driver as close as possible to the driven power FET.
• Understand where the switching power currents flow. The high
amplitude di/dt currents of the driven power FET will induce
significant voltage transients on the associated traces.
• Keep power loops as short as possible by paralleling the
source and return traces.
• Use planes where practical; they are usually more effective
than parallel traces.
• Avoid paralleling high amplitude di/dt traces with low level
signal lines. High di/dt will induce currents and consequently,
noise voltages in the low level signal lines.
• When practical, minimize impedances in low level signal
circuits. The noise, magnetically induced on a 10kΩ resistor, is
10x larger than the noise on a 1kΩ resistor.
• Be aware of magnetic fields emanating from transformers and
inductors. Gaps in the magnetic cores of these structures are
especially bad for emitting flux.
General EPAD Heatsinking
Considerations
The thermal pad is electrically connected to the GND supply
through the IC substrate. The EPAD of the ISL89163, ISL89164,
ISL89165 has two main functions: to provide a quiet GND for the
input threshold comparators and to provide heat sinking for the
IC. The EPAD must be connected to a ground plane and no
switching currents from the driven FET should pass through the
ground plane under the IC.
Figure 20 is a PCB layout example of how to use vias to remove
heat from the IC through the EPAD.
For maximum heatsinking, it is recommended that a ground
plane, connected to the EPAD, be added to both sides of the PCB.
A via array, within the area of the EPAD, will conduct heat from
the EPAD to the GND plane on the bottom layer. The number of
vias and the size of the GND planes required for adequate
heatsinking is determined by the power dissipated by the
ISL89163, ISL89164, ISL89165, the air flow and the maximum
temperature of the air around the IC.
EPAD GND
PLANE
EPAD GND
PLANE
• If you must have traces close to magnetic devices, align the
traces so that they are parallel to the flux lines to minimize
coupling.
• The use of low inductance components such as chip resistors
and chip capacitors is highly recommended.
• Use decoupling capacitors to reduce the influence of parasitic
inductance in the VDD and GND leads. To be effective, these
caps must also have the shortest possible conduction paths. If
vias are used, connect several paralleled vias to reduce the
inductance of the vias.
COMPONENT
LAYER
BOTTOM
LAYER
FIGURE 20. TYPICAL PCB PATTERN FOR THERMAL VIAS
• It may be necessary to add resistance to dampen resonating
parasitic circuits especially on OUTA and OUTB. If an external
gate resistor is unacceptable, then the layout must be
improved to minimize lead inductance.
• Keep high dv/dt nodes away from low level circuits. Guard
banding can be used to shunt away dv/dt injected currents
from sensitive circuits. This is especially true for control circuits
that source the input signals to the ISL89163, ISL89164,
ISL89165.
• Avoid having a signal ground plane under a high amplitude
dv/dt circuit. This will inject di/dt currents into the signal
ground paths.
• Do power dissipation and voltage drop calculations of the
power traces. Many PCB/CAD programs have built in tools for
calculation of trace resistance.
• Large power components (Power FETs, Electrolytic caps, power
resistors, etc.) will have internal parasitic inductance which
cannot be eliminated.
This must be accounted for in the PCB layout and circuit design.
• If you simulate your circuits, consider including parasitic
components especially parasitic inductance.
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September 30, 2015
ISL89163, ISL89164, ISL89165
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
Updated the Ordering Information table on page 3.
Replaced Products section with About Intersil section.
Updated Package Outline Drawing L8.3x3I to the latest revision. Changes are as follows:
September 30, 2015 FN7707.4
-Tiebar Note updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
February 22, 2012
(page 5) ENA and ENB added to the Input Range parameter
(page 6) Propagation delay testing parameters changed for option C
(page 6) Note 13 added
(page 7) Figure 3 modified to show different input thresholds for testing prop delays for option C
FN7707.3 (page 4) The startup sequence references for the VDD Undervoltage Lock-out parameters for Option C is now the
same as Options A and B. Options A, B, and C now have the same startup sequence.
(page 5) Note 9 is rewritten to be more precise.
(page 8) The old startup sequence for Option C has been deleted (formerly Figure 10)
(page 10) The old startup sequence description in the Functional Description Overview has been deleted.
January 9, 2012
(page 1) vertical part numbers in the right margin are deleted to conform to new datasheet standards.
(page 1) Last paragraph of the product description is changed to better describe the improved turn on characteristics.
(page 1) features list is reduced in size to 8 features. Some features are reworded to improve readability.
(page 1) a reference to a non-existent application note is deleted from the Related Literature section.
(page 2) pin configuration pictures are redrawn and relabeled for readability.
(page 2) some pins description names are changed to corollate to the pin name in the pin configuration pictures.
Some descriptions are also corrected. The truth table associated with the pin descriptions is expanded to include the
logic performance of the under-voltage. (these revisions are not a change to function).
FN7707.2 (page 4) note and figure references are added to the VDD Under-voltage lock-out parameter
for options A, B, and C
(page 5) note 12 is revised to more clearly describe the turn-on characteristics of options A, B, and C.
(page 6) no load test conditions added to the rising and falling propagation matching parameters.
(page 8) figures 7 and 8 added to clearly define the startup characteristics
(page 10) the last paragraph of the Functional Description overview is replaced by 3 paragraphs to more clearly
describe the under voltage and turn-on and turn-off characteristics.
(page 11). A new section is added to the application information describing how the drivers outputs can be paralleled.
(pages 1..13) various minor corrections to text for grammar and spelling.
August 26, 2011
(page 5) Note 12 revised from 200µs to 400µs
(page 4) The Operating Junction Temp Range in the “Thermal Information” was revised to read
FN7707.1 “Maximum Operating Junction Temp Range....-40°C to +150°C” from “-40°C to +125°C”
Updated POD M8.15D by converting to new POD format. Removed table of dimensions and moved dimensions onto
drawing. Added land pattern.
October 12, 2010
FN7707.0 Initial Release
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For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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FN7707.4
September 30, 2015
ISL89163, ISL89164, ISL89165
Package Outline Drawing
L8.3x3I
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 2 5/15
2X 1.950
3.00
B
0.15
8
5
3.00
(4X)
6X 0.65
A
1.64 +0.10/ - 0.15
6
PIN 1
INDEX AREA
4
8X 0.30
8X 0.400 ± 0.10
TOP VIEW
6
PIN #1 INDEX AREA
1
4
0.10 M C A B
2.38
+0.10/ - 0.15
BOTTOM VIEW
SEE DETAIL "X"
( 2.38 )
( 1.95)
0.10 C
Max 0.80
C
0.08 C
SIDE VIEW
( 8X 0.60)
(1.64)
( 2.80 )
PIN 1
C
0 . 2 REF
5
(6x 0.65)
0 . 00 MIN.
0 . 05 MAX.
( 8 X 0.30)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
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FN7707.4
September 30, 2015
ISL89163, ISL89164, ISL89165
Package Outline Drawing
M8.15D
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD PLASTIC PACKAGE
Rev 1, 3/11
8
INDEX
6.20 (0.244)
5.84 (0.230)
AREA
DETAIL "A"
1.27 (0.050)
0.41 (0.016)
3.99 (0.157)
3.81 (0.150)
1
2
0.50 (0.02)
x 45°
0.25 (0.01)
3
TOP VIEW
8°
0°
0.25 (0.010)
0.19 (0.008)
SEATING PLANE
1.72 (0.067)
1.52 (0.059)
2.25
(0.089)
-C-
0.25 (0.010)
0.10 (0.004)
1.27 (0.050)
0.46 (0.019)
0.36 (0.014)
1
2
SIDE VIEW “A
3
1
2
4
3
1.95
(0.077)
8
3.25 (0.128)
4.98 (0.196)
4.80 (0.189)
SIDE VIEW “B”
7
0.60 (0.023)
1.27 (0.050)
6
5
5.45 (0.214)
2.50 (0.099)
2.00 (0.078)
8
NOTES:
1. Dimensions are in millimeters. Dimensions in ( ) for reference only.
2. Dimensioning and tolerancing per ASME-Y14.5M-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05.
4. Dimension does not include interlead flash or protrusions. Interlead flash
or protrusions shall not exceed 0.25mm per side.
5. The Pin 1 identifier may be either a mold or a mark feature.
6. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
3.50 (0.137)
3.00 (0.118)
BOTTOM VIEW
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TYPICAL RECOMMENDED LAND PATTERN
15
FN7707.4
September 30, 2015
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