an1399

ISL9107EVAL1Z, ISL9108EVAL1Z Evaluation
Board Application Manual
®
Application Note
July 29, 2008
AN1399.0
Description
Specifications
The ISL9107EVAL1Z and ISL9108EVAL1Z provide the
complete evaluation kit for the ISL9107 and ISL9108, which
are1.6MHz switching frequency, low quiescent current, high
efficiency integrated step-down regulators. They are capable of
delivering up to 1.5A output current with an output voltage
range from 0.8V to ~VIN. The output voltage is set by two
voltage divider resistors of R2 and R3 on the board. The default
output voltage is set to be 1.6V on the evaluation board. In
addition to ISL9108, ISL9107 offers a typical 215ms
Power-Good (PG) timer when powered up. This timer output
can be reset by RSI.
Table 1 below shows the recommended operating conditions
for using ISL9107EVAL1Z, ISL9108EVAL1Z.
The complete ISL9107, ISL9108 regulator is located at the
center of the board. On the left side of the board are the
connectors for the input power source (VIN and GND). The
output connectors are located on the right side (VO and GND).
The other two test points are for the PG and RSI signals
respectively (for ISL9107 only), as labelled on the board. The
RSI input needs either be driven to a low or a high logic input
(Please refer to the ISL9107, ISL9108 datasheet, FN6612, for
more details regarding the RSI function). On the board, the
open-drain PG signal is pulled up to the VIN through a 100kΩ
resistor (R1). Jumper JP1 allows the user to enable or disable
the IC. Jumper JP2 is the mode selection input. Do not leave
the EN and the MODE signal floating. The evaluation board
also offers one oscilloscope probe tip connector connected to
SW pin to minimize the switching noise during the evaluation.
The evaluation board schematic, layout and bill-of-materials
(BOM) can be found at the end of this application note.
Ordering Information
• ISL9108EVAL1Z - Evaluation Board for ISL9108
Features
• A Complete Evaluation Platform for ISL9107and ISL9108
• Convenient Jumpers for Enable/Disable, Operation Mode
Selection
• 2.7V to 5.5V Supply Voltage
• 1.5A Output Current
• 17µA Quiescent Current in Skip (Low IQ) Mode
PARAMETER
Input Voltage
Output Voltage (Note)
Maximum Output Current
MIN
TYP
MAX
UNIT
2.7
-
5.5
V
-
1.6
-
V
1.5
-
-
A
NOTE: The output voltage can be set to other values by changing
the R2, R3 values, VOUT = 0.8V*(1+R2/R3). Refer to ISL9107,
ISL9108 datasheet for some recommended R2, R3 and C3 values for
different output voltages.
Recommended Equipment
The following instruments are recommended for testing:
• DC Power Supply, 5V/3A
• Electronic loads capable of sinking current up to 4A
• Multimeters
• Function generator
• Oscilloscope
Evaluation Board Setup
The following are recommended steps for setting up the
ISL9107EVAL1Z and ISL9108EVAL1Z evaluation boards:
1. Connect Jumper JP1 at the position of “Enable” to enable
the device. Connect JP1 at the position of “Disable“ to
disable the device.
2. Connect Jumper JP2 either at the position of “SKIP” or
“PWM”. With JP2 connected at the position of “SKIP”, the
device enters skip mode under light load condition; with
JP2 connected at the position of “PWM”, the device
always operates under PWM mode regardless of the load
condition.
• ISL9107EVAL1Z - Evaluation Board for ISL9107
• Integrated Synchronous Buck Regulator with High
Efficiency
TABLE 1. RECOMMENDED OPERATING CONDITIONS
3. For ISL9107EVAL1Z, connect the RSI input to either
ground or VIN. Please refer to the ISL9107, ISL9108
datasheet, FN6612, for more details regarding the
function of RSI.
4. Connect DC power supply between VIN and GND
connectors on board. Make sure the power supply has
enough supply current capability. The absolute maximum
rating for VIN pin is 6.5V and the recommended
maximum input voltage applied on VIN is up to 5.5V.
5. Connect the output to a load (resistor or electronic load).
6. Turn on the input power supply and start the evaluation.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1399
TP1
SW
VDD
U1
1
VIN
C1
2
100k R1
10µF/6.3V
1
JP3
2
3
4
VDD
SW
EN
GND
PG
FB
MODE
RSI
8
7
6
L1
J4 Vo
2.2µH
C2
R2
100k
C3
220pF
10µF/6.3V
5
R3
100k
1
ISL9107/ISL9108
3
J3 PG
(ISL9107 ONLY)
J5 GND
2
2
JP1
3
JP2
1
J1 VIN
J2 GND
2
1
J6 RSI
(ISL9107 ONLY)
JP4
J3, J6, JP3 AND JP4 ARE ONLY POPULATED FOR ISL9107EVAL1Z.
FOR ISL9108EVAL1Z, THESE SHOULD BE UN-POPULATED ON THE BOARD.
FIGURE 1. ISL9107EVAL1Z, ISL9108EVAL1Z SCHEMATIC
ISL9107EVAL1Z and ISL9108EVAL1Z Bill of Materials (BOM)
ITEM QTY
REFERENCE
PART DESCRIPTION
PCB
FOOTPRINT
8 Ld (2x3)
DFN
1
1
U1
ISL9107 for ISL9107EVAL1Z and ISL9108 for
ISL9108EVAL1Z
2
1
C1
Capacitor, SMD, 10µF/6.3V, 10%, X5R
3
1
C2
4
1
C3
5
3
R1, R2, R3
6
1
L1
7
6
VIN, VO, PG, RSI,
GND (x2)
8
1
TP1
9
2
10
2
PART NUMBER
VENDOR
ISL9107 or ISL9108
Intersil
0805
GRM21BR60J106KE19L
Murata
Capacitor, SMD, 10µF/6.3V, 10%, X5R
0805
GRM21BR60J106KE19L
Murata
Capacitor, SMD, 220pF/50V, 10%, X7R
0603
GRM188R71H221KA01D Murata
Resistor, SMD, 100kΩ, 1%, 0.1W
0603
RC0603FR-07100KL
Yageo
3.8x3.8
CDRH3D17/SNP-2R2
Sumida
Inductor, 2.2µH
Turrent Terminal Pin. J3 (PG) and J6 (RSI) are
only populated on ISL9107EVAL1Z.
-
3156-1-00-15-00-00-08-0
Mill-Max
Scope Probe Test Point
-
131503100
Tektronix
JP1, JP2
Connect Header, 1X3
-
68000-236-1X3
BERG/FCI
JP3, JP4
Connect Header, 1X2. Only populated for
ISL9107EVAL1Z.
-
68000-236-1x2
BERG/FCI
2
AN1399.0
July 29, 2008
Application Note 1399
PCB Layout
ISL910XEVAL1Z
REV A
J1 VIN
SW
TP1
JP1
J4 VO
L1
ON
C1
J2 GND
OFF
C3
R2
C3
U1
R3
JP2
JP4
JP3
R1
SKIP
J6 RSI
J3 PG
PWM
(ISL9107 ONLY)
J5 GND
CALL 1-888-INTERSIL
(ISL9107 ONLY)
FIGURE 2. SILK LAYER
FIGURE 3. TOP LAYER
FIGURE 4. BOTTOM LAYER (Mirrored)
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
3
AN1399.0
July 29, 2008
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