Application Note 1500 Author: Tu Bui ISL8500EVAL2Z 2A Negative Output Buck-Boost Converter Description The ISL8500EVAL2Z REV A kit is intended for use by individuals with requirements for Point-of-Load applications sourcing from 9V to 14V. The ISL8500EVAL2Z evaluation board is used to demonstrate the performance of the ISL8500 standard buck-boost regulator. The ISL8500 is offered in a 4mmx3mm 12 Ld DFN package with 1mm maximum height. The complete converter occupies less than 0.385in2 area. Features • Standard Buck Controller with Integrated Switching Power MOSFET • One electronic load capable of sinking current up to 5A • Digital Multimeters (DMMs) • 100MHz quad-trace oscilloscope • Signal generator Quick Set-up Guide 1. Ensure that the circuit is correctly connected to the supply and loads prior to applying any power. 2. Connect the bias supply to VIN, the plus terminal to TP1 (VIN) and the negative return to TP2 (GND). 3. Verify that SW1 is on ENABLE. • Integrated Boot Diode 4. Turn on the power supply. • Input Voltage Range - Variable 9V to14V 5. Verify the PG is on and the output voltage is 2.5V for VOUT(TP3). • PWM Output Voltage Adjustable from -12.6V to -0.6V with Continuous Output Current up to 2A • Voltage Mode Control with Voltage Feed Forward • Fixed 500kHz Switching Frequency • Externally Adjustable Soft-Start Time • Output Undervoltage Protection • PGOOD Output Evaluating the Other Output Voltage The ISL8500EVAL kit outputs are preset to -12V; however, it can be programmed using resistor dividers using Equation 1: R 2 ⋅ 0.6V R 4 = ------------------------------------V OUT – 0.6V (EQ. 1) The output voltage programming resistor R2 will depend on on the feedback resistor R1, as referred to in Figure 1. The value of R1 is typically between 1kΩ and 10kΩ. If the output voltage desired is 0.6V, then R2 is left opened. • Overcurrent Protection • Thermal Overload Protection • Internal 5V LDO regulator Applications R2 • General Purpose + - • Hand-Held Instruments EA What’s Inside R4 0.6V REFERENCE The Evaluation Board Kit contains the following materials: -VOUT FIGURE 1. EXTERNAL RESISTOR DIVIDER • The ISL8500 EVAL2Z REV A Board • The ISL8500 Datasheet TABLE 1. SWITCH 1 SETTINGS • This EVAL KIT Document SW1 Recommended Equipment 1 ENABLE SW1 OPERATING MODE Enable or disable the buck controller The following materials are recommended to perform testing: • 0V to 15V power supply with at least 5A source current capability, battery, notebook AC adapter November 19, 2009 AN1500.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Schematic C1 2 1 R2 0.01UF C2 20K C3 VIN 1 1 13 C20 220UF 1 0.1UF 2 4 VDD SP2 EP C8 -VOUT 2 -VOUT TP13 1 100K R12 VDD OFF -VOUT EN 3 SW1 1 2 TP3 1 TP4 1 4 32 SP1 1 -VOUT ISL8500IRZ ON C21 BOOT 1 100UF GND 8 1 BOOT 2 2 PG C9 2 67 PHASE 1 9 10UF 5 EN L1 PHASE 2 4 10 R30 VIN OPEN POPULATE R30 IF VIN <6V ONLY Application Note 1500 EN PG VIN PHASE SS C12 1UF -VOUT COMP -VOUT 11 47UF C13 3 1 12 3 C4 VIN 1 2 FB TP2 D1 2 -VOUT 2 GND 1 2 1 COMP TP1 1 1 U1 2 FB 3 -VOUT PG 2N7002 C10 2 1.05K TP16 1 2200PF R4 1 Q4 2 1 D3 1 698 10UF R3 150PF 10UF C11 5.11K 1UF 10K R21 R1 2 R20 2.43K VDD AN1500.0 November 19, 2009 Application Note 1500 ISL8500EVAL2Z Bill of Materials PART NUMBER QTY REFERENCE UNITS DESIGNATOR ISL8500EVAL2ZREVAPCB 1 ea H1044-00103-50V10-T 1 ea H1065-00106-25V10-T 2 ea DNP 0 ea H1082-00476-16V20-T 1 ea DESCRIPTION MFTR MANUFACTURER PART PWB-PCB, ISL8500EVAL2Z, REVA, ROHS TITAN ISL8500EVAL2ZREVAPCB C1 CAP, SMD, 0402, 10nF, 50V, 10%, X7R, ROHS PANASONIC ECJ-0EB1H103K C10, C11 CAP, SMD, 1206, 10µF, 25V, 10%, X5R, ROHS VENKEL C1206X5R250-106KNE TDK C3225X5R1C476M PANASONIC ECJ-4YB1E476M AVX 1210YD476MAT C13, C20, C21 DO NOT POPULATE OR PURCHASE C12 CAP, SMD, 1210, 47µF, 16V, 20%, X5R, ROHS H1044-00151-50V5-T 1 ea C2 CAP, SMD, 0402, 150pF, 50V, 5%, NPO, ROHS VENKEL C0402COG500-151JNE H1044-00222-50V10-T 1 ea C3 CAP, SMD, 0402, 2200pF, 50V, 10%, X7R, ROHS PANASONIC ECJ-0EB1H222K VENKEL C0402X74500-471KNE CAP, SMD, 0603, 1µF, 6.3V, 10%, X5R, ROHS PANASONIC ECJ1VB0J105K H1045-00105-6R3V10-T 2 ea C4,C8 C1608X7R1H104K-T 1 ea C9 CAPACITOR, SMD, 0603, 0.10µF, 50V, 10%, X7R TDK C1608X7R1H104K B340LB-13-F-T 1 ea D1 DIODE-SCHOTTKY SMD, SMB, 2P, 40V, 3A LOW VF, ROHS DIODES INC. B340LB-13-F DNP 0 ea D3 DO NOT POPULATE OR PURCHASE IHLP2525CZRZ220M01 1 ea L1 COIL-PWR INDUCTOR, SMD, 6.9x6.5, 22µH, 20%, 2.5A, ROHS VISHAY IHLP2525CZRZ220M01 DNP 0 ea Q4 DO NOT POPULATE OR PURCHASE H2510-05111-1/16W1-T 1 ea R1 RES, SMD, 0402, 5.11k, 1/16W, 1%, TF, ROHS PANASONIC ERJ-2RKF5111X VENKEL CR0402-16W-5111FT RES, SMD, 0402, 100k, 1/16W, 1%, TF, ROHS PANASONIC ERJ2RKF1003 RES, SMD, 0402, 20k, 1/16W, 1%, TF, ROHS PANASONIC ERJ-2RKF2002 VENKEL CR0402-16W-2002FT H2510-01003-1/16W1-T 1 ea R12 H2510-02002-1/16W1-T 1 ea R2 DNP 0 ea R20 DO NOT POPULATE OR PURCHASE H2511-01002-1/10W1-T 1 ea R21 RES, SMD, 0603, 10k, 1/10W, 1%, TF, ROHS KOA RK73H1JT1002F VENKEL CR0603-10W-1002FT RES, SMD, 0402, 698Ω, 1/16W, 1%, TF, ROHS PANASONIC ERJ-2RKF6980X VENKEL CR0402-16W-6980-FT H2510-06980-1/16W1-T 1 3 ea R3 AN1500.0 November 19, 2009 Application Note 1500 ISL8500EVAL2Z Bill of Materials (Continued) PART NUMBER QTY REFERENCE UNITS DESIGNATOR H2511-DNP 0 ea R30 H2510-01051-1/16W1-T 1 ea R4 DESCRIPTION MFTR MANUFACTURER PART RES, SMD, 0603, DNPPLACE HOLDER, ROHS RES, SMD, 0402, 1.05k, 1/16W, 1%, TF, ROHS VENKEL CR0402-16W-1051FT PANASONIC ERJ-2RKF1051X VISHAY/DALE CRCW04021K05FKED 131-4353-00 2 ea SP1, SP2 CONN-SCOPE PROBE TEST PT, COMPACT, PCB MNT, ROHS TEKTRONIX 131-4353-00 GT11MSCBE-T 1 ea SW1 SWITCH-TOGGLE, SMD, ULTRAMINI, 1P, SPST MINI C&K COMPONENTS GT11MSCKE 5002 2 ea TP13, TP16 CONN-MINI TEST POINT, VERTICAL, WHITE, ROHS KEYSTONE 5002 1514-2 4 ea TP1-TP4 CONN-TURRET, TERMINAL POST, TH, ROHS KEYSTONE 1514-2 ISL8500IRZ 1 ea U1 IC-2A BUCK REGULATOR, 12P, DFN, 4x3, ROHS INTERSIL ISL8500IRZ 4 AN1500.0 November 19, 2009 Application Note 1500 ISL8500EVAL2Z Board Layout FIGURE 2. TOP COMPONENTS 5 AN1500.0 November 19, 2009 Application Note 1500 ISL8500EVAL2Z Board Layout (Continued) FIGURE 3. TOP LAYER ETCH 6 AN1500.0 November 19, 2009 Application Note 1500 ISL8500EVAL2Z Board Layout (Continued) FIGURE 4. 2nd LAYER ETCH 7 AN1500.0 November 19, 2009 Application Note 1500 ISL8500EVAL2Z Board Layout (Continued) FIGURE 5. 3rd LAYER ETCH 8 AN1500.0 November 19, 2009 Application Note 1500 ISL8500EVAL2Z Board Layout (Continued) FIGURE 6. BOTTOM LAYER ETCH (Mirrored) 9 AN1500.0 November 19, 2009 Application Note 1500 Theory of Operation The ISL8500 in this configuration is a non-sysnchronous positive to negative switching regulator which can handle input voltages above, below, or equal to the absolute value of the output. The ISL8500EVAL2Z circuit design is optimized for 12V input to -12V output applications. The regulator operates at 500kHz fixed switching frequency, FS, under heavy load conditions to allow smaller external inductors and capacitors to be used for minimal printed-circuit board (PCB) area. At light load, the regulator reduces the switching frequency by skipping pulses to maintain regulation and increase efficiency. The principle of operation is shown in Figure 7 and uses the energy storage of the inductor L during the on period, and then transfers the energy through the free wheeling diode, D, to the output. When the HS MOSFET switch turns on, the diode is reverse biased, and the inductor current will ramp up. When the switch is off, as shown in Figure 8, the inductor will reverse its polarity to maintain its peak current. The forward biased diode and the stored energy of the inductor gets transferred to the load and the output capacitor. Since the voltage of the inductor is negative with respect to GND, the output voltage across the capacitor will be negative. This type of converter can step up and down the magnitude of the input voltage. Therefore, this circuit is called a buck-boost converter. For steady state operation, the volt-second of the inductor must equal, DVL= (1-D)VL. VL is equal to VIN during the ON time and VL is equal to -VOUT during the OFF time. Therefore, the DC steady state transfer is VOUT/VIN = -D/(1-D). Figure 9 is the voltage and current waveforms. + + VHS - VL + VHS - + VL - L VIN D CIN PWM + VD COUT - -VOUT DURING THE OFF TIME FIGURE 8. VOLTAGE ACROSS THE ELEMENT DURING THE OFF TIME Equation 3 for Figure 8: VL = V OUT (EQ. 3) V D ≈ 0V V HS = V IN + V OUT VIN VL 1-D D VOUT ILAVE IL VIN+VOUT VHS IHS L VIN+VOUT VIN D CIN + VD PWM COUT VD ID -VOUT DURING THE ON TIME FIGURE 7. VOLTAGE ACROSS THE ELEMENT DURING THE ON TIME IN V OUT D = -------------------------------V IN + V D I LAVE = I OUT ⎛ 1 + -------------⎞ ⎝ 1 – D⎠ IN VD = V Equation 4 for Figure 9: OUT Equation 2 for Figure 7: VL = V FIGURE 9. SIMPLIFICATION OF THE BUCK BOOST CONVERTER (EQ. 2) + V OUT ΔI L = V (EQ. 4) D ⋅ --------------- IN L ⋅ F S V HS ≈ 0V 10 AN1500.0 November 19, 2009 Application Note 1500 Component Selection Use 47µF 16V ceramic for this example. This section will detail the calculation and selection of the components. Calculations are done in continuous operation mode. Input Capacitor Selection Inductor Selection From Equation 3 and ignoring the diode VD and rDS(ON) of the FET, the duty cycle is shown in Equation 5. V OUT D ≈ ----------------------------------V IN + V OUT (EQ. 5) For this example, D is 12V/(12V+12V) = 0.5. The average inductor current is shown in Equation 6. 1 D I LAVE = I OUT ⎛ 1 + -------------⎞ = I OUT ⎛ -------------⎞ ⎝ 1 – D⎠ ⎝ 1 – D⎠ (EQ. 6) The higher or lower inductor value can be used to optimize the total converter system performance. For example, for higher output voltage application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. It is recommended to set the ripple inductor current approximately 20% to 30% of the maximum average inductor current for optimized performance. The inductor ripple current can be expressed as shown in Equation 7: V IN ⋅ V OUT L = --------------------------------------------------------------------------------( V IN + V OUT ) ( 0.3 ⋅ I LAVE ) ⋅ f S Diode Selection The free wheeling diode had to be able to handle the maximum voltage and current stress. The voltage stress is equal to VIN plus VOUT and the current stress is ILAVE+0.5ΔIL. The power dissipation is shown in Equation 8. (EQ. 8) where VD is the forward voltage of the diode. This value is typically 0.5V for 3A Schottky diode. A 30V or 40V 3A, B340LB is a good choice. Output Capacitor Selection The output capacitor has to be selected based on its RESR value, and the capacitance must be high enough to hold the charges for the load during the off time. The output ripple is shown in Equation 9. ΔV OUT = R ESR ⋅ ( I LAVE + 0.5ΔI L ) (EQ. 9) where ΔVOUT is the desired output ripple. The minimum output capacitor value for tis output ripple is shown in Equation 10. I OUT ⋅ D C OUT = -----------------------------f S ⋅ ΔV OUT (EQ.10) 11 Compensation Selection The buck-boost typology is difficult to stabilize because it has a right-half-plane zero in its control to output transfer function. The small signal AC model of the buck-boost power section in relationship to d(s) is shown in Figure 10. 1-D : -D SL --------------------2 (1 – D) VOUT I 1 -------SC + - Vs (EQ. 7) where fs is the switching frequency. The inductor’s saturation current rating needs to be at least larger than the peak current. The ISL8500 protects the typical peak current 3.1A. The saturation current needs be over 4A for maximum output current application. For IOUT of 1A, the inductor L is 24µH. Then use 22µH. P D = ( I LAVE + 0.5ΔI L ) ⋅ V D ⋅ ( 1 + D ) The main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. Two 10µF X5R or X7R ceramic capacitors are a good starting point for the input capacitor selection. One capacitor connecting from VIN to -VOUT and another one connecting from VIN to GND. R ˆ – V OUT SL ⋅ D V S = ------------------- ⎛ 1 – ------------------------------⎞ dˆ ( s ) ⎝ ⎠ 2 2 (1 – D) ⋅ R D FIGURE 10. SMALL SIGNAL AC MODEL To solve the power transfer function, see Equation 11. SLI ⎛ 1 – ------------------------------------------------------⎞ V IN – V OUT ⎜ ( 1 – D ) ( V IN – V OUT )⎟ Vˆ OUT ( S ) ⎜ - = – -------------------------------- -----------------------------------------------------------------⎟ H ( S ) = -----------------------⎜ ⎟ 2 1–D dˆ ( S ) S LC - ⎟ SL - -------------------⎜ 1 + ------------------------+ ⎝ 2 2⎠ (1 – D) R (1 – D) (EQ.11) The salent characteristics are shown in Equation 12. V OUT V IN – V OUT 12V H ( 0 ) = – -------------------------------- = ----------------------- = --------------------- = 48 D(1 – D) 0.5 ⋅ 0.5 1–D H(0)=33.8dB 2 ( 1 – D ) ( V IN – V OUT ) (1 – D) R ω Z = ------------------------------------------------------- = -------------------------LI DL 2 3 0.5 ⋅ 12Ω ω Z = --------------------------- = 136 ×10 22μH ⋅ 1A , this is RHPZ 3 F Z = 43.4 ×10 Hz (EQ.12) C 44μF Q = ( 1 – D )R ---- = 0.5 ⋅ 12Ω ⋅ --------------- = 8.77 L 22μH Q=18.9dB 3 (1 – D) 0.5 ω LC = ------------------ = -------------------------------------- = 12 × 10 LC 22μH ⋅ 47μF FLC=2.4kHz AN1500.0 November 19, 2009 Application Note 1500 The compensation network consists of the error amplifier (internal to the ISL8500) and the impedance networks. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. 70 GAIN (dB) 35 From the transfer function, there is a right-half-plane-zero. Therefore, it is highly recommended to insure that the crossover frequency, Fc, is well before the Fz. Figures 11 and 12 are the bode plot of the gain and phase for H(S). 0 35 70 10 1 .10 100 3 1 .10 4 1 .10 5 1 .10 6 FREQUENCY (Hz) FIGURE 11. GAIN ON H(S) IN dB Phase margin is the difference between the closed loop phase at f0dB and 180°. Equation 13 relates the compensation network’s poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and C3) in Figure 14. Use the following guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R2/R1) for converter bandwidth (~30% FZ). 2. Place 1ST Zero Below Filter’s Double Pole (~30% FLC). 200 3. Place 2ND Zero at Filter’s Double Pole. 5. Place 2ND Pole at the 2.5x of RHP Zero. 100 6. Check Gain against Error Amplifier’s Open-Loop Gain. Estimate Phase Margin - Repeat if Necessary. 0 Compensation Break Frequency Equations 100 10 1 . 10 100 3 1 .10 4 1 .10 5 1 .10 1 F Z1 = -----------------------------------2π x R 2 x C 2 1 F P1 = --------------------------------------------------------⎛ C 1 x C 2⎞ 2π x R 2 x ⎜ ----------------------⎟ ⎝ C1 + C2 ⎠ 1 F Z2 = ------------------------------------------------------2π x ( R 1 + R 3 ) x C 3 1 F P2 = -----------------------------------2π x R 3 x C 3 6 FREQUENCY (Hz) FIGURE 12. PHASE OF H(S) IN ° ZFB C1 VOUT Z IN C2 R2 C3 60 R3 45 R1 COMP - FB + (EQ. 13) Figures 14 and 15 shows the bode plot of the gain and phase for the closed loop response. R4 GAIN (dB) PHASE (°) 4. Place 1ST Pole at half the Switching Frequency. 30 15 0 ISL8500 REFERENCE 15 FIGURE 13. DETAILED COMPENSATION NETWORK 30 100 1 .10 3 4 1 .10 1 .10 5 1 .10 6 FREQUENCY (Hz) FIGURE 14. GAIN OF CLOSED LOOP IN dB 12 AN1500.0 November 19, 2009 Application Note 1500 The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope, and a phase margin greater than 40°. Include worst case component variations when determining phase margin. 180 PHASE (°) 150 120 90 60 30 0 100 3 1 .10 4 1 .10 5 1 .10 6 1 .10 FREQUENCY (Hz) FIGURE 15. PHASE OF CLOSED LOOP IN ° Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 13 AN1500.0 November 19, 2009 Application Note 1500 Typical Performace Curves TA = +25°C, Unless Otherwise Specified, operating conditions are: TA = +25°C, VIN = 12V, EN = VDD, L = 22µH, C12 = 100µF, C10 = C11 = 10µF, IOUT = 0A to 1A. 100 4.0 90 3.5 POWER DISSIPATION (Ω) EFFICENCY (%) 80 70 10V VIN 60 12V VIN 14V VIN 50 40 30 10V VIN 12V VIN 3.0 2.5 2.0 1.5 1.0 0.5 20 0.0 0.2 0.4 0.6 0.8 14V VIN 0.0 0.0 1.0 0.2 OUTPUT LOAD (A) 12.290 12.28 12.285 12.28 12.280 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 12.29 12.27 14V VIN 10V VIN 12.26 12.26 12V VIN 0.4 0.6 1.0 12.270 0.5A 12.265 0A 12.260 1A 12.255 0.2 0.8 12.275 ISL8500 VOUT = 12V 12.25 12.25 0.0 0.6 FIGURE 17. POWER DISSIPATION vs LOAD FIGURE 16. EFFICIENCY vs LOAD 12.27 0.4 OUTPUT LOAD (A) 0.8 1.0 12.250 5 7 OUTPUT LOAD (A) FIGURE 18. VOUT REGULATION vs LOAD PHASE 10V/DIV 9 11 INPUT VOLTAGE (V) 13 15 FIGURE 19. OUTPUT VOLTAGE REGULATION vs VIN PHASE 10V/DIV VOUT RIPPLE 20mV/DIV VOUT RIPPLE 20mV/DIV IL 0.5A/DIV IL 1A/DIV FIGURE 20. STEADY STATE OPERATION AT NO LOAD 14 FIGURE 21. STEADY STATE OPERATION AT FULL LOAD AN1500.0 November 19, 2009 Application Note 1500 Typical Performace Curves TA = +25°C, Unless Otherwise Specified, operating conditions are: TA = +25°C, VIN = 12V, EN = VDD, L = 22µH, C12 = 100µF, C10 = C11 = 10µF, IOUT = 0A to 1A. (Continued) PHASE 10V/DIV EN 0.5V/DIV VOUT RIPPLE 100mV/DIV VOUT 0.5V/DIV IL 1A/DIV IL 1A/DIV FIGURE 23. SOFT-START AT NO LOAD FIGURE 22. LOAD TRANSIENT VOUT 0.5V/DIV EN 0.5V/DIV EN 0.5V/DIV IL 1A/DIV VOUT 0.5V/DIV IL 1A/DIV FIGURE 24. SOFT-START AT FULL LOAD PHASE 10V/DIV FIGURE 25. SHUT-DOWN CIRCUIT PHASE 10V/DIV VOUT 5V/DIV VOUT 0.5V/DIV IL 1A/DIV FIGURE 26. OUTPUT SHORT CIRCUIT 15 IL 1A/DIV FIGURE 27. OUTPUT SHORT CIRCUIT RECOVERY AN1500.0 November 19, 2009

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