DATASHEET

ISL8499
®
Data Sheet
February 5, 2008
Ultra Low ON-Resistance, +1.65V to +4.5V,
Single Supply, Quad SPDT (Dual DPDT)
Analog Switch
The Intersil ISL8499 device is a low ON-Resistance, low
voltage, bidirectional, Quad SPDT (Dual DPDT) analog
switch designed to operate from a single +1.65V to +4.5V
supply. Targeted applications include battery powered
equipment that benefit from low rON (0.24Ω) and fast
switching speeds (tON = 15ns, tOFF = 13ns). The digital logic
input is 1.8V logic-compatible when using a single +3V supply.
With a supply voltage of 4.2V and logic high voltage of 2.85V
at both logic inputs, the part draws only 10µA max of ICC
current.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL8499 is offered in small form factor packages, alleviating
board space limitations.
The ISL8499 consists of four SPDT switches. It is configured
as a dual double-pole/double-throw (DPDT) device with two
logic control inputs that control two SPDT switches each. The
configuration can be used as a dual differential 2-to-1
multiplexer/demultiplexer. The ISL8499 is pin compatible with
the STG3699 and DG2799.
TABLE 1. FEATURES AT A GLANCE
FN6111.3
Features
• Drop in Replacement for the STG3699 and DG2799
• ON-Resistance (rON)
- V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.24Ω
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.26Ω
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.45Ω
• rON Matching between Channels . . . . . . . . . . . . . . . . . 0.04Ω
• rON Flatness Across Signal Range . . . . . . . . . . . . . . . 0.05Ω
• Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V
• Low Power Consumption (PD) . . . . . . . . . . . . . . . . . <0.2µW
• Fast Switching Action (V+ = +4.3V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns
• Guaranteed Break-Before-Make
• 1.8V Logic Compatible (+3V supply)
• Low ICC Current when VinH is not at the V+ Rail
• Available in 16 Ld 3x3 TQFN, 16 Ld 3x3 QFN and
16 Ld TSSOP
• ESD HBM Rating
- COM Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9kV
- All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV
• Pb-Free Available (RoHS Compliant)
Applications
-
ISL8499
Number of Switches
4
SW
Quad SPDT (Dual DPDT)
4.3V rON
0.24Ω
4.3V tON/tOFF
15ns/13ns
3.0V rON
0.26Ω
3.0V tON/tOFF
21ns/17ns
1.8V rON
0.45Ω
1.8V tON/tOFF
51ns/43ns
Packages
16 Ld 3x3 TQFN, 16 Ld 3x3 QFN,
16 Ld TSSOP
• Battery Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8499
Pinouts
Ordering Information
(Note 1)
ISL8499
(16 LD QFN TSSOP)
TOP VIEW
PART
PART NUMBER MARKING
16 V+
NO1 1
14 COM4
NC1 3
IN1-2 4
13 NO4
NO2 5
12 IN3-4
11 NC3
COM2 6
NC2 7
10 COM3
GND 8
9 NO3
COM1
NO1
V+
NC4
ISL8499
(16 LD 3X3 TQFN, 3X3 QFN)
TOP VIEW
16
15
14
13
NC1
1
12 COM4
IN1-2
2
11 NO4
NO2
3
10 IN3-4
COM2
4
9
PACKAGE
PKG.
DWG. #
ISL8499IR
499I
-40 to +85 16 Ld 3x3 QFN
L16.3x3
ISL8499IR-T*
499I
-40 to +85 16 Ld 3x3 QFN
Tape and Reel
L16.3x3
ISL8499IV
8499 IV
-40 to +85 16 Ld TSSOP
M16.173
ISL8499IV-T*
8499 IV
-40 to +85 16 Ld TSSOP
Tape and Reel
M16.173
ISL8499IRZ
(Note)
499Z
-40 to +85 16 Ld 3x3 QFN
(Pb-free)
L16.3x3
ISL8499IRZ-T*
(Note)
499Z
-40 to +85 16 Ld 3x3 QFN
Tape and Reel
(Pb-free)
L16.3x3
ISL8499IVZ
(Note)
8499 IVZ
-40 to +85 16 Ld TSSOP
(Pb-free)
M16.173
ISL8499IVZ-T*
(Note)
8499 IVZ
-40 to +85 16 Ld TSSOP
Tape and Reel
(Pb-free)
M16.173
ISL8499IRTZ
(Note)
99TZ
-40 to +85 16 Ld 3x3 TQFN L16.3x3A
(Pb-free)
ISL8499IRTZ-T* 99TZ
(Note)
-40 to +85 16 Ld 3x3 TQFN L16.3x3A
Tape and Reel
(Pb-free)
15 NC4
COM1 2
TEMP.
RANGE
(°C)
5
6
7
8
NC2
GND
NO3
COM3
*Please refer to TB347 for details on reel specifications
NC3
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach materials
and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which
is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
NOTE:
1. Switches Shown for Logic “0” Input.
Truth Table
LOGIC
NC SW
NO SW
0
ON
OFF
1
OFF
ON
NOTE:
Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.
Pin Descriptions
PIN
V+
FUNCTION
System Power Supply Input (+1.65V to +4.5V)
GND
Ground Connection
IN
Digital Control Input
COM
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
2
FN6111.3
February 5, 2008
ISL8499
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V
Input Voltages
NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA
ESD Ratings:
HBM COMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>9kV
HBM NOX, NCX, INX, V+, GND . . . . . . . . . . . . . . . . . . . . . . .>4kV
MM COMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
MM NOX, NCX, INX, V+, GND . . . . . . . . . . . . . . . . . . . . . . .>300V
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
θJC (°C/W)
TQFN and QFN Package (Notes 4, 5) .
70
10
TSSOP Package (Note 3) . . . . . . . . . .
150
N/A
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range
ISL8499IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications - 4.3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 6),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 7, 8)
TYP
MAX
(Notes 7, 8) UNITS
Full
0
-
V+
V
25
-
0.25
-
Ω
Full
-
0.28
-
Ω
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 5)
rON Matching Between Channels,
ΔrON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = Voltage at
max rON,(Note 11)
rON Flatness, RFLAT(ON)
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+,
(Note 9)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 4.5V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 4.5V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V,
3V, or Floating
25
-
0.04
-
Ω
Full
-
0.05
-
Ω
25
-
0.05
-
Ω
Full
-
0.05
-
Ω
25
-50
-
50
nA
Full
-150
-
150
nA
25
-50
-
50
nA
Full
-150
-
150
nA
25
-
15
25
ns
Full
-
-
30
ns
25
-
13
23
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω,
CL = 35pF, (See Figure 1, Note 10)
Turn-OFF Time, tOFF
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω,
CL = 35pF, (See Figure 1, Note 10)
Full
-
-
28
ns
Break-Before-Make Time Delay, tD
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω,
CL = 35pF, (See Figure 3, Note 10)
Full
2
3
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2)
25
-
-120
-
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 4)
25
-
68
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 6)
25
-
-98
-
dB
3
FN6111.3
February 5, 2008
ISL8499
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 6),
Unless Otherwise Specified (Continued)
TEMP
(°C)
MIN
(Notes 7, 8)
TYP
25
-
0.003
-
%
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
106
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
212
-
pF
Full
1.65
-
4.5
V
PARAMETER
TEST CONDITIONS
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VPP, RL = 600Ω
COM ON Capacitance, CCOM(ON)
MAX
(Notes 7, 8) UNITS
POWER SUPPLY CHARACTERISTICS
Power Supply Range
V+ = +4.5V, VIN = 0V or V+
Positive Supply Current, I+
V+ = +4.2V, VIN = 2.85V
Positive Supply Current, I+
25
-
-
0.09
μA
Full
-
-
1.4
μA
25
-
-
12
μA
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full
-
-
0.5
V
Input Voltage High, VINH
Full
1.6
-
-
V
Full
-0.5
-
0.5
μA
Input Current, IINH, IINL
V+ = 4.5V, VIN = 0V or V+, (Note 10)
NOTES:
6. VIN = input voltage to perform proper function.
7. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
8. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
9. Flatness is defined as the difference between maximum and minimum value of ON-Resistance over the specified analog signal range.
10. Limits established by characterization and are not production tested.
11. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value, between NC1 and NC2, NC3 and NC4 or between NO1 and NO2, NO3 and NO4.
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 6),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 7, 8)
TYP
MAX
(Notes 7, 8) UNITS
Full
0
-
V+
V
25
-
0.3
0.45
Ω
Full
-
-
0.6
Ω
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 5)
ON-Resistance, rON
rON Matching Between Channels,
ΔrON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at
max rON, (Note 11)
rON Flatness, rFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(Note 9)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V,
3V, or Floating
25
-
0.04
0.08
Ω
Full
-
-
0.09
Ω
25
-
0.06
0.15
Ω
Full
-
-
0.15
Ω
25
-
1.2
-
nA
Full
-
13
-
nA
25
-
1
-
nA
Full
-
35
-
nA
25
-
21
30
ns
Full
-
-
35
ns
25
-
17
27
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω,
CL = 35pF, (See Figure 1, Note 10)
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω,
CL = 35pF, (See Figure 1, Note 10)
Break-Before-Make Time Delay, tD
V+ = 3.3V, VNO or VNC = 1.5V, RL = 50Ω,
CL = 35pF, (See Figure 3, Note 10)
4
Full
-
-
32
ns
Full
2
3
-
ns
FN6111.3
February 5, 2008
ISL8499
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 6),
Unless Otherwise Specified (Continued)
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 7, 8)
TYP
MAX
(Notes 7, 8) UNITS
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2)
25
-
-82
-
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 4)
25
-
68
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 6)
25
-
-98
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω
25
-
0.003
-
%
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
106
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
212
-
pF
25
-
0.025
-
μA
Full
-
0.715
-
μA
Input Voltage Low, VINL
Full
-
-
0.5
V
Input Voltage High, VINH
Full
1.4
-
-
V
Full
-0.5
-
0.5
μA
COM ON Capacitance, CCOM(ON)
POWER SUPPLY CHARACTERISTICS
V+ = 3.6V, VIN = 0V or V+
Positive Supply Current, I+
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 3.6V, VIN = 0V or V+ (Note 10)
Electrical Specifications - 1.8V Supply
PARAMETER
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 6), Unless
Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 7, 8)
TYP
MAX
(Notes 7, 8) UNITS
Full
0
-
V+
V
25
-
0.45
0.8
Ω
Full
-
-
0.85
Ω
25
-
51
65
ns
Full
-
-
70
ns
25
-
43
58
ns
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 5)
ON-Resistance, rON
DYNAMIC CHARACTERISTICS
V+ = 1.65V, VNO or VNC = 1.0V, RL = 50Ω,
CL = 35pF, (See Figure 1, Note 10)
Turn-ON Time, tON
Turn-OFF Time, tOFF
V+ = 1.65V, VNO or VNC = 1.0V, RL = 50Ω,
CL = 35pF, (See Figure 1, Note 10)
Full
-
-
65
ns
Break-Before-Make Time Delay, tD
V+ = 2.0V, VNO or VNC = 1.0V, RL = 50Ω,
CL = 35pF, (See Figure 3, Note 10)
Full
3
8
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2
25
-
-44
-
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 4)
25
-
68
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 6)
25
-
-98
-
dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
106
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
212
-
pF
Input Voltage Low, VINL
Full
-
-
0.4
V
Input Voltage High, VINH
Full
1.0
-
-
V
Full
-0.5
-
0.5
μA
COM ON Capacitance, CCOM(ON)
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+ (Note 10)
5
FN6111.3
February 5, 2008
ISL8499
Test Circuits and Waveforms
V+
LOGIC
INPUT
V+
tr < 5ns
tf < 5ns
50%
0V
tOFF
SWITCH
INPUT
SWITCH
INPUT VNO
VOUT
VOUT
NO or NC
COM
IN
90%
SWITCH
OUTPUT
C
90%
LOGIC
INPUT
0V
CL
35pF
RL
50Ω
GND
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) ---------------------------R L + r ( ON )
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
SWITCH
OUTPUT
VOUT
RG
ΔVOUT
C
VOUT
COM
NO or NC
V+
LOGIC
INPUT
VG
ON
ON
GND
IN
CL
OFF
0V
LOGIC
INPUT
Q = ΔVOUT x CL
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
V+
LOGIC
INPUT
VNX
C
NO
RL
50Ω
IN
SWITCH
OUTPUT
VOUT
VOUT
COM
NC
0V
90%
LOGIC
INPUT
CL
35pF
GND
0V
tD
CL includes fixture and stray capacitance.
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
6
FN6111.3
February 5, 2008
ISL8499
Test Circuits and Waveforms (Continued)
V+
V+
C
C
rON = V1/100mA
SIGNAL
GENERATOR
NO or NC
NO or NC
VNX
IN
0V or V+
100mA
0V or V+
COM
COM
ANALYZER
IN
V1
GND
GND
RL
FIGURE 5. rON TEST CIRCUIT
FIGURE 4. OFF ISOLATION TEST CIRCUIT
V+
C
V+
C
SIGNAL
GENERATOR
NO or NC
COM
50Ω
NO or NC
IN1
IN
0V or V+
NC or NO
COM
ANALYZER
0V or V+
IMPEDANCE
ANALYZER
GND
COM
N.C.
GND
RL
FIGURE 6. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL8499 is a bidirectional, quad single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.65V to 4.5V supply with low
on-resistance (0.24Ω) and high speed operation
(tON = 15ns, tOFF = 13ns). The device is especially well
suited for portable battery powered equipment due to its low
operating supply voltage (1.65V), low power consumption
(2.7µW max), low leakage currents (150nA max), and the tiny
TQFN, QFN and TSSOP packages. The ultra low
ON-Resistance and rON flatness provide very low insertion
loss and distortion to applications that require signal
reproduction.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
7
FIGURE 7. CAPACITANCE TEST CIRCUIT
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 8). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch, so two small signal
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
FN6111.3
February 5, 2008
ISL8499
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch signal range is
reduced and the resistance may increase, especially at low
supply voltages.
OPTIONAL PROTECTION
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
INX
VNO or NC
VCOM
GND
OPTIONAL PROTECTION
DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL8499 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL8499 4.7V
maximum supply voltage provides plenty of room for the
10% tolerance of 4.3V supplies, as well as room for
overshoot and noise spikes.
The minimum recommended supply voltage is 1.65V but will
operate with a supply voltage below 1.5V. It is important to
note that the input signal range, switching times, and
on-resistance degrade at lower supply voltages. Refer to the
“Electrical Specification” tables starting on page 3 and
“Typical Performance” curves starting on page 6 for details.
V+ and GND also power the internal logic and level shiftiers.
The level shiftiers convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
time minimizes power dissipation. The ISL8499 has been
designed to minimize the supply current whenever the digital
input voltage is not driven to the supply rails (0V to V+). For
example driving the device with 2.85V logic (0V to 2.85V)
while operating with a 4.2V supply the device draws only
6μA of current (see Figure 21 for VIN = 2.85V).
High-Frequency Performance
In 50Ω systems, the signal response is reasonably flat even
past 30MHz with a -3dB bandwidth of 104MHz (see
Figure 17). The frequency response is very consistent over a
wide V+ range, and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off Isolation is
the resistance to this feedthrough, while Crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 18 details the high Off Isolation and Crosstalk
rejection provided by this part. At 100kHz, Off Isolation is
about 68dB in 50Ω systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
impedances decrease Off Isolation and Crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.7V to 4.5V (see Figure 14). At 2.7V
the VIL level is about 0.52V. This is still above the 1.8V
CMOS guaranteed low output maximum level of 0.5V, but
noise margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
8
FN6111.3
February 5, 2008
ISL8499
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
0.45
0.28
V+ = 4.3V
ICOM = 100mA
ICOM = 100mA
0.26
0.40
V+ = 1.8V
0.24
rON (Ω)
rON (Ω)
0.35
0.30
+85°C
0.22
0.2
V+ = 2.7V
+25°C
0.25
0.18
V+ = 3V
0.20
V+ = 4.3V
0.16
V+ = 3.6V
0.15
0
1
2
-40°C
3
4
0.14
5
0
1
2
3
4
5
VCOM (V)
VCOM (V)
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.50
0.35
V+ = 1.8V
ICOM = 100mA
V+ = 2.7V
ICOM = 100mA
0.45
+85°C
0.30
0.40
rON (Ω)
rON (Ω)
+85°C
0.25
+25°C
0.35
0.30
0.20
+25°C
-40°C
-40°C
0.25
0.15
0.20
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
VCOM (V)
1.5
2.0
VCOM (V)
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
1.1
50
1.0
0.9
0
VINH
VINH AND VINL (V)
Q (pC)
V+ = 1.8V
V+ = 3V
-50
-100
0.8
0.7
VINL
0.6
0.5
0.4
-150
0
0.5
1.0
1.5
2.0
2.5
VCOM (V)
FIGURE 13. CHARGE INJECTION vs SWITCH VOLTAGE
9
3.0
0.3
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V+ (V)
FIGURE 14. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FN6111.3
February 5, 2008
ISL8499
200
200
150
150
100
tOFF (ns)
tON (ns)
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
+85°C
+25°C
100
+85°C
+25°C
-40°C
50
50
0
1
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
0
4.5
1.5
1
2.0
2.5
3.0
3.5
4.0
FIGURE 16. TURN - OFF TIME vs SUPPLY VOLTAGE
10
-10
V+ = 3V
V+ = 3V
0
4.5
V+ (V)
FIGURE 15. TURN - ON TIME vs SUPPLY VOLTAGE
-20
20
-30
30
-40
40
-50
50
-20
0
PHASE
20
60
80
RL = 50Ω
VIN = 0.2VP-P to 2VP-P
1M
PHASE (°)
40
ISOLATION
70
-70
80
-80
CROSSTALK
-90
90
100
-100
100
10M
100M
FREQUENCY (Hz)
60
-60
-110
1k
600M
OFF ISOLATION (dB)
GAIN
CROSSTALK (dB)
NORMALIZED GAIN (dB)
-40°C
FIGURE 17. FREQUENCY RESPONSE
10k
100k
1M
10M
FREQUENCY (Hz)
110
100M 500M
FIGURE 18. CROSSTALK AND OFF ISOLATION
100
50
V+ = 4.5V
V+ = 4.5V
VCOM = 0.3V
50
0
0
IOFF (nA)
ION (nA)
+25°C
+25°C
-50
-50
+85°C
-100
+85°C
-100
0
1
2
3
VCOM/NX (V)
4
FIGURE 19. ON LEAKAGE vs SWITCH VOLTAGE
10
5
-150
0
1
2
3
4
5
VNX (V)
FIGURE 20. OFF LEAKAGE vs SWITCH VOLTAGE
FN6111.3
February 5, 2008
ISL8499
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
200
V+ = 4.2V
Sweeping Both Logic Inputs
ION (μA)
150
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND (QFN Paddle Connection: To Ground or Float)
TRANSISTOR COUNT:
228
100
PROCESS:
Si Gate CMOS
50
0
1
2
3
4
5
VIN1-4 (V)
FIGURE 21. SUPPLY CURRENT vs VLOGIC
11
FN6111.3
February 5, 2008
ISL8499
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
E
0.25(0.010) M
2
INCHES
E1
GAUGE
PLANE
-B1
B M
L
0.05(0.002)
-A-
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.043
-
1.10
-
A1
3
A
D
-C-
e
α
c
0.10(0.004)
C A M
0.05
0.15
-
A2
0.033
0.037
0.85
0.95
-
b
0.0075
0.012
0.19
0.30
9
c
0.0035
0.008
0.09
0.20
-
B S
0.002
D
0.193
0.201
4.90
5.10
3
0.169
0.177
4.30
4.50
4
0.026 BSC
E
0.246
L
0.020
N
a
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
0.006
E1
e
A2
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
MILLIMETERS
0.65 BSC
0.256
6.25
0.028
0.50
16
0o
-
0.70
6
16
8o
0o
-
6.50
7
8o
Rev. 1 2/02
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm
(0.006 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact. (Angles in degrees)
12
FN6111.3
February 5, 2008
ISL8499
Package Outline Drawing
L16.3x3
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 4/07
4X 1.5
3.00
12X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
16
13
1
3.00
12
1 .50 ± 0 . 15
9
4
0.15
(4X)
5
8
0.10 M C A B
+ 0.07
4 16X 0.23 - 0.05
TOP VIEW
16X 0.40 ± 0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0.1
C
BASE PLANE
( 2. 80 TYP )
(
SEATING PLANE
0.08 C
1. 50 )
SIDE VIEW
( 12X 0 . 5 )
( 16X 0 . 23 )
C
( 16X 0 . 60)
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
13
FN6111.3
February 5, 2008
ISL8499
Thin Quad Flat No-Lead Plastic Package (TQFN)
Thin Micro Lead Frame Plastic Package (TMLFP)
2X
L16.3x3A
0.15 C A
D
A
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
9
D/2
MILLIMETERS
D1
D1/2
2X
N
6
INDEX
AREA
0.15 C B
1
2
3
E1/2
E/2
MIN
NOMINAL
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
A2
-
-
0.80
9
0.30
5, 8
A3
E1
E
b
9
0.20 REF
0.18
D
2X
B
TOP VIEW
0.15 C A
D2
A2
0
A
/ / 0.10 C
C
A3
SIDE VIEW
9
5
NX b
4X P
E
3.00 BSC
-
2.75 BSC
9
1.35
1.50
1.65
7, 8, 10
0.50 BSC
-
k
0.20
-
-
-
L
0.30
0.40
0.50
8
2
8
Nd
4
3
NX k
Ne
4
3
D2
2 N
1
(DATUM A)
2
3
6
INDEX
AREA
E2/2
N e
9
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
SECTION "C-C"
C
L
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
L
L1
10
L
e
TERMINAL TIP
FOR ODD TERMINAL/SIDE
9
12
3. Nd and Ne refer to the number of terminals on each D and E.
A1
e
0.60
-
2. N is the number of terminals.
NX b
10
-
-
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
8
BOTTOM VIEW
C
L
-
θ
NOTES:
9
CORNER
OPTION 4X
(Nd-1)Xe
REF.
P
Rev. 0 6/04
(Ne-1)Xe
REF.
E2
7
NX L
C C
7, 8, 10
16
7
L1
9
1.65
N
4X P
8
1.50
0.10 M C A B
D2
(DATUM B)
A1
-
2.75 BSC
1.35
e
SEATING PLANE
9
E1
E2
0.08 C
0.23
3.00 BSC
D1
0.15 C B
2X
4X
SYMBOL
FOR EVEN TERMINAL/SIDE
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2
and D2 MAX dimension.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN6111.3
February 5, 2008
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