DATASHEET

ISL9012
Data Sheet
December 10, 2015
Dual LDO with Low Noise, Low IQ, and
High PSRR
FN9220.4
Features
ISL9012 is a high performance dual LDO capable of
sourcing 150mA current from Channel 1, and 300mA from
Channel 2. The device has a low standby current and
high-PSRR and is stable with output capacitance of 1µF to
10µF with ESR of up to 200m.
The device integrates a Power-On-Reset (POR) function for
the VO2 output. The POR delay for VO2 can be externally
programmed by connecting a timing capacitor to the CPOR
pin. A reference bypass pin is also provided for connecting a
noise-filtering capacitor for low noise and high PSRR
applications.
• Integrates two high performance LDOs
- VO1 - 150mA output
- VO2 - 300mA output
• Excellent transient response to large current steps
• Excellent load regulation:
1% voltage change across full range of load current
• High PSRR: 70dB @ 1kHz
• Wide input voltage capability: 2.3V to 6.5V
• Extremely low quiescent current: 45µA (both LDOs on)
• Low dropout voltage: typically 120mV @ 150mA
The quiescent current is typically only 45µA with both LDO’s
enabled and active. Separate enable pins control each
individual LDO output. When both enable pins are low, the
device is in shutdown, typically drawing less than 0.1µA.
• Low output noise: typically 30µVRMS @ 100µA (1.5V)
Several combinations of voltage outputs are standard.
Output voltage options for each LDO range from 1.5V to
3.3V. Other output voltage options are available on request.
• POR output, with adjustable delay time indicates when the
VO2 output is good
• Stable with 1 to10µF ceramic capacitors
• Separate enable pins for each LDO
• Soft-start to limit input current surge during enable
• Current limit and overheat protection
Pinout
• ±1.8% accuracy over all operating conditions
ISL9012
(10 LD 3X3 DFN)
TOP VIEW
• Tiny 10 Ld 3x3mm DFN package
• -40°C to +85°C operating temperature range
VIN
1
10 VO1
EN1
2
9
VO2
• Pin compatible with Micrel MIC2212
• Pb-free (RoHS compliant)
EN2
3
8
POR
CBYP
4
7
NC
Applications
CPOR
5
6
GND
• PDAs, Cell Phones and Smart Phones
• Portable Instruments, MP3 Players
• Handheld Devices including Medical Handhelds
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas LLC 2005, 2006. 2008, 2015. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL9012
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
VO1 VOLTAGE
(V)
VO2 VOLTAGE
(V)
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG. DWG. #
ISL9012IRNNZ
DCTA
3.3
3.3
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9012IRNJZ (No
longer available,
recommended
replacement:
ISL9000AIRNJZ)
DAPA
3.3
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9012IRNFZ (No
longer available,
recommended
replacement:
ISL9000AIRNFZ)
DARA
3.3
2.5
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9012IRMNZ
DCYA
3.0
3.3
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9012IRMMZ (No
longer available,
recommended
replacement:
ISL9000AIRMGZ-T)
DAAK
3.0
3.0
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9012IRMGZ
DCBC
3.0
2.7
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9012IRJNZ
DCBD
2.8
3.3
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9012IRJMZ (No
longer available,
recommended
replacement:
ISL9000AIRJBZ-T)
DAAH
2.8
3.0
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9012IRJRZ (No
longer available,
recommended
replacement:
ISL9000AIRJNZ-T)
DAAG
2.8
2.6
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9012IRJCZ (No
longer available,
recommended
replacement:
ISL9000AIRJBZ-T)
DAAF
2.8
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9012IRFDZ
DCBK
2.5
2.0
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9012IRFCZ
DCBL
2.5
2.0
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9012IRCJZ
DCBN
1.8
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9012IRCCZ
DCBP
1.8
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. For other output voltages, contact Intersil Marketing.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2
FN9220.4
December 10, 2015
ISL9012
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V
VO1, VO2 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)V
Thermal Resistance (Notes 4, 5)
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V
JA (°C/W)
JC (°C/W)
3x3 DFN Package . . . . . . . . . . . . . . . .
50
10
Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
5. JC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows:
TA = -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF;
CBYP = 0.01µF; CPOR = 0.01µF
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8) UNITS
DC CHARACTERISTICS
Supply Voltage
2.3
VIN
Ground Current
6.5
V
Quiescent condition: IO1 = 0µA; IO2 = 0µA
IDD1
One LDO active
25
40
µA
IDD2
Both LDO active
45
60
µA
Shutdown Current
IDDS
@+25°C
0.1
1.0
µA
UVLO Threshold
VUV+
1.9
2.1
2.3
V
1.6
1.8
VUVRegulation Voltage Accuracy
Variation from nominal voltage output, VIN = VO + 0.5 to 5.5V,
TJ = -40°C to +125°C
-1.8
Line Regulation
VIN = (VOUT + 1.0V relative to highest output voltage) to 5.5V
-0.2
Load Regulation
IOUT = 100µA to 150mA (VO1 and VO2)
2.0
V
+1.8
%
0
0.2
%/V
0.1
0.7
%
IOUT = 100µA to 300mA (VO2)
Maximum Output Current
IMAX
Internal Current Limit
Thermal Shutdown Temperature
%
150
mA
VO2: Continuous
300
mA
ILIM
Dropout Voltage (Note 7)
1.0
VO1: Continuous
350
475
600
mA
VDO1
IO = 150mA; VO 2.1V (VO1)
125
200
mV
VDO2
IO = 300mA; VO < 2.5V (VO2)
300
500
mV
VDO3
IO = 300mA; 2.5V  VO  2.8V (VO2)
250
400
mV
VDO4
IO = 300mA; VO > 2.8V (VO2)
200
325
mV
TSD+
145
°C
TSD-
110
°C
@ 1kHz
70
dB
@ 10kHz
55
dB
@ 100kHz
40
dB
AC CHARACTERISTICS
Ripple Rejection
IO = 10mA, VIN = 2.8V(min), VO = 1.8V, CBYP = 0.1µF
3
FN9220.4
December 10, 2015
ISL9012
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows:
TA = -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF;
CBYP = 0.01µF; CPOR = 0.01µF (Continued)
PARAMETER
SYMBOL
Output Noise Voltage
MIN
(Note 8)
TEST CONDITIONS
TYP
IO = 100µA, VO = 1.5V, TA = +25°C, CBYP = 0.1µF
BW = 10Hz to 100kHz (Note 6)
30
MAX
(Note 8) UNITS
µVrms
DEVICE START-UP CHARACTERISTICS
Device Enable TIme
tEN
Time from assertion of the ENx pin to when the output voltage
reaches 95% of the VO(nom)
250
500
µs
LDO Soft-start Ramp Rate
tSSR
Slope of linear portion of LDO output voltage ramp during startup
30
60
µs/V
EN1, EN2 PIN CHARACTERISTICS
Input Low Voltage
VIL
-0.3
0.5
V
Input High Voltage
VIH
1.4
VIN+0.3
V
0.1
µA
Input Leakage Current
IIL, IIH
Pin Capacitance
CPIN
Informative
5
pF
POR PIN CHARACTERISTICS
POR Thresholds
VPOR+
As a percentage of nominal output voltage
VPORPOR Delay
tPLH
CPOR = 0.01µF
91
94
97
%
87
90
93
%
100
200
300
ms
25
tPHL
POR Pin Output Low Voltage
VOL
POR Pin Internal Pull-Up
Resistance
@IOL = 1.0mA
RPOR
78
100
µs
0.2
V
180
k
NOTES:
6. Limits established by characterization and are not production tested.
7. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V.
8. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
EN2
tEN
VPOR+
VPOR-
VPOR+
VPOR-
<tPHL
VO2
tPLH
tPHL
POR
FIGURE 1. TIMING PARAMETER DEFINITION
4
FN9220.4
December 10, 2015
ISL9012
Typical Performance Curves
0.10
0.8
VO = 3.3V
ILOAD = 0mA
0.4
0.2
-40C
0.0
+25C
-0.2
+85C
-0.4
VIN = 3.8V
VO = 3.3V
0.08
OUTPUT VOLTAGE CHANGE (%)
OUTPUT VOLTAGE, VO (%)
0.6
-0.6
0.06
0.04
-40C
0.02
+25C
0.00
-0.02
+85C
-0.04
-0.06
-0.08
-0.8
3.4
3.8
4.6
4.2
5.0
5.4
5.8
6.2
-0.10
6.6
0
50
200
250
300
350
400
LOAD CURRENT - IO (mA)
FIGURE 2. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V
OUTPUT)
FIGURE 3. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT
3.4
0.10
VIN = 3.8V
VO = 3.3V
ILOAD = 0mA
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
VO1 = 3.3V
IO = 0mA
3.3
OUTPUT VOLTAGE, VO (V)
OUTPUT VOLTAGE CHANGE (%)
150
100
INPUT VOLTAGE (V)
3.2
IO = 150mA
3.1
3.0
2.9
-0.08
2.8
-0.10
-40
-25
-10
5
20 35 50 65
TEMPERATURE (C)
80
95
110 125
FIGURE 4. OUTPUT VOLTAGE CHANGE vs TEMPERATURE
DROPOUT VOLTAGE, VDO (mV)
OUTPUT VOLTAGE, VO (V)
5.1
5.6
6.1
6.5
300
IO = 150mA
2.6
IO = 300mA
2.5
2.4
3.1
4.6
350
VO2 = 2.8V
2.7
2.6
4.1
FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE
(VO1 = 3.3V)
2.8
2.3
3.6
INPUT VOLTAGE (V)
2.9
IO = 0mA
3.1
3.6
4.1
4.6
5.1
5.6
INPUT VOLTAGE (V)
FIGURE 6. OUTPUT VOLTAGE vs INPUT VOLTAGE
(VO2 = 2.8V)
5
6.1
6.5
250
VO2 = 2.8V
200
150
100
VO1 = 3.3V
50
0
0
50
100
150
200
250
OUTPUT LOAD (mA)
300
350
400
FIGURE 7. VO1 DROPOUT VOLTAGE vs LOAD CURRENT
FN9220.4
December 10, 2015
ISL9012
Typical Performance Curves
(Continued)
55
175
50
GROUND CURRENT (µA)
DROPOUT VOLTAGE, VDO (mV)
VO1 = 3.3V
150
125
+85C
+25C
-40C
100
75
50
+125C
+25C
45
-40C
40
35
VO1 = 3.3V
VO2 = 2.8V
30
25
IO (BOTH CHANNELS) = 0µA
0
25
0
25
50
75
100
125
OUTPUT LOAD (mA)
150
175
200
3.0
4.0
3.5
4.58
5.0
5.5
6.5
6.0
INPUT VOLTAGE (V)
FIGURE 8. VO1 DROPOUT VOLTAGE vs LOAD CURRENT
FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE
200
55
180
50
140
+25C
+85C
120
GROUND CURRENT (µA)
GROUND CURRENT (µA)
160
-40C
100
80
60
40
VIN = 3.8V
VO1 = 3.3V
VO2 = 2.8V
20
0
0
50
100
150
200
250
300
350
45
40
35
VIN = 3.8V
VO = 3.3V
ILOAD = 0µA
30
BOTH OUTPUTS ON
25
-40
400
-25
-10
5
LOAD CURRENT (mA)
35
20
50
65
FIGURE 10. GROUND CURRENT vs LOAD
VIN
VO1
VO1 = 3.3V
VO2 = 2.8V
IL1 = 150mA
3.0
IL2 = 300mA
2.5
3
2
VOLTAGE (V)
VOLTAGE (V)
4
95
110 125
FIGURE 11. GROUND CURRENT vs TEMPERATURE
3.5
5
80
TEMPERATURE (C)
VO2
1
0
VO1 = 3.3V
VO2 = 2.8V
IL1 = 150mA
POR
IL2 = 300mA
CPOR = 0.1µF
2.0
VO-1
1.5
VO-2
1.0
0.5
0
0
1
2
3
4
5
6
TIME (s)
7
8
FIGURE 12. POWER-UP/POWER-DOWN
6
9
10
0
0.5
1.0
1.5
2.0
2.5
3.0
TIME (s)
3.5
4.0
4.5
5.0
FIGURE 13. POWER-UP/POWER-DOWN WITH POR SIGNALS
FN9220.4
December 10, 2015
ISL9012
Typical Performance Curves
(Continued)
VO2 (10mV/DIV)
VO = 3.3V
ILOAD = 150mA
2
VO1 (V)
CLOAD = 1µF
CBYP = 0.01µF
VIN = 5.0V
VO1 = 3.3V
VO2 = 2.8V
IL1 = 150mA
IL2 = 300mA
CL1, CL2 = 1µF
CBYP = 0.01µF
3
1
4.3V
3.6V
0
VEN (V)
5
10mV/DIV
0
0
100
200
300
400
500
600
700
800
900 1000
400µs/DIV
TIME (µs)
FIGURE 14. TURN ON/TURN OFF RESPONSE
FIGURE 15. LINE TRANSIENT RESPONSE, 3.3V OUTPUT
VO = 2.8V
ILOAD = 300mA
CLOAD = 1µF
CBYP = 0.01µF
VO (25mV/DIV)
4.2V
3.5V
VO = 1.8V
VIN = 2.8V
300mA
10mV/DIV
ILOAD
10µA
100µs/DIV
400µs/DIV
FIGURE 17. LOAD TRANSIENT RESPONSE
FIGURE 16. LINE TRANSIENT RESPONSE, 2.8V OUTPUT
100
SPECTRAL NOISE DENSITY (nV/Hz)
80
CBYP = 0.01µF
70
PSRR (dB)
1000
VIN = 3.6V
VO = 1.8V
IO = 10mA
90
CLOAD = 1µF
60
50
40
30
20
10
0
0.1k
1k
10k
FREQUENCY (Hz)
100k
FIGURE 18. PSRR vs FREQUENCY
7
1M
100
10
1
VIN = 3.6V
VO = 1.8V
ILOAD = 10mA
CBYP = 0.01µF
CIN = 1µF
CLOAD = 1µF
0.1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 19. SPECTRAL NOISE DENSITY vs FREQUENCY
FN9220.4
December 10, 2015
ISL9012
Pin Description
PIN
NUMBER
PIN
NAME
1
VIN
Analog I/O
Supply Voltage/LDO Input:
Connect a 1µF capacitor to GND.
2
EN1
Low Voltage Compatible
CMOS Input
LDO-1 Enable.
3
EN2
Low Voltage Compatible
CMOS Input
LDO-2 Enable.
4
CBYP
Analog I/O
Reference Bypass Capacitor Pin:
Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in the
desired noise and PSRR performance.
5
CPOR
Analog I/O
POR Delay Setting Capacitor Pin:
Connect a capacitor between this pin and GND to delay the POR output release after LDO-2
output reaches 94% of its specified voltage level (200ms delay per 0.01µF).
6
GND
Ground
GND is the connection to system ground. Connect to PCB Ground plane.
7
NC
NC
No Connection.
8
POR
Open Drain Output (1mA)
Open-drain POR Output for LDO-2 (active-low).
9
VO2
Analog I/O
LDO-2 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
10
VO1
Analog I/O
LDO-1 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
TYPE
DESCRIPTION
Typical Application
R1
ISL9012
VIN (2.3V TO 6.5V)
1
ON
2
ENABLE 1
OFF ON
ENABLE 2
OFF
3
4
5
C1
C2
VIN
EN1
EN2
VO1
VO2
POR
CBYP
NC
CPOR
GND
10
VOUT 1
9
VOUT 2 OK
8
VOUT2
RESET
VOUT2 TOO LOW (200ms DELAY, C3 = 0.01µF)
7
6
C3
C4
C5
C1, C4, C5: 1µF X5R CERAMIC CAPACITOR
C2: 0.01µF X5R CERAMIC CAPACITOR
C3: 0.01µF X5R CERAMIC CAPACITOR
R1: 100k RESISTOR, 5%
8
FN9220.4
December 10, 2015
ISL9012
Block Diagram
VIN
IS2
1V
LDO
VREF
ERROR
TRIM
VO2
AMPLIFIER
VO1
QEN2
~1.0V
VO2
POR
COMPARATOR
VOK2
POR
LDO-2
EN1
QEN2
QEN1
IS2
IS1
LDO-1
CONTROL
LOGIC
EN2
UVLO
GND
BANDGAP AND
TEMPERATURE
SENSOR
VOK2
VOLTAGE
REFERENCE
GENERATOR
CBYP
Functional Description
The ISL9012 contains all circuitry required to implement two
high performance LDO’s. High performance is achieved
through a circuit that delivers fast transient response to
varying load conditions. In a quiescent condition, the
ISL9012 adjusts its biasing to achieve the lowest standby
current consumption.
The device also integrates current limit protection, smart
thermal shutdown protection, staged turn-on and soft-start.
Smart Thermal shutdown protects the device against
overheating. Staged turn-on and soft-start minimize start-up
input current surges without causing excessive device
turn-on time.
Power Control
The ISL9012 has two separate enable pins, EN1 and EN2,
to individually control power to each of the LDO outputs.
When both EN1 and EN2 are low, the device is in shutdown
9
POR
DELAY
POR
1.00V
0.94V
0.90V
CPOR
mode. During this condition, all on-chip circuits are off, and
the device draws minimum current, typically less than 0.1µA.
When one or both of the enable pins are asserted, the
device first polls the output of the UVLO detector to ensure
that VIN voltage is at least about 2.1V. Once verified, the
device initiates a start-up sequence. During the start-up
sequence, trim settings are first read and latched. Then,
sequentially, the bandgap, reference voltage and current
generation circuitry power up. Once the references are
stable, a fast-start circuit quickly charges the external
reference bypass capacitor (connected to the CBYP pin) to
the proper operating voltage. After the bypass capacitor has
been charged, the LDO’s power up.
If EN1 is brought high, and EN2 goes high before the VO1
output stabilizes, the ISL9012 delays the VO2 turn-on until
the VO1 output reaches its target level.
If EN2 is brought high, and EN1 goes high before VO2 starts
its output ramp, then VO1 turns on first and the ISL9012
FN9220.4
December 10, 2015
ISL9012
delays the VO2 turn-on until the VO1 output reaches its
target level.
one of the following output voltages: 1.5V, 1.8V, 1.85V, 2.5V,
2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V, and 3.3V.
If EN2 is brought high, and EN1 goes high after VO2 starts
its output ramp, then the ISL9012 immediately starts to ramp
up the VO1 output.
Power-On Reset Generation
If both EN1 and EN2 are high, the VO1 output has priority,
and is always powered up first.
During operation, whenever the VIN voltage drops below
about 1.8V, the ISL9012 immediately disables both LDO
outputs. When VIN rises back above 2.1V, the device
re-initiates its start-up sequence and LDO operation will
resume automatically.
Reference Generation
The reference generation circuitry includes a trimmed
bandgap, a trimmed voltage reference divider, a trimmed
current reference generator, and an RC noise filter. The filter
includes the external capacitor connected to the CBYP pin.
A 0.01µF capacitor connected CBYP implements a 100Hz
lowpass filter, and is recommended for most high
performance applications. For the lowest noise application, a
0.1µF or greater CBYP capacitor should be used. This filters
the reference noise to below the 10Hz to1kHz frequency
band, which is crucial in many noise-sensitive applications.
The bandgap generates a zero temperature coefficient (TC)
voltage for the reference divider. The reference divider
provides the regulation reference, POR detection thresholds,
and other voltage references required for current generation
and over-temperature detection.
The current generator outputs references required for
adaptive biasing as well as references for LDO output
current limit and thermal shutdown determination.
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9012 provides a regulator that has low
quiescent current, fast transient response, and overall
stability across all operating and load current conditions.
LDO stability is guaranteed for a 1µF to 10µF output
capacitor that has a tolerance better than 20% and ESR less
than 200m. The design is performance-optimized for a 1µF
capacitor. Unless limited by the application, use of an output
capacitor value above 4.7µF is not recommended as LDO
performance improvement is minimal.
LDO-2 has a Power-on Reset signal generation circuit which
outputs to the POR pin. The POR signal is generated as
follows:
A POR comparator continuously monitors the voltage of the
LDO-2 output. The LDO enters a power-good state when the
output voltage is above 94% of the expected output voltage
for a period exceeding the LDO PGOOD entry delay time. In
the power-good state, the open-drain POR output is in a
high-impedance state. An external resistor can be added
between the POR output and either LDO output or the input
voltage, VIN.
The power-good state is exited when the LDO-2 output falls
below 90% of the expected output voltage for a period longer
than the PGOOD exit delay time. While power-good is false,
the ISL9012 pulls the respective POR pin low.
The PGOOD entry and exit delays are determined by the
value of the external capacitor connected to the CPOR pin.
For a 0.01µF capacitor, the entry and exit delays are 200ms
and 25µs respectively. Larger or smaller capacitor values will
yield proportionately longer or shorter delay times. The POR
exit delay should never be allowed to be less than 10µs to
ensure sufficient immunity against transient induced false
POR triggering.
Overheat Detection
The bandgap outputs a proportional-to-temperature current
that is indicative of the temperature of the silicon. This
current is compared with references to determine if the
device is in danger of damage due to overheating. When the
die temperature reaches about +145°C, one or both of the
LDO’s momentarily shut down until the die cools sufficiently.
In the overheat condition, only the LDO sourcing more than
50mA will be shut off. This does not affect the operation of
the other LDO. If both LDOs source more than 50mA and an
overheat condition occurs, both LDO outputs are disabled.
Once the die temperature falls back below about +110°C,
the disabled LDO(s) are re-enabled and soft-start
automatically takes place.
Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge. The
ISL9012 provides short-circuit protection by limiting the
output current to about 475mA.
Each LDO uses an independently trimmed 1V reference. An
internal resistor divider drops the LDO output voltage down
to 1V. This is compared to the 1V reference for regulation.
The resistor division ratio is programmed in the factory to
10
FN9220.4
December 10, 2015
ISL9012
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
CHANGE
December 10, 2015
FN9220.4
Added Rev History beginning with Rev 4.
Added About Intersil. Verbiage.
Updated Ordering Information table on page 2
Updated POD L10.3x3C to most current version. Revision changes are as follows:
Updated Format to new standard
Removed package outline and included center to center distance between lands on recommended land
pattern.
Removed Note 4 "Dimension b applies to the metallized terminal and is measured between 0.18mm and
0.30mm from the terminal tip." since it is not applicable to this package. Renumbered notes accordingly.
Tiebar Note 4 updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN9220.4
December 10, 2015
ISL9012
Package Outline Drawing
L10.3x3C
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 4, 3/15
3.00
5
PIN #1 INDEX AREA
A
B
10
5
PIN 1
INDEX AREA
1
2.38
3.00
0.50
2
10 x 0.25
6
(4X)
0.10 C B
1.64
TOP VIEW
10x 0.40
BOTTOM VIEW
(4X)
0.10 M C B
SEE DETAIL "X"
(10 x 0.60)
(10x 0.25)
0.90
MAX
0.10 C
BASE PLANE
2.38
0.20
C
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
1.64
2.80 TYP
C
TYPICAL RECOMMENDED LAND PATTERN
0.20 REF
4
0.05
DETAIL "X"
NOTES:
12
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
5.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
6.
Compliant to JEDEC MO-229-WEED-3 except for E-PAD
dimensions.
FN9220.4
December 10, 2015
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