DATASHEET

150mA Dual LDO with Low Noise, High PSRR, and Low IQ
ISL9016
Features
ISL9016 is a high performance dual LDO capable of providing
up to 150mA current on each channel. It features a low standby
current and very high PSRR and is stable with output
capacitance of 1µF to 4.7µF with an ESR of up to 200mΩ.
• Dual Integrated 150mA High Performance LDOs
The device integrates a separate enable function for each
output. The quiescent current is typically 49µA when only one
LDO is enabled and typically 80µA when both LDOs are
enabled. When both LDOs are under shutdown condition, the
drawing current is typically less than 1µA.
ISL9016 provides a wide input voltage range from 1.8V to
6.5V. It also has a high PSRR of 80dB at 1kHz and 45dB at
1MHz. ISL9016 also provides output current limit, overheat
protection, reverse current protection, as well as excellent load
transient response.
ISL9016 is offered in a tiny 1.6mmx1.6mm 6 Ld µTDFN
package. Output voltage options are available from 1.2V to
3.3V. Several combinations of voltage outputs are standard
and others may be available upon request.
• High PSRR: 80dB @ 1kHz and 45dB @ 1MHz
• Reverse Current Protection
• Low Quiescent Current
- 49µA (Single LDO Enabled)/80µA (Dual LDOs Enabled)
• Excellent Load Transient Response
• Typically ±0.8% Output Voltage Accuracy
• Low Output Noise: Typically 25µVRMS
• Wide Input Voltage Capability: 1.8V to 6.5V
• Low Dropout Voltage: Typically 120mV @ 150mA
• Separate Enable Control for each LDO
• Stable with 1µF to 4.7µF Ceramic Output Capacitors
• Soft-start to Limit Input Current Surge During Enable
• Current Limit and Overheat Protection
• Tiny 6 Ld 1.6mmx1.6mm µTDFN package
• Pb-free (RoHS Compliant)
Applications
• PDAs, Cell Phones and Smart Phones
• Portable Instruments, MP3/4 Players, PMP, DSC
• Handheld Devices including Medical Handhelds
ISL9016
VIN (1.8V TO 6.5V)
VIN
VOUT1
1.2V~3.3V, 0~150mA
VOUT1
VOUT2
1.2V~3.3V, 0~150mA
C1
R1
GND
VOUT2
EN2
EN1
C2
ON
OFF
ON
C3
R2
OFF
C1, C2, C3: 1µF, X5R (or X7R) CERAMIC CAPACITOR
R1, R2: 100k
FIGURE 1. TYPICAL APPLICATION DIAGRAM
May 16, 2011
FN6832.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2009, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL9016
Pin Configuration
ISL9016
(6 LD 1.6x1.6 µTDFN)
TOP VIEW
VIN 1
6 VOUT1
GND 2
5 VOUT2
EN2 3
4 EN1
Pin Descriptions
PIN #
PIN NAME
DESCRIPTION
1
VIN
Supply Voltage/LDO Input. Connect a 1µF capacitor to GND.
2
GND
GND is the connection to system ground. Connect to PCB Ground plane.
3
EN2
LDO2 Enable pin. Enable = High, Disable = Low. A 100k resistor should be connected between EN2 and the control voltage rail.
Do NOT leave it floating.
4
EN1
LDO1 Enable pin. Enable = High, Disable = Low. A 100k resistor should be connected between EN1 and the control voltage rail.
Do NOT leave it floating.
5
VOUT2
LDO2 Output. Connect capacitor with a value from 1µF to 4.7µF to GND (1µF recommended).
6
VOUT1
LDO1 Output. Connect capacitor with a value from 1µF to 4.7µF to GND (1µF recommended).
-
E-Pad
Connect the e-pad to the system ground.
2
FN6832.1
May 16, 2011
ISL9016
Ordering Information
PART NUMBER
(Notes 1, 3)
PART
MARKING
VO1 VOLTAGE
(V) (Note 2)
VO2 VOLTAGE
(V) (Note 2)
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG
DWG. #
ISL9016IRUWCZ-T
N7
1.2
1.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUWGZ-T
N6
1.2
2.7
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUWJZ-T
N2
1.2
2.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUWKZ-T
N1
1.2
2.85
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUBWZ-T
R7
1.5
1.2
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUBBZ-T
R6
1.5
1.5
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUCWZ-T
R5
1.8
1.2
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUCBZ-T
R4
1.8
1.5
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUCCZ-T
U7
1.8
1.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUFWZ-T
R3
2.5
1.2
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUFBZ-T
N8
2.5
1.5
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUFCZ-T
N9
2.5
1.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUFFZ-T
P0
2.5
2.5
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUGWZ-T
P1
2.7
1.2
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUGCZ-T
R2
2.7
1.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUGGZ-T
N3
2.7
2.7
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUJWZ-T
P2
2.8
1.2
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUJBZ-T
P3
2.8
1.5
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUJCZ-T
N4
2.8
1.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUJJZ-T
N0
2.8
2.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUKWZ-T
P5
2.85
1.2
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUKFZ-T
P4
2.85
2.5
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUKKZ-T
N5
2.85
2.85
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUMWZ-T
P6
3.0
1.2
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUMBZ-T
P7
3.0
1.5
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUMCZ-T
P8
3.0
1.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUMKZ-T
P9
3.0
2.85
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUNWZ-T
R0
3.3
1.2
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUNCZ-T
R1
3.3
1.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. For other output voltages, contact Intersil marketing or local sales office.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and Tin Bismuth plate - e6
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL9016. For more information on MSL please see techbrief TB363.
3
FN6832.1
May 16, 2011
ISL9016
Absolute Maximum Ratings
Thermal Information
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.1V
All Other Pins to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)V
Thermal Resistance
Recommended Operating Conditions
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 6.5V
Each LDO Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . up to 150mA
Ambient Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
θJA (°C/W)
6 Ld µTDFN Package (Note 5) . . . . . . . . . . . . . . . . . . . .
117.5
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
Electrical Specifications Typical specifications are measured at the following conditions: TA = +25°C; VIN = (VO + 0.5V) to 6.5V with a
minimum VIN of 1.8V; CIN = 1µF; CO = 1µF. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8) UNITS
DC CHARACTERISTICS
Supply Voltage
VIN
UVLO Threshold
VUV+
1.8
1.710
VUV-
1.55
6.5
V
1.775
V
1.62
Quiescent condition: IO1 = 0µA; IO2 = 0µA
Input Quiescent Current
Shutdown Current
IDD1
One LDO active
49
67
µA
IDD2
Both LDO active
80
100
µA
IDDS
@ +25°C
0.1
1.0
µA
Regulation Voltage Accuracy
Maximum Output Current
IMAX
VIN = VO + 0.5V to 6.5V, IO = 10µA to 150mA, TA = +25°C
-0.8
+0.8
%
VIN = VO + 0.5V to 6.5V, IO = 10µA to 150mA, TA = -40°C to +85°C
-1.8
+1.8
%
Each LDO, Continuous
150
mA
Internal Current Limit
ILIM
265
355
mA
Dropout Voltage (Note 6)
VDO1
IO = 150mA; 1.2V ≤ VO ≤ 2.1V
250
425
mV
VDO2
IO = 150mA; 2.1V ≤ VO ≤ 2.8V
200
325
mV
VDO3
IO = 150mA; 2.8V ≤ VO
120
200
mV
Thermal Shutdown Temperature
175
TSD+
145
°C
TSD-
110
°C
@ 1kHz
80
dB
@ 10kHz
60
dB
@ 100kHz
50
dB
@ 1MHz
45
dB
VIN = 4.2V, IO = 10mA, TA = +25°C, BW = 10Hz to 100kHz
25
µVRMS
400
600
µs
30
60
µs/V
AC CHARACTERISTICS
IO = 10mA, VIN = 3.7V(min), VO = 2.7V, TA = +25°C
Ripple Rejection
Output Noise Voltage
DEVICE START-UP CHARACTERISTICS
Device Enable Time
tEN
Time from assertion of the ENx pin to when the output voltage
reaches 95% of the VO(nom)
LDO Soft-Start Ramp Rate
tSSR
Slope of linear portion of LDO output voltage ramp during start-up
4
FN6832.1
May 16, 2011
ISL9016
Electrical Specifications Typical specifications are measured at the following conditions: TA = +25°C; VIN = (VO + 0.5V) to 6.5V with a
minimum VIN of 1.8V; CIN = 1µF; CO = 1µF. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8) UNITS
EN PIN CHARACTERISTICS
Input Low Voltage
VIL
Input High Voltage
VIH
Input Leakage Current
TA = -20°C to +85°
-0.3
0.4
V
1.1
VIN + 0.3
V
0.1
µA
15
µA
IIL, IIH
REVERSE CURRENT CHARACTERISTICS
Output Reverse Leakage Current
(Note 7)
IORLC
VIN = 0V, VOUT = 5.5V
8
NOTES:
6. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.80V.
7. Output reverse leakage current is measured with VIN pin grounded and VOUT pin connected to 5.5V.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
5
FN6832.1
May 16, 2011
ISL9016
Typical Operating Performance
55
55
50
QUIESCENT CURRENT (µA)
QUIESCENT CURRENT (µA)
T = +85°C
T = +85°C
T = +50°C
T = +25°C
45
40
T = 0°C
35
T = -40°C
30
2.4
T = -25°C
3.6
4.8
T = +50°C
50
T = +25°C
45
40
T = 0°C
35
T = -25°C
T = -40°C
30
2.4
6.0
FIGURE 2. QUIESCENT CURRENT vs INPUT VOLTAGE (VOUT1 = 2.1V,
ONLY LDO1 ENABLED)
T = +50°C
T = +25°C
75
70
T = 0°C
65
60
2.4
T = -25°C
3.6
4.8
T = +25°C
40
T = 0°C
T = -25°C
35
T = -40°C
4.4
5.2
6.0
INPUT VOLTAGE (V)
FIGURE 4. QUIESCENT CURRENT vs INPUT VOLTAGE
(VOUT1 = VOUT2 = 2.1V, LDO1 AND LDO2 ENABLED)
FIGURE 5. QUIESCENT CURRENT vs INPUT VOLTAGE (VOUT1 = 3.3V,
ONLY LDO1 ENABLED)
55
85
T = +25°C
T = +50°C
T = +85°C
QUIESCENT CURRENT (µA)
QUIESCENT CURRENT (µA)
T = +85°C
45
30
3.6
6.0
T = +50°C
50
INPUT VOLTAGE (V)
50
45
40
T = 0°C
T = -25°C
35
T = +25°C
80
T = +85°C
T = +50°C
75
T = 0°C
70
T = -25°C
65
T = -40°C
T = -40°C
30
6.0
55
T = +85°C
T = -40°C
4.8
FIGURE 3. QUIESCENT CURRENT vs INPUT VOLTAGE (VOUT2 = 2.1V,
ONLY LDO2 ENABLED)
QUIESCENT CURRENT (µA)
QUIESCENT CURRENT (µA)
85
80
3.6
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3.6
4.4
5.2
6.0
INPUT VOLTAGE (V)
FIGURE 6. QUIESCENT CURRENT vs INPUT VOLTAGE (VOUT2 = 3.3V,
ONLY LDO2 ENABLED)
6
60
3.6
4.4
5.2
6.0
INPUT VOLTAGE (V)
FIGURE 7. QUIESCENT CURRENT vs INPUT VOLTAGE
(VOUT1 = VOUT2 = 3.3V, LDO1 AND LDO2 ENABLED)
FN6832.1
May 16, 2011
ISL9016
Typical Operating Performance
(Continued)
10
15
T = +85°C
10
ΔVO (mV)
0
-5
T = +25°C
-5
-10
T = -40°C
-15
-10
T = -40°C
-15
1.5
3.0
4.5
-20
6.0
1.5
2.5
FIGURE 8. ΔVOUT vs INPUT VOLTAGE (VOUT_NOMINAL = 1.2V,
IOUT = 50mA)
4.5
5.5
FIGURE 9. ΔVOUT vs INPUT VOLTAGE (VOUT_NOMINAL = 1.2V,
IOUT = 150mA)
3.32
1.22
OUTPUT VOLTAGE (V)
1.21
1.20
T = +25°C
1.19
30
3.30
T = +85°C
3.29
3.28
T = -40°C
3.27
3.26
T = -40°C
0
T = +25°C
3.31
T = +85°C
OUTPUT VOLTAGE (V)
3.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
1.18
T = +25°C
0
5
ΔVO (mV)
T = +85°C
5
60
90
120
150
3.25
0
30
LOAD CURRENT (mA)
FIGURE 10. LOAD REGULATION (VIN = 1.8V, VOUT = 1.2V)
EN1 = EN2
5V/DIV
60
90
LOAD CURRENT (mA)
120
150
FIGURE 11. LOAD REGULATION (VIN = 4.5V, VOUT = 3.3V)
5V/DIV
VIN
VOUT1 (AC COUPLED)
50mV/DIV
1V/DIV
VOUT1
50mV/DIV
1V/DIV
200mA/DIV
VOUT2
100µs/DIV
FIGURE 12. ENABLE OPERATION (VIN = 3.6V, VOUT1 = VOUT1 = 1.2V)
7
VOUT2 (AC COUPLED)
IOUT1
1ms/DIV
FIGURE 13. LOAD TRANSIENT RESPONSE (VIN = 3.6V,
VOUT1 = VOUT2 = 1.2V, IOUT1 0.01mA TO 150mA)
FN6832.1
May 16, 2011
ISL9016
Typical Operating Performance
5V/DIV
VIN
(Continued)
5V/DIV
VIN
VOUT1 (AC COUPLED)
50mV/DIV
50mV/DIV
VOUT1 (AC COUPLED)
1ms/DIV
VOUT2 (AC COUPLED)
50mV/DIV
50mV/DIV
IOUT1
200mA/DIV
200mA/DIV
VOUT2 (AC COUPLED)
IOUT1
1ms/DIV
1ms/DIV
FIGURE 14. LOAD TRANSIENT RESPONSE (VIN = 3.6V,
VOUT1 = VOUT2 = 1.2V, IOUT2 0.01mA TO 150mA)
FIGURE 15. LOAD TRANSIENT RESPONSE (VIN = 3.6V,
VOUT1 = VOUT2 = 3.3V, IOUT1 0.01mA TO 150mA)
VOUT1 (AC COUPLED)
50mV/DIV
20mV/DIV
100mA/DIV
100mV/DIV
VOUT (AC COUPLED)
VOUT2 (AC COUPLED)
IOUT1
1ms/DIV
di/dt = 150mA/µs
FIGURE 16. LOAD TRANSIENT RESPONSE (VIN = 1.8V,
VOUT1 = VOUT2 = 1.2V, IOUT1 0.01mA TO 150mA)
8
100mA/DIV
IOUT
1ms/DIV
di/dt = 150mA/µs
FIGURE 17. LOAD TRANSIENT RESPONSE (VIN = 3.3V,
VOUT1 = VOUT2 = 1.2V, IOUT1 0.01mA TO 150mA)
FN6832.1
May 16, 2011
ISL9016
Block Diagram
VOUT2
VIN
VOUT1
REVERSE CURRENT
PROTECTION
VIN
VOUT1
EN1
UNDERVOLTAGE
LOCKOUT
EN2
SHORT CIRCUIT
THERMAL PROTECTION
SOFT-START
CONTROL
LOGIC
EN1
VREF1
+
LDO-2
LDO-1
VREF2
VREF1
BANDGAP
TEMP-SENSOR
VREF3
REFERENCE
VOLTAGES
GND
Functional Description
ISL9016 contains two high performance LDO’s. High
performance is achieved through a circuit which delivers fast
transient response to varying load conditions. In a quiescent
condition, the ISL9016 adjusts its biasing to achieve the lowest
standby current consumption.
The device also integrates current limit protection, thermal
shutdown protection, reverse current protection and soft-start.
Thermal shutdown protects the device against overheating.
Soft-start limits the start-up input current surges. In some certain
application circuits, the output voltage may be externally held up,
meanwhile, the input voltage could be connected to ground, or
connected to some voltage lower than the output side, or be left
open circuit. ISL9016 features the reverse current protection; it
can limit the current flow from output to input. This protection will
automatically initiate when VOUT is detected to be higher than VIN.
When VIN is pulled to ground and VOUT is held at 5.5V, the current
flow from VOUT to VIN is typically less than 8µA.
Enable Control
The ISL9016 has two separate enable pins, EN1 and EN2, which
independently enable/disable each of the LDO outputs. When both
EN1 and EN2 are low, the whole device is in shutdown mode. In this
condition, all on-chip circuits are off, and the device draws minimum
current, typically less than 0.1mA. When one or both the EN pins go
high, the LDO1 and/or LDO2 will be enabled accordingly based on
the voltage signal applied on its related EN pin and start from the
soft-start. Likewise, when one or both EN pins go low, LDO1 and/or
LDO2 will be disabled based on the signal applied on its related EN
pin. A 100kΩ (or above) pull-up resistor should be connected
9
between ENx pin and the external control voltage (as shown in the
“Typical Application Diagram” on page 1).
LDO Protections
ISL9016 offers several protections which make it ideal for using
in battery-powered application circuits.
ISL9016 provides short-circuit protection by limiting the output
current to typical 265mA. When short circuit happens, the circuit
is limited at 265mA (typical). If the short circuit lasts long enough,
the die temperature increases, and the over-temperature
protection circuit will turn off the output.
When the die temperature reaches about +145°C, the thermal
protection starts working. Under the overheat condition, only the
LDO sourcing more than 50mA will be shut off. This does not
affect the operation of the other LDO. If both LDOs source more
than 50mA and an overheat condition occurs, both LDO outputs
will be disabled. Once the die temperature falls back to about
+110°C, the disabled LDO(s) are re-enabled and soft-start
automatically takes place.
In certain applications, the following input/output situations may
occur, with output voltage externally held up higher than the input
voltage:
1. Input is pulled to ground;
2. Input is left open circuit; and
3. Input is pulled to some intermediate voltage
ISL9016 provides the reverse current protection to limit the current
flow from output to input under these situations. When input is
pulled to ground and output is held to 5.5V, the typical reverse
current from output to input side is less than 8µA.
FN6832.1
May 16, 2011
ISL9016
Input and Output Capacitors
Board Layout Recommendations
The ISL9016 provides a linear regulator that has low quiescent
current, fast transient response, and overall stability across the
recommended operating conditions. A ceramic capacitor (X5R or
X7R) with a capacitance of 1µF to 4.7µF with an ESR up to 200mΩ
is suitable for the ISL9016 to maintain its output stability. The
ground connection of the output capacitor should be connected
directly to the GND pin of the device, and also placed close to the
device. Similarly for the input capacitor, usually a 1µF ceramic
capacitor (X5R or X7R) is suitable for most cases, but if large, fast
rising-time load transient condition is expected, a higher value
input capacitor may be necessary to achieve better performance.
A good PCB layout will be an important step to achieve good
performance. It is recommended to design the board with
separate ground planes for input and output, and connect both
ground planes at the GND pin of the device. Consideration should
be taken when placing the components and route the trace to
minimize the ground impedance, as well as keep the parasitic
inductance low. Usually the input/output capacitors should be
placed close to the device with good ground connection.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
CHANGE
April 26, 2011
FN6832.1
Added ISL9016IRUCCZ-T to Ordering Information table.
January 22, 2009
FN6832.0
Initial release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL9016
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/sear
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN6832.1
May 16, 2011
ISL9016
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
A
E
6
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
D
1
3
A1
TOP VIEW
e
1.00 REF
4
6
L
CO.2
D2
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.45
0.50
0.55
-
A1
-
-
0.05
-
0.127 REF
A3
0.15 C
3
1
b 6X
0.10 M C A B
E2
0.15
0.20
0.25
-
D
1.55
1.60
1.65
4
D2
0.40
0.45
0.50
-
E
1.55
1.60
1.65
4
E2
0.95
1.00
1.05
-
0.50 BSC
L
0.25
0.30
0.35
Rev. 1 6/06
NOTES:
1. Dimensions are in mm. Angles in degrees.
BOTTOM VIEW
DETAIL A
0.10 C
-
b
e
DAP SIZE 1.30 x 0.76
6X
L6.1.6x1.6A
4
PIN 1
REFERENCE
2X
0.15 C
2X
A
B
2. Coplanarity applies to the exposed pad as well as the terminals.
Coplanarity shall not exceed 0.08mm.
3. Warpage shall not exceed 0.10mm.
4. Package length/package width are considered as special
characteristics.
0.08 C
5. JEDEC Reference MO-229.
A3
SIDE VIEW
C
SEATING
PLANE
6. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
0.127±0.008
0.127 +0.058
-0.008
TERMINAL THICKNESS
A1
DETAIL A
0.25
0.50
1.00
0.45
1.00
2.00
0.30
1.25
LAND PATTERN
11
6
FN6832.1
May 16, 2011
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