DATASHEET

ISL84541, ISL84542, ISL84543, ISL84544
Data Sheet
August 19, 2015
Low-Voltage, Single Supply, Dual SPST,
SPDT Analog Switches
The Intersil ISL84541–ISL84544 devices are precision, dual
analog switches designed to operate from a single +2.7V to
+12V supply. Targeted applications include battery powered
equipment that benefit from the devices’ low power
consumption (5W), low leakage currents (100pA max), and
fast switching speeds (tON = 35ns, tOFF = 25ns). Cell phones,
for example, often face ASIC functionality limitations. The
number of analog input or GPIO pins may be limited and
digital geometries are not well suited to analog switch
performance. This family of parts may be used to “mux-in”
additional functionality while reducing ASIC design risk. Some
of the smallest packages are available alleviating board space
limitations, and making Intersil’s newest line of low-voltage
switches an ideal solution.
The ISL84541/ISL84542/ISL84543 are dual singlepole/single-throw (SPST) devices. The ISL84541 has two
normally open (NO) switches; the ISL84542 has two normally
closed (NC) switches; the ISL84543 has one NO and one NC
switch and can be used as an SPDT. The ISL84544 is a
committed SPDT, which is perfect for use in 2-to-1 multiplexer
applications.
Table 1 summarizes the performance of this family. For higher
performance, pin compatible versions, see the ISL43120 - 22
and ISL43210 datasheet.
TABLE 1. FEATURES AT A GLANCE
ISL84541
ISL84542 ISL84543
ISL84544
NUMBER OF
SWITCHES
2
2
2
1
SW 1 / SW 2
NO / NO
NC / NC
NO / NC
SPDT
3.3V RON
50
50
50
50
3.3V tON / tOFF
50 / 20ns
5V RON
30
5V tON / tOFF
35 / 25ns
35 / 25ns 35 / 25ns
35 / 25ns
8 Ld PDIP,
8 Ld SOIC,
8 Ld SOT-23,
8 Ld MSOP
8 Ld PDIP,
8 Ld SOIC,
8 Ld SOT-23
8 Ld PDIP,
8 Ld SOIC,
6 Ld SOT-23
PACKAGES
50 / 20ns 50 / 20ns
30
30
50 / 20ns
30
Related Literature
Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
1
FN6016.7
Features
• Pb-free Available as an Option
• Drop-in Replacements for MAX4541 - MAX4544,
DG9461, DG9262 - DG9263
• Fully Specified at 3.3V and 5V Supplies
• Pin Compatible with MAX323 - MAX325
• ON Resistance (RON) . . . . . . . . . . . . . . . . . . . . . . . . 30
• RON Matching Between Channels. . . . . . . . . . . . . . . . . . <1
• Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . 5pC (Max)
• Single Supply Operation. . . . . . . . . . . . . . . . . +2.7V to +12V
• Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . . .<5W
• Low Leakage Current (Max at 85oC) . . . . . . . . . . . . 10nA
• Fast Switching Action
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns
• Guaranteed Break-Before-Make (ISL84543/ISL84544
only)
• Minimum 2000V ESD Protection per Method 3015.7
• TTL, CMOS Compatible
• Available in SOT-23 Packaging
Applications
• Battery Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
• Communications Systems
- Military Radios
- PBX, PABX
• Test Equipment
- Ultrasound
- Electrocardiograph
• Heads-Up Displays
• Audio and Video Switching
• Various Circuits
- +3V/+5V DACs and ADCs
- Sample and Hold Circuits
- Digital Filters
- Operational Amplifier Gain Switching Networks
- High Frequency Analog Switching
- High Speed Multiplexing
- Integrator Reset Circuits
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2001-2004, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL84541, ISL84542, ISL84543, ISL84544
Pinouts
(Note 1)
ISL84541 (PDIP, SOIC, MSOP)
TOP VIEW
ISL84541 (SOT-23)
TOP VIEW
NO1 1
8 V+
COM1 2
7 IN1
V+ 2
7 IN1
6 COM2
IN2 3
6 GND
COM2 4
5 NO2
IN2 3
5 NO2
GND 4
ISL84542 (PDIP, SOIC)
TOP VIEW
NC1 1
COM1 2
ISL84542 (SOT-23)
TOP VIEW
NC1 1
7 IN1
V+ 2
7 IN1
IN2 3
6 GND
COM2 4
5 NC2
5 NC2
GND 4
8 COM1
8 V+
6 COM2
IN2 3
8 COM1
NO1 1
ISL84543 (PDIP, SOIC)
TOP VIEW
ISL84543 (SOT-23)
TOP VIEW
NO1 1
8 V+
NO1 1
COM1 2
7 IN1
V+ 2
7 IN1
IN2 3
6 GND
COM2 4
5 NC2
6 COM2
IN2 3
5 NC2
GND 4
ISL84544 (PDIP, SOIC)
TOP VIEW
8 COM1
ISL84544 (SOT-23)
TOP VIEW
NO 1
8 V+
IN 1
6 NO
COM 2
7 IN
V+ 2
5 COM
NC 3
6 NC
GND 4
5 NC
4 NC
GND 3
NOTE:
1. Switches Shown for Logic “0” Input.
Truth Table
Pin Descriptions
ISL84541 ISL84542
ISL84543
ISL84544
PIN
PIN NC PIN NO
V+
FUNCTION
System Power Supply Input (+2.7V to +12V)
LOGIC
SW 1, 2
SW 1, 2
SW 1
SW 2
0
OFF
ON
OFF
ON
ON
OFF
GND
Ground Connection
1
ON
OFF
ON
OFF
OFF
ON
IN
Digital Control Input
NOTE:
Logic “0”  0.8V. Logic “1” 2.4V.
2
COM
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
N.C.
No Internal Connection
ISL84541, ISL84542, ISL84543, ISL84544
Ordering Information
Ordering Information
PACKAGE
(RoHS
Compliant)
PART NO.
(BRAND)
TEMP.
RANGE (oC)
ISL84541CPZ
(Note 2) (No
longer available,
recommended
replacement:
ISL84541CBZ-T)
0 to 70
8 Ld PDIP
ISL84541CBZ
(Note 2)
0 to 70
ISL84541CBZ-T
(Note 2)
TEMP.
RANGE (oC)
E8.3
ISL84542IBZ
(Note 2) (No
longer available,
recommended
replacement:
ISL84541CBZ-T)
-40 to 85
8 Ld SOIC
M8.15
8 Ld SOIC Tape and Reel
M8.15
E8.3
ISL84542IBZ-T
(Note 2) (No
longer available,
recommended
replacement:
ISL84541CBZ-T)
8 Ld SOIC
M8.15
8 Ld SOT-23 Tape and Reel
ISL84542IHZ-T
(542I) (Note 2) (No
longer available,
recommended
replacement:
ISL84541CBZ-T)
8 Ld SOIC Tape and Reel
M8.15
-40 to 85
ISL84541IBZ
(Note 2)
-40 to 85
ISL84541IUZ
(541I) (Note 2) (No
longer available,
recommended
replacement:
ISL84541CBZ-T)
8 Ld PDIP
-40 to 85
8 Ld MSOP
8 Ld MSOP Tape and Reel
ISL84541IUZ-T
(541I) (Note 2) (No
longer available,
recommended
replacement:
ISL84541CBZ-T)
ISL84542CPZ
(Note 2) (No
longer available,
recommended
replacement:
ISL84541CBZ-T)
0 to 70
ISL84542CBZ
(Note 2) (No
longer available,
recommended
replacement:
ISL84541CBZ-T)
0 to 70
ISL84542CBZ-T
(Note 2) (No
longer available,
recommended
replacement:
ISL84541CBZ-T)
ISL84542IPZ
(Note 2) (No
longer available,
recommended
replacement:
ISL84541CBZ-T)
PACKAGE
(RoHS
Compliant)
PART NO.
(BRAND)
ISL84541IPZ
(Note 2) (No
longer available,
recommended
replacement:
ISL84541CBZ-T)
ISL84541IBZ-T
(Note 2)
PKG.
DWG. #
8 Ld PDIP
8 Ld SOIC
8 Ld SOIC Tape and Reel
-40 to 85
8 Ld PDIP
3
M8.118
M8.118
E8.3
M8.15
M8.15
E8.3
PKG.
DWG. #
8 Ld SOIC
M8.15
8 Ld SOIC Tape and Reel
M8.15
P8.064
ISL84543CPZ
(Note 2) (No
longer available,
recommended
replacement:
ISL84544CBZ-T)
0 to 70
8 Ld PDIP
E8.3
ISL84543CBZ
(Note 2) (No
longer available,
recommended
replacement:
ISL84544CBZ-T)
0 to 70
8 Ld SOIC
M8.15
8 Ld SOIC Tape and Reel
M8.15
ISL84543CBZ-T
(Note 2) (No
longer available,
recommended
replacement:
ISL84544CBZ-T)
ISL84543IPZ
(Note 2) (No
longer available,
recommended
replacement:
ISL84544CBZ-T)
-40 to 85
8 Ld PDIP
E8.3
ISL84543IBZ
(Note 2) (No
longer available,
recommended
replacement:
ISL84544CBZ-T)
-40 to 85
8 Ld SOIC
M8.15
8 Ld SOIC Tape and Reel
M8.15
ISL84543IBZ-T
(Note 2) (No
longer available,
recommended
replacement:
ISL84544CBZ-T)
ISL84541, ISL84542, ISL84543, ISL84544
Ordering Information
PART NO.
(BRAND)
TEMP.
RANGE (oC)
PACKAGE
(RoHS
Compliant)
8 Ld SOT-23 Tape and Reel
ISL84543IHZ-T
(543I) (Note 2) (No
longer available,
recommended
replacement:
ISL84544CBZ-T)
PKG.
DWG. #
P8.064
ISL84544CPZ
(Note 2) (No
longer available,
recommended
replacement:
ISL84544CBZ-T)
0 to 70
8 Ld PDIP
E8.3
ISL84544CBZ
(Note 2)
0 to 70
8 Ld SOIC
M8.15
8 Ld SOIC Tape and Reel
M8.15
ISL84544CBZ-T
(Note 2)
ISL84544IPZ
(Note 2) (No
longer available,
recommended
replacement:
ISL84544CBZ-T)
-40 to 85
8 Ld PDIP
E8.3
ISL84544IBZ
(Note 2)
-40 to 85
8 Ld SOIC
M8.15
ISL84544IBZ-T
(Note 2)
8 Ld SOIC Tape and Reel
M8.15
ISL84544IHZ-T
(544I) (Note 2)
6 Ld SOT-23 Tape and Reel
P6.064
NOTE:
2. Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish,
which is compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
4
ISL84541, ISL84542, ISL84543, ISL84544
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V
Input Voltages
IN (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
NO, NC (Note 3) . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 10mA
Peak Current, IN, NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 20mA
ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . .>2kV
Thermal Resistance (Typical, Note 4)
Operating Conditions
Temperature Range
ISL8454XCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
ISL8454XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
JA (oC/W)
6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . .
230
8 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . .
215
8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . .
210
8 LD SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . .
170
8 LD PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . .
140
Maximum Junction Temperature (Plastic Package). . . . . . . . 150oC
Moisture Sensitivity (See Technical Brief TB363)
All Other Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
8 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2
Maximum Storage Temperature Range . . . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC, MSOP and SOT-23 - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. Signals on NC, NO, COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
4. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(oC)
MIN
(NOTE 6)
TYP
Full
0
-
V+
V
25
-
30
60

Full
-
-
75

25
-
0.8
2

Full
-
-
4

MAX
(NOTE 6) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V,
See Figure 5
RON Matching Between Channels,
RON
V+ = 5V, ICOM = 1.0mA, VNO or VNC= 3.5V
RON Flatness, RFLAT(ON)
V+ = 5V, ICOM = 1.0mA, VNO or VNC = 1V, 2V, 3V
Full
-
7
8

NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V,
Note 7
25
-0.1
0.01
0.1
nA
Full
-5
-
5
nA
25
-0.1
-
0.1
nA
Full
-5
-
5
nA
25
-0.2
-
0.2
nA
Full
-10
-
10
nA
COM OFF Leakage Current,
ICOM(OFF)
V+ = 5.5V, VCOM = 4.5V, 1V, VNO or VNC = 1V, 4.5V,
Note 7
COM ON Leakage Current,
ICOM(ON)
V = 5.5V, VCOM = 1V, 4.5V, or VNO or VNC = 1V,
4.5V, or Floating, Note 7
5
ISL84541, ISL84542, ISL84543, ISL84544
Electrical Specifications - 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5),
Unless Otherwise Specified (Continued)
TEST CONDITIONS
TEMP
(oC)
MIN
(NOTE 6)
TYP
25
-
35
100
ns
Full
-
-
240
ns
25
-
25
75
ns
Full
-
-
150
ns
MAX
(NOTE 6) UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
VNO or VNC = 3V, RL =1k, CL = 35pF, VIN = 0 to 3V,
See Figure 1
VNO or VNC = 3V, RL =1k, CL = 35pF, VIN = 0 to 3V,
See Figure 1
Turn-OFF Time, tOFF
Break-Before-Make Time Delay
(ISL84543, ISL84544), tD
RL = 300, CL = 35pF, VNO = VNC = 3V, VIN = 0 to 3V,
See Figure 3
Full
2
10
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0, See Figure 2
25
-
1
5
pC
OFF Isolation
RL = 50, CL = 5pF, f = 1MHz, See Figure 4
25
-
76
-
dB
Crosstalk (Channel-to-Channel)
RL = 50, CL = 5pF, f = 1MHz, See Figure 6
25
-
-90
-
dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7
25
-
8
-
pF
COM OFF Capacitance,
CCOM(OFF)
f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7
25
-
8
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7,
ISL84541/2/3
25
-
13
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7,
ISL84544
25
-
20
-
pF
Full
2.7
12
V
Full
-1
0.0001
1
A
Input Voltage Low, VINL
Full
-
-
0.8
V
Input Voltage High, VINH
Full
2.4
-
-
V
POWER SUPPLY CHARACTERISTICS
Power Supply Range
V+ = 5.5V, VIN = 0V or V+, all channels on or off
Positive Supply Current, I+
DIGITAL INPUT CHARACTERISTICS
NOTES:
5. VIN = input voltage to perform proper function.
6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25oC.
6
ISL84541, ISL84542, ISL84543, ISL84544
Electrical Specifications - 3.3V Supply
PARAMETER
Test Conditions: V+ = +3.0V to +3.6V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(oC)
MIN
(NOTE 6)
TYP
Full
0
-
V+
V
25
-
50
80

Full
-
-
140

25
-
0.8
2

Full
-
-
4

25
-
6
10

Full
-
7
12

25
-0.1
0.01
0.1
nA
Full
-5
-
5
nA
25
-0.1
0.01
0.1
nA
Full
-5
-
5
nA
25
-0.2
-
0.2
nA
Full
-10
-
10
nA
25
-
50
120
ns
200
ns
MAX
(NOTE 6) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V
RON Matching Between Channels,
RON
V+ = 3.3V, ICOM = 1.0mA, VNO or VNC = 1.5V
RON Flatness, RFLAT(ON)
V+ = 3.3V, ICOM = 1.0mA, VNO or VNC = 0.5V,
1V, 1.5V
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 3V, 1V, Note 7
COM OFF Leakage Current,
ICOM(OFF)
V+ = 3.6V, VCOM = 3V, 1V, VNO or VNC = 1V, 3V, Note 7
COM ON Leakage Current,
ICOM(ON)
V = 3.6V, VCOM = 1V, 3V, or VNO or VNC = 1V, 3V,
or floating, Note 7
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
VNO or VNC = 1.5V, RL =1k, CL = 35pF, VIN = 0 to 3V
Full
Turn-OFF Time, tOFF
VNO or VNC = 1.5V, RL =1k, CL = 35pF, VIN = 0 to 3V
25
-
20
50
ns
Full
-
-
120
ns
Break-Before-Make Time Delay
(ISL84543, ISL84544), tD
RL = 300, CL = 35pF, VNO or VNC = 1.5V,
VIN = 0 to 3V
Full
3
30
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0
25
-
1
5
pC
OFF Isolation
RL = 50, CL = 5pF, f = 1MHz
25
-
76
-
dB
Crosstalk (Channel-to-Channel)
25
-
-90
-
dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V
25
-
8
-
pF
COM OFF Capacitance,
CCOM(OFF)
f = 1MHz, VNO or VNC = VCOM = 0V
25
-
8
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V, ISL84541/2/3
25
-
13
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V, ISL84544
25
-
20
-
pF
Full
-1
-
1
A
Input Voltage Low, VINL
Full
-
-
0.8
V
Input Voltage High, VINH
Full
2.4
-
-
V
Full
-1
-
1
A
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 3.6V, VIN = 0V or V+, all channels on or off
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 3.6V, VIN = 0V or V+
7
ISL84541, ISL84542, ISL84543, ISL84544
Test Circuits and Waveforms
3V
LOGIC
INPUT
V+
tr < 20ns
tf < 20ns
50%
0V
tOFF
SWITCH
INPUT VNO
VOUT
NO or NC
SWITCH
INPUT
COM
VOUT
IN
90%
SWITCH
OUTPUT
C
90%
LOGIC
INPUT
0V
CL
35pF
RL
1k
GND
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) -----------------------------R +R
L
FIGURE 1A. MEASUREMENT POINTS
 ON 
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
SWITCH
OUTPUT
VOUT
VOUT
RG
C
VOUT
COM
NO or NC
V+
LOGIC
INPUT
ON
ON
OFF
0V
VG
GND
IN
CL
LOGIC
INPUT
Q = VOUT x CL
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
3V
LOGIC
INPUT
C
0V
VNX
SWITCH
OUTPUT
VOUT1
SWITCH
OUTPUT
VOUT2
COM1
0V
COM2
IN1
tD
RL2
300
IN2
90%
tD
VOUT2 RL1
300
NC2
90%
0V
VOUT1
NO1
LOGIC
INPUT
CL2
35pF
GND
CL includes fixture and stray capacitance.
FIGURE 3A. MEASUREMENT POINTS (ISL84543 ONLY)
8
FIGURE 3B. TEST CIRCUIT (ISL84543 ONLY)
CL1
35pF
ISL84541, ISL84542, ISL84543, ISL84544
Test Circuits and Waveforms (Continued)
V+
C
3V
LOGIC
INPUT
0V
NO
VNX
VOUT
COM
NC
90%
SWITCH
OUTPUT
VOUT
0V
RL
300
IN
GND
LOGIC
INPUT
tD
CL
35pF
CL includes fixture and stray capacitance.
FIGURE 3D. TEST CIRCUIT (ISL84544 ONLY)
FIGURE 3C. MEASUREMENT POINTS (ISL84544 ONLY)
FIGURE 3. BREAK-BEFORE-MAKE TIME
V+
V+
C
C
RON = V1/1mA
SIGNAL
GENERATOR
NO or NC
NO or NC
VNX
INX
0V or 2.4V
1mA
0.8V or 2.4V
COM
COM
ANALYZER
IN
V1
GND
GND
RL
FIGURE 5. RON TEST CIRCUIT
FIGURE 4. OFF ISOLATION TEST CIRCUIT
V+
C
V+
C
SIGNAL
GENERATOR
NO1 or NC1
COM1
50
NO or NC
IN1
0V or 2.4V
COM2
ANALYZER
INX
IN2 0V or 2.4V
NO2 or NC2
GND
0V or 2.4V
IMPEDANCE
ANALYZER
NC
COM
GND
RL
FIGURE 6. CROSSTALK TEST CIRCUIT
9
FIGURE 7. CAPACITANCE TEST CIRCUIT
ISL84541, ISL84542, ISL84543, ISL84544
Detailed Description
The ISL84541–ISL84544 dual analog switches offer precise
switching capability from a single 2.7V to 12V supply with
low on-resistance (30) and high speed operation
(tON = 35ns, tOFF = 25ns). The devices are especially well
suited to portable battery powered equipment thanks to the
low operating supply voltage (2.7V), low power consumption
(5W), low leakage currents (100pA max), and the tiny
SOT-23 packaging. High frequency applications also benefit
from the wide bandwidth, and the very high off isolation and
crosstalk rejection.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and input signal voltages
must remain between V+ and GND. If these conditions cannot
be guaranteed, then one of the following two protection
methods should be employed.
Logic inputs can easily be protected by adding a 1k resistor
in series with the input (see Figure 8). The resistor limits the
input current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
Adding a series resistor to the switch input defeats the
purpose of using a low RON switch, so two small signal diodes
can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
OPTIONAL PROTECTION
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
INX
VNO or NC
VCOM
GND
OPTIONAL PROTECTION
DIODE
their analog voltage limits. Unlike switches with a 13V
maximum supply voltage, the ISL8454X 15V maximum supply
voltage provides plenty of room for the 10% tolerance of 12V
supplies, as well as room for overshoot and noise spikes.
The minimum recommended supply voltage is 2.7V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer to
the electrical specification tables and Typical Performance
curves for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the logic levels to switched V+ and
GND signals to drive the analog switch gate terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes negative
in this configuration.
Logic-Level Thresholds
This switch family is TTL compatible (0.8V and 2.4V) over a
supply range of 3V to 11V (see Figure 15). At 12V the VIH
level is about 2.5V. This is still below the TTL guaranteed
high output minimum level of 2.8V, but noise margin is
reduced. For best results with a 12V supply, use a logic
family the provides a VOH greater than 3V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 5systems, signal response is reasonably flat even past
300MHz (see Figure 16). Figure 16 also illustrates that the
frequency response is very consistent over a wide V+ range,
and for varying analog signal levels.
An off switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off Isolation is
the resistance to this feedthrough, while Crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 17 details the high Off Isolation and Crosstalk
rejection provided by this family. At 10MHz, off isolation is
about 50dB in 5systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
impedances decrease Off Isolation and Crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.
Leakage Considerations
Power-Supply Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND.
One of these diodes conducts if any analog signal exceeds
V+ or GND.
The ISL8454X construction is typical of most CMOS analog
switches, except that they have only two supply pins: V+ and
GND. V+ and GND drive the internal CMOS switches and set
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
FIGURE 8. OVERVOLTAGE PROTECTION
10
ISL84541, ISL84542, ISL84543, ISL84544
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog-signal
paths and V+ or GND.
Typical Performance Curves TA = 25oC, Unless Otherwise Specified
45
40
V+ = 3.3V
40
35
35
30
20
25oC
-40oC
15
30
25
V+ = 5V
85oC
25oC
-40oC
20
15
-40oC
10
25oC
20
25
15
85oC
25
85oC
RON ()
RON ()
30
10
20
85oC
15
5
3
4
5
6
7
8
V+ (V)
9
10
11
12
10
13
5
V+ = 3.3V
4
6
VCOM (V)
8
10
12
50
85oC
0.1
0
0.25
0.2
0.15
40
-40oC
30
V+ = 5V
25oC
0.1
Q (pC)
RON ()
2
60
25oC
0.2
85oC
85oC
0.05
0
0.15
V+ = 12V
85oC
25oC
-40oC
0
V+ = 5V
2
4
6
8
10
VCOM (V)
FIGURE 11. RON MATCH vs SWITCH VOLTAGE
11
V+ = 12V
V+ = 3.3V
0
25oC
-40oC
0.05
20
10
-40oC
0.1
0
-40oC
0
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE
0.5
0.4
0.3
V+ = 12V
25oC
12
-10
-20
0
2
4
6
VCOM (V)
8
10
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
12
ISL84541, ISL84542, ISL84543, ISL84544
Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued)
100
35
90
80
30
85oC
60
tOFF (ns)
85oC
50
25
-40oC
-40oC
40
20
-40oC
25oC
30
20
25oC
2
3
4
5
6
7
V+ (V)
8
9
10
11
15
12
FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE
NORMALIZED GAIN (dB)
2.5
VINH AND VINL (V)
VINH
-40oC
85oC
4
5
6
7
V+ (V)
8
9
10
11
12
V+ = 3.3V to 12V
0
GAIN
-3
-6
0
PHASE
20
25oC
1.5
85oC
40
-40oC
60
25oC
1.0
RL = 50
VIN = 0.2VP-P to 2.5VP-P (V+ = 3.3V)
VIN = 0.2VP-P to 4VP-P (V+ = 5V)
VIN = 0.2VP-P to 5VP-P (V+ = 12V)
VINL
85oC
0.5
2
3
4
5
6
7
8
V+ (V)
9
10
11
12
13
1
10
80
100
100
FREQUENCY (MHz)
FIGURE 15. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
-10
FIGURE 16. FREQUENCY RESPONSE
10
V+ = 3V to 13V
-20
20
Die Characteristics
-30
30
SUBSTRATE POTENTIAL (POWERED UP):
-40
40
-50
50
-60
60
ISOLATION
-70
70
-80
80
-90
CROSSTALK
-100
-110
1k
90
100
10k
100k
1M
10M
110
100M 500M
FREQUENCY (Hz)
FIGURE 17. CROSSTALK AND OFF ISOLATION
12
GND
OFF ISOLATION (dB)
CROSSTALK (dB)
3
FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE
3.0
2.0
2
TRANSISTOR COUNT:
ISL84541: 66
ISL84542: 66
ISL84543: 66
ISL84544: 58
PROCESS:
Si Gate CMOS
600
PHASE (DEGREES)
tON (ns)
70
ISL84541, ISL84542, ISL84543, ISL84544
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
August 19, 2015
FN6016.7
CHANGE
- Ordering Information Table on page 3.
- Added Revision History.
- Added About Intersil Verbiage.
*Updated POD M8.118 to most recent revision, changes are as follows:
-Revision 2 to Revision 3 Changes:
Updated to new intersil format by adding land pattern and moving dimensions from table onto drawing
-Revision 3 to Revision 4 Changes:
Corrected lead width dimension in side view 1 from "0.25 - 0.036" to "0.25 - 0.36"
*Updated POD M8.15 to most current revision with changes as follows:
-Revision 0 to Revision 1 Changes:
POD created from MCOL M8.15
-Revision 1 to Revision 2 Changes:
Updated to new POD format by removing table and moving dimensions onto drawing and adding land
pattern
-Revision 2 to Revision 3 Changes:
Changed Note 1 "1982" to "1994"
Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
-Revision 3 to Revision 4 Changes:
Changed Note 1 "1982" to "1994"
*Updated POD P6.064 to most current revision with changes as follows:
Updated to new format (same dimensions, added land pattern and moved dimensions from table onto
drawing)
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at
www.intersil.com/support
13
ISL84541, ISL84542, ISL84543, ISL84544
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
SEATING
PLANE
A2
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
0.204
C
D
0.355
0.400
9.01
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
eB
-
L
0.115
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
14
5
D1
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
0.355
10.16
N
8
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
8
6
10.92
7
3.81
4
9
Rev. 0 12/93
ISL84541, ISL84542, ISL84543, ISL84544
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.36
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
15
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
ISL84541, ISL84542, ISL84543, ISL84544
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
16
ISL84541, ISL84542, ISL84543, ISL84544
Package Outline Drawing
P6.064
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 4, 2/10
0-8°
1.90
0.95
0.08-0.22
D
A
6
5
4
2.80
PIN 1
INDEX AREA
1.60 +0.15/-0.10
3
3
(0.60)
1
2
3
0.20 C
2x
0.40 ±0.10
B
SEE DETAIL X
3
0.20 M C A-B D
END VIEW
TOP VIEW
10° TYP
(2 PLCS)
2.90 ±0.10
3
1.15 +0.15/-0.25
C
0.10 C
SEATING PLANE
0.00-0.15
SIDE VIEW
(0.25)
GAUGE
PLANE
1.45 MAX
DETAIL "X"
0.45±0.1
4
(0.95)
(0.60)
(1.20)
(2.40)
TYPICAL RECOMMENDED LAND PATTERN
17
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3.
Dimension is exclusive of mold flash, protrusions or gate burrs.
4.
Foot length is measured at reference to guage plane.
5.
Package conforms to JEDEC MO-178AB.
ISL84541, ISL84542, ISL84543, ISL84544
Small Outline Transistor Plastic Packages (SOT23-8)
0.20 (0.008) M
CL
C
P8.064
VIEW C
8 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
e
b
INCHES
SYMBOL
8
6
7
5
CL
CL
E
1
2
3
E1
4
e1
C
D
CL
A
A2
A1
SEATING
PLANE
-C-
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.036
0.057
0.90
1.45
-
A1
0.000
0.0059
0.00
0.15
-
A2
0.036
0.051
0.90
1.30
-
b
0.009
0.015
0.22
0.38
-
b1
0.009
0.013
0.22
0.33
c
0.003
0.009
0.08
0.22
6
c1
0.003
0.008
0.08
0.20
6
D
0.111
0.118
2.80
3.00
3
E
0.103
0.118
2.60
3.00
-
E1
0.060
0.067
1.50
1.70
3
e
0.0256 Ref
0.65 Ref
-
e1
0.0768 Ref
1.95 Ref
-
L
0.10 (0.004) C
MIN
0.014
0.022
0.35
0.55
L1
0.024 Ref.
0.60 Ref.
L2
0.010 Ref.
0.25 Ref.
N
8
8
5
WITH
b
R
0.004
-
0.10
-
PLATING
b1
R1
0.004
0.010
0.10
0.25

0o
8o
0o
8o
c
c1
4
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC-74 and JEDEC MO178BA.
4X 1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
4. Footlength L measured at reference to gauge plane.
R1
5. “N” is the number of terminal positions.
R
GAUGE PLANE
SEATING
PLANE
L
C
L1

6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
L2
4X 1
VIEW C
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
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