DATASHEET

DATASHEET
2.5A Regulator with Integrated High-side MOSFET for
Synchronous Buck or Boost Buck Converter
ISL85403
Features
The ISL85403 is a 40V, 2.5A synchronous buck or boost buck
controller with a high-side MOSFET and low-side driver
integrated. In buck mode, the ISL85403 supports a wide input
range of 3V to 40V. In boost-buck mode, the input range can
be extended down to 2.5V and output regulation can be
maintained when VIN drops below VOUT, enabling sensitive
electronics to remain on in low input voltage conditions.
• Buck mode: input voltage range 3V to 40V (refer to “Input
Voltage” on page 15 for more details)
The ISL85403 has a flexible selection of operation modes of
forced PWM mode and PFM mode. In PFM mode, the
quiescent input current is as low as 180µA (AUXVCC connected
to VOUT). The load boundary between PFM and PWM can be
programmed to cover wide applications.
The low-side driver can be either used to drive an external low-side
MOSFET for a synchronous buck or left unused for a standard
non-synchronous buck. The low-side driver can also be used to
drive a boost converter as a preregulator followed by a buck
controlled by the same IC, which greatly expands the operating
input voltage range down to 2.5V or lower (Refer to “Typical
Application Schematic III - Boost Buck Converter” on page 6).
The ISL85403 offers the most robust current protections. It uses
peak current mode control with cycle-by-cycle current limiting.
It is implemented with frequency foldback under current limit
condition; also, the hiccup overcurrent mode is also
implemented to guarantee reliable operations under harsh
short conditions.
The ISL85403 has comprehensive protections against various
faults including overvoltage and over-temperature protections,
etc.
Related Literature
• Boost mode expands operating input voltage lower than
2.5V (refer to “Input Voltage” on page 15 for more details)
• Selectable forced PWM mode or PFM mode
• 300µA IC quiescent current (PFM, no load); 180µA input
quiescent current (PFM, no load, VOUT tied to AUXVCC)
• Less than 5µA (MAX) shutdown input current (IC disabled)
• Operational topologies
- Synchronous buck
- Non-synchronous buck
- Two-stage boost buck
- Non-inverting single inductor buck boost
• Programmable frequency from 200kHz to 2.2MHz and
frequency synchronization capability
• ±1% tight voltage regulation accuracy
• Reliable overcurrent protection
- Temperature compensated current sense
- Cycle-by-cycle current limiting with frequency foldback
- Hiccup mode for worst case short condition
• 20 Ld 4x4 QFN package
• Pb-free (RoHS compliant)
Applications
• General purpose
• 24V bus power
• AN1960, “ISL85403DEMO1Z Demonstration Board User
Guide”
• Battery power
• UG010, “ISL85403EVAL2Z Evaluation Board User Guide”
• Embedded processor and I/O supplies
• Point-of-load
100
95
VIN
SYNC
AUXVCC
VCC
VIN
BOOT
ISL85403
ISL85403
PHASE
ILIMIT
LGATE
SS
PGND
EXT_BOOST
FS
SGND
FB
COMP
6V VIN
90
V OUT
EFFICIENCY (%)
PGOOD
EN
MODE
85
12V VIN
80
36V VIN
75
24V VIN
70
65
60
55
50
0.1m
1m
10m
100m
1.0
2.5
LOAD CURRENT (A)
FIGURE 1. TYPICAL APPLICATION
March 13, 2015
FN8631.1
1
FIGURE 2. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
VOUT 5V, TA = +25°C
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL85403
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Application Schematic I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Application Schematic II - VCC Switchover to VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Application Schematic III - Boost Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PFM Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous and Non-Synchronous Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUXVCC Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-Stage Boost Buck Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator and Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
14
14
14
14
15
15
15
15
16
17
18
Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
18
18
Component Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitors - Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitors - Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor - Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-side Power MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Feedback Resistor Divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boost Inductor (2-Stage Boost Buck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boost Output Capacitor (2-Stage Boost Buck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
19
19
19
19
19
19
Loop Compensation Design - Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Comparator Gain Fm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sampling Transfer Function He(S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Stage Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
20
20
Loop Compensation Design for 2-Stage Boost Buck and Single-stage Buck Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Layout Suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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2
FN8631.1
March 13, 2015
ISL85403
Pin Configuration
EN
1
FS
2
AUXVCC
VCC
SGND
VIN
VIN
ISL85403
(20 LD QFN)
TOP VIEW
20
19
18
17
16
PAD
Thermal
Pad
21
15
BOOT
14
PGND
13
LGATE
SYNC
COMP
11
EXT_BOOST
6
7
8
9
10
PHASE
12
5
PHASE
4
PGOOD
FB
MODE
3
ILIMIT
SS
Functional Pin Descriptions
PIN NAME
PIN #
EN
1
The controller is enabled when this pin is left floating or pulled HIGH. The IC is disabled when this pin is pulled LOW.
Range: 0V to 5.5V.
FS
2
Connecting this pin to VCC, or GND, or leaving it open will force the IC to have 500kHz switching frequency. The oscillator switching
frequency can also be programmed by adjusting the resistor from this pin to GND.
SS
3
Connect a capacitor from this pin to ground. This capacitor, along with an internal 5µA current source, sets the soft-start interval of
the converter. Also, this pin can be used to track a ramp on this pin.
FB
4
This pin is the inverting input of the voltage feedback error amplifier. With a properly selected resistor divider connected from VOUT
to FB, the output voltage can be set to any voltage between the power rail (reduced by maximum duty cycle and voltage drop) and
the 0.8V reference. Loop compensation is achieved by connecting an RC network across COMP and FB. The FB pin is also monitored
for overvoltage events.
COMP
5
Output of the voltage feedback error amplifier.
ILIMIT
6
Programmable current limit pin. With this pin connected to the VCC pin, or to GND, or left open, the current limiting threshold is set
to default of 3.6A; the current limiting threshold can be programmed with a resistor from this pin to GND.
MODE
7
Mode selection pin. Pull this pin to GND for forced PWM mode; to have it floating or connected to VCC will enable PFM mode when
the peak inductor current is below the default threshold of 700mA. The current boundary threshold between PFM and PWM can
also be programmed with a resistor at this pin to ground. Check for more details in the “PFM Mode Operation” on page 14.
PGOOD
8
PGOOD is an open-drain output and pull-up pin with a resistor to VCC for proper function. PGOOD will be pulled low under the events
when the output is out of regulation (OV or UV) or EN pin is pulled low. PGOOD rising has a fixed 128 cycles delay.
PHASE
EXT_BOOST
DESCRIPTION
9, 10 These pins are the PHASE nodes that should be connected to the output inductor. These pins are connected to the source of the
high-side N-channel MOSFET.
11
This pin is used to set boost mode and monitor the battery voltage that is the input of the boost converter. After VCC POR, the
controller will detect the voltage on this pin; if voltage on this pin is below 200mV, the controller is set in
synchronous/non-synchronous buck mode and will latch in this state unless VCC is below POR falling threshold; if the voltage on
this pin after VCC POR is above 200mV, the controller is set in boost mode and latch in this state. In boost mode, the low-side driver
output PWM with same duty cycle with upper-side driver to drive the boost switch.
In boost mode, this pin is used to monitor input voltage through a resistor divider. By setting the resistor divider, the high threshold
and hysteresis can be programmed. When voltage on this pin is above 0.8V, the PWM output (LGATE) for the boost converter is
disabled, and when voltage on this pin is below 0.8V minus the hysteresis, the boost PWM is enabled.
In boost mode operation, PFM is disabled when boost PWM is enabled. Check the “2-Stage Boost Buck Converter Operation” on
page 16 for more details.
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March 13, 2015
ISL85403
Functional Pin Descriptions
(Continued)
PIN NAME
PIN #
DESCRIPTION
SYNC
12
This pin can be used to synchronize two or more ISL85403 controllers. Multiple ISL85403s can be synchronized with their SYNC
pins connected together. 180° phase shift is automatically generated between the master and slave ICs.
The internal oscillator can also lock to an external frequency source applied on this pin with square pulse waveform (with frequency
10% higher than the IC’s local frequency, and pulse width higher than 150ns). Range: 0V to 5.5V.
This pin should be left floating if not used.
LGATE
13
In synchronous buck mode, this pin is used to drive the lower side MOSFET to improve efficiency. A 5.1k or smaller value resistor
has to be added to connect LGATE to ground to avoid falsely turn-on of LGATE caused by coupling noise.
In non-synchronous buck when a diode is used as the bottom side power device, this pin should be connected to VCC through a
resistor (less than 5k) before IC start-up to have the low-side driver (LGATE) disabled.
In boost mode, it can be used to drive the boost power MOSFET. The boost control PWM is same with the buck control PWM.
PGND
14
This pin is used as the ground connection of the power flow including driver. Connect it to large ground plane.
BOOT
15
This pin provides bias voltage to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive the
internal N-channel MOSFET. The boot charge circuitries are integrated inside of the IC. No external boot diode is needed. A 1µF
ceramic capacitor is recommended to be used between BOOT and PHASE pin.
VIN
16, 17 Connect the input rail to these pins that are connected to the drain of the integrated high-side MOSFET as well as the source for the
internal linear regulator that provides the bias of the IC. Range: 3V to 40V.
With the part switching, the operating input voltage applied to the VIN pins must be under 40V. This recommendation allows for
short voltage ringing spikes (within a couple of ns time range) due to switching while not exceeding “Absolute Maximum Ratings”
on page 7.
SGND
18
This pin provides the return path for the control and monitor portions of the IC. Connect it to a quiet ground plane.
VCC
19
This pin is the output of the internal linear regulator that supplies the bias for the IC including the driver. A minimum 4.7µF
decoupling ceramic capacitor is recommended between VCC to ground.
AUXVCC
20
This pin is the input of the auxiliary internal linear regulator, which can be supplied by the regulator output after power-up. With
such configuration, the power dissipation inside of the IC is reduced. The input range for this LDO is 3V to 20V.
In boost mode operation, this pin works as boost output overvoltage detection pin. It detects the boost output through a resistor
divider. When voltage on this pin is above 0.8V, the boost PWM is disabled; and when voltage on this pin is below 0.8V minus the
hysteresis, the boost PWM is enabled.
Range: 0V to 20V.
PAD
-
Bottom thermal pad. It is not connected to any electrical potential of the IC. In layout it must be connected to PCB ground copper
plane with area as large as possible to effectively reduce the thermal impedance.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP.
RANGE (°C)
-40 to +105
PACKAGE
(RoHS Compliant)
ISL85403FRZ
85 403FRZ
20 Ld 4x4 QFN
ISL85403DEMO1Z
Compact size demo board for SYNC buck
ISL85403EVAL2Z
Evaluation Board for non-inverting buck-boost configuration
PKG. DWG. #
L20.4x4C
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL85403. For more information on MSL please see techbrief TB363.
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FN8631.1
March 13, 2015
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Block Diagram
AUXVCC
VCC
PGOOD
VIN (x2)
VIN
CURRENT
MONITOR
AUXILARY LDO
BIAS LDO
5
ILIMIT
POWER-ON
RESET
SGND
VCC
BOOT
OCP, OVP, OTP
PFM LOGIC
BOOST MODE CONTROL
EN
EXT_BOOST
PFM/FPWM
PHASE (x2)
GATE DRIVE
VOLTAGE
MONITOR
SYNC
FS
SLOPE
COMPENSATION
LGATE
OSCILLATOR
+
SOFT-START
LOGIC
VCC
BOOT REFRESH
0.8V
REFERENCE
5 µA
EA
SS
+
FB
COMPARATOR
COMP
PGND
ISL85403
MODE
FN8631.1
March 13, 2015
ISL85403
Typical Application Schematic I
PGOOD
EN
MODE
SYNC
AUXVCC
VCC
PGOOD
EN
MODE
VIN
VIN
SYNC
AUXVCC
BOOT
ISL85403
V OUT
PHASE
VCC
ILIMIT
VIN
VIN
BOOT
ISL85403
V OUT
PHASE
ILIMIT
LGATE
SS
LGATE
SS
PGND
PGND
EXT_BOOST
FS
SGND
EXT_BOOST
FS
SGND
FB
COMP
FB
COMP
(b) NON-SYNCHRONOUS BUCK
(a) SYNCHRONOUS BUCK
Typical Application Schematic II - VCC Switchover to VOUT
PGOOD
EN
MODE
SYNC
AUXVCC
VCC
PGOOD
EN
MODE
VIN
VIN
SYNC
AUXVCC
BOOT
ISL85403
VCC
V OUT
PHASE
BOOT
ISL85403
V OUT
PHASE
ILIMIT
ILIMIT
LGATE
SS
VIN
VIN
LGATE
SS
PGND
PGND
EXT_BOOST
FS
SGND
EXT_BOOST
FS
SGND
FB
COMP
(a) SYNCHRONOUS BUCK
FB
COMP
(b) NON-SYNCHRONOUS BUCK
Typical Application Schematic III - Boost Buck Converter
Battery
+
+
R1
R2
PGOOD
EN
MODE
EXT_BOOST
PGOOD
EN
R3
LGATE
AUXVCC
SYNC
VCC
1M
VCC
ILIMIT
ISL85403
BOOT
PHASE
SS
V OUT
VIN
ISL85403
BOOT
COMP
FB
(a) 2-STAGE BOOST BUCK
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6
V OUT
PHASE
PGND
LGATE
PGND
SGND
VIN
SS
FS
FS
130k
AUXVCC
SYNC
R4
VIN
ILIMIT
EXT_BOOST
VCC
SGND
COMP
FB
(b) NON-INVERTING SINGLE INDUCTOR BUCK BOOST
FN8631.1
March 13, 2015
ISL85403
Absolute Maximum Ratings
Thermal Information
VIN, PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +44V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +6.0V
AUXVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +22V
Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +50.0V
Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . +6.0V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . . 1kV
Latch-up Rating (Tested per JESD78B; Class II, Level A) . . . . . . . . . 100mA
Thermal Resistance
JA (°C/W) JC (°C/W)
QFN 4x4 Package (Notes 4, 5). . . . . . . . . . . . . . .
40
3.5
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Supply Voltage on VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 40V
AUXVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Refer to “Block Diagram” on page 5 and “Typical Application Schematics” on page 6. Operating Conditions
Unless Otherwise Noted: VIN = 12V, or VCC = 4.5V ±10%, TA = -40°C to +105°C. Typicals are at TA = +25°C. Boldface limits apply across the operating
temperature range, -40°C to +105°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
VIN PIN SUPPLY
VIN Pin Voltage Range
Operating Supply Current
IQ
Shutdown Supply Current
IIN_SD
VIN Pin
3.05
40
V
VIN Pin connected to VCC
3.05
5.5
V
MODE = VCC/FLOATING (PFM), no load at the
output
300
µA
MODE = GND (forced PWM), VIN = 12V,
IC operating, not including driving current
1.3
mA
EN connected to GND, VIN = 12V
2.8
4.5
µA
4.5
4.8
V
0.3
0.52
V
0.25
0.42
V
INTERNAL MAIN LINEAR REGULATOR
MAIN LDO VCC Voltage
VCC
MAIN LDO Dropout Voltage
VIN > 5V
4.2
VDROPOUT_MAIN VIN = 4.2V, IVCC = 35mA
VIN = 3V, IVCC = 25mA
VCC Current Limit of MAIN LDO
60
mA
INTERNAL AUXILIARY LINEAR REGULATOR
AUXVCC Input Voltage Range
VAUXVCC
AUX LDO VCC Voltage
VCC
LDO Dropout Voltage
3
VAUXVCC > 5V
4.2
VDROPOUT_AUX VAUXVCC = 4.2V, IVCC = 35mA
VAUXVCC = 3V, IVCC = 25mA
Current Limit of AUX LDO
20
V
4.5
4.8
V
0.3
0.52
V
0.25
0.42
V
60
mA
AUX LDO Switchover Rising Threshold
VAUXVCC_RISE
AUXVCC voltage rise; Switch to auxiliary LDO
2.97
3.1
3.2
V
AUX LDO Switchover Falling Threshold Voltage
VAUXVCC_FALL
AUXVCC voltage fall; Switch back to main BIAS
LDO
2.73
2.87
2.97
V
AUX LDO Switchover Hysteresis
VAUXVCC_HYS
AUXVCC switchover hysteresis
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7
0.2
V
FN8631.1
March 13, 2015
ISL85403
Electrical Specifications
Refer to “Block Diagram” on page 5 and “Typical Application Schematics” on page 6. Operating Conditions
Unless Otherwise Noted: VIN = 12V, or VCC = 4.5V ±10%, TA = -40°C to +105°C. Typicals are at TA = +25°C. Boldface limits apply across the operating
temperature range, -40°C to +105°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
2.82
2.9
3.05
2.8
MAX
(Note 6) UNITS
POWER-ON RESET
Rising VCC POR Threshold
VPORH_RISE
Falling VCC POR Threshold
VPORL_FALL
2.6
VCC POR Hysteresis
VPORL_HYS
0.3
V
V
V
ENABLE
Enable On Voltage
VENH
Enable Off voltage
VENL
EN Pull-up Current
IEN_PULLUP
1.7
V
1
V
VEN = 1.2V, VIN = 24V
1.5
µA
VEN = 1.2V, VIN = 12V
1.2
µA
VEN = 1.2V, VIN = 5V
0.9
µA
OSCILLATOR
PWM Frequency
FOSC
RT = 665kΩ
160
200
240
kHz
RT = 51.1kΩ
1870
2200
2530
kHz
FS pin connected to VCC or floating or GND
450
500
550
kHz
MIN ON Time
tMIN_ON
130
225
ns
MIN OFF Time
tMIN_OFF
210
330
ns
Input High Threshold
VIH
2
Input Low Threshold
VIL
SYNCHRONIZATION
V
0.5
V
Input Minimum Pulse Width
25
ns
Input Impedance
100
kΩ
Input Minimum Frequency Divided by Free
Running Frequency
1.1
Input Maximum Frequency Divided by Free
Running Frequency
1.6
CSYNC = 100pF
Output Pulse Width
RLOAD = 1kΩ
100
ns
VCC-0.25
V
Output Pulse High
VOH
Output Pulse Low
VOL
GND
V
VREF
0.8
V
REFERENCE VOLTAGE
Reference Voltage
System Accuracy
-1.0
FB Pin Source Current
+1.0
5
%
nA
Soft-start
Soft-start Current
ISS
3
5
7
µA
ERROR AMPLIFIER
Unity Gain-bandwidth
CLOAD = 50pF
DC Gain
CLOAD = 50pF
10
MHz
88
dB
Maximum Output Voltage
3.6
V
Minimum Output Voltage
0.5
V
5
V/µs
Slew Rate
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SR
8
CLOAD = 50pF
FN8631.1
March 13, 2015
ISL85403
Electrical Specifications
Refer to “Block Diagram” on page 5 and “Typical Application Schematics” on page 6. Operating Conditions
Unless Otherwise Noted: VIN = 12V, or VCC = 4.5V ±10%, TA = -40°C to +105°C. Typicals are at TA = +25°C. Boldface limits apply across the operating
temperature range, -40°C to +105°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
PFM MODE CONTROL
Default PFM Current Threshold
MODE = VCC or floating
700
mA
Limits apply for +25°C only
127
LGate Source Resistance
100mA source current
3.5
Ω
LGATE Sink Resistance
100mA sink current
2.8
Ω
INTERNAL HIGH-SIDE MOSFET
Upper MOSFET rDS(ON)
rDS(ON)_UP
140
mΩ
LOW-SIDE MOSFET GATE DRIVER
BOOST CONVERTER CONTROL
EXT_BOOST Boost_Off Threshold Voltage
EXT_BOOST Hysteresis Sink Current
IEXT_BOOST_HYS
AUXVCC Boost Turn-Off Threshold Voltage
AUXVCC Hysteresis Sink Current
IAUXVCC_HYS
0.74
0.8
0.86
V
2.1
3.2
4.2
µA
0.74
0.8
0.86
V
2.1
3.2
4.2
µA
104
110
116
%
POWER-GOOD MONITOR
Overvoltage Rising Trip Point
VFB/VREF
Percentage of reference point
Overvoltage Rising Hysteresis
VFB/VOVTRIP
Percentage below OV trip point
Undervoltage Falling Trip Point
VFB/VREF
Percentage of reference point
Undervoltage Falling Hysteresis
VFB/VUVTRIP
Percentage above UV trip point
PGOOD Rising Delay
3
84
tPGOOD_R_DELAY
PGOOD Leakage Current
PGOOD HIGH, VPGOOD = 4.5V
90
%
96
%
3
%
128
cycle
10
nA
0.10
V
VPGOOD
PGOOD LOW, IPGOOD = 0.2mA
Default Cycle-by-cycle Current Limit Threshold
IOC_1
ILIMIT = GND or VCC or floating
Hiccup Current Limit Threshold
IOC_2
Hiccup, IOC_2/IOC_1
115
%
OV 120% Trip Point
Active in and after soft-start.
Percentage of reference point
LG = UG = LOW
120
%
OV 120% Release Point
Active in and after soft-start.
Percentage of reference point
102.5
%
OV 110% Trip Point
Active after soft-start done.
Percentage of reference point
LG = UG = LOW
110
%
OV 110% Release Point
Active after soft-start done.
Percentage of reference point
102.5
%
Over-temperature Trip Point
160
°C
Over-temperature Recovery Threshold
140
°C
PGOOD Low Voltage
OVERCURRENT PROTECTION
3
3.6
4.2
A
OVERVOLTAGE PROTECTION
OVER-TEMPERATURE PROTECTION
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
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FN8631.1
March 13, 2015
ISL85403
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
0.0
100
95
24V VIN
12V VIN
6V VIN
90
36V VIN
EFFICIENCY (%)
EFFICIENCY (%)
Typical Performance Curves
6V VIN
12V VIN
85
80
36V VIN
75
24V VIN
70
65
60
55
0.5
1.0
1.5
2.0
50
0.1m
2.5
1m
10m
FIGURE 3. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM
MODE, 500kHz, VOUT 5V, TA = +25°C
5.200
5.150
5.150
2.5
5.100
IO = 0A
5.050
VOUT (V)
VOUT (V)
5.100
5.000
4.950
4.900
IO = 1A
4.850
5
10
15
12V VIN
4.950
36V VIN
6V VIN
4.850
30
35
40
4.800
0
0.5
1.0
1.5
LOAD CURRENT (A)
2.0
2.5
FIGURE 6. LOAD REGULATION, VOUT 5V, TA = +25°C
100
95
90
12V VIN
85
24V VIN
EFFICIENCY (%)
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
0.0
24V VIN
5.000
4.900
IO = 2A
20
25
INPUT VOLTAGE (V)
5.050
FIGURE 5. LINE REGULATION, VOUT 5V, TA = +25°C
EFFICIENCY (%)
1.0
FIGURE 4. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
VOUT 5V, TA = +25°C
5.200
4.800
100m
LOAD CURRENT (A)
LOAD CURRENT (A)
36V VIN
6V VIN
6V VIN
12V VIN
80
36V VIN
75
24V VIN
70
65
60
55
50
45
0.5
1.0
1.5
2.0
LOAD CURRENT (A)
FIGURE 7. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM
MODE, 500kHz, VOUT 3.3V, TA = +25°C
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10
2.5
40
0.1m
1m
10m
100m
LOAD CURRENT (A)
1.0
2.5
FIGURE 8. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
VOUT 3.3V, TA = +25°C
FN8631.1
March 13, 2015
ISL85403
Typical Performance Curves (Continued)
200
180
VIN = 12V
INPUT CURRENT (µA)
160
VOUT 2V/DIV
140
120
VIN = 24V
100
80
PHASE 20V/DIV
60
40
20
0
-50
-25
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 9. INPUT QUIESCENT CURRENT UNDER NO LOAD,
PFM MODE, VOUT = 5V
2ms/DIV
FIGURE 10. SYNCHRONOUS BUCK MODE, VIN 36V, IO 2A,
ENABLE ON
VOUT 2V/DIV
VOUT 2V/DIV
PHASE 20V/DIV
PHASE 20V/DIV
2ms/DIV
FIGURE 11. SYNCHRONOUS BUCK MODE, VIN 36V, IO 2A,
ENABLE OFF
2ms/DIV
FIGURE 12. VIN 36V, PREBIASED START-UP
VOUT 20mV/DIV (5V OFFSET)
VOUT 100mV/DIV (5V OFFSET)
IOUT 1A/DIV
PHASE 20V/DIV
PHASE 20V/DIV
5µs/DIV
FIGURE 13. SYNCHRONOUS BUCK WITH FORCE PWM MODE,
VIN 36V, IO 2A
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11
1ms/DIV
FIGURE 14. VIN 24V, 0 TO 2A STEP LOAD, FORCE PWM MODE
FN8631.1
March 13, 2015
ISL85403
Typical Performance Curves (Continued)
VOUT 200mV/DIV (5V OFFSET)
VOUT 70mV/DIV (5V OFFSET)
VOUT 1V/DIV
LGATE 5V/DIV
LGATE 5V/DIV
IOUT 1A/DIV
PHASE 20V/DIV
PHASE 20V/DIV
100µs/DIV
1ms/DIV
FIGURE 15. VIN 24V, 80mA LOAD, PFM MODE
FIGURE 16. VIN 24V, 0 TO 2A STEP LOAD, PFM MODE
VOUT 10mV/DIV (5V OFFSET)
VOUT 10mV/DIV (5V OFFSET)
PHASE 5V/DIV
PHASE 10V/DIV
20µs/DIV
5µs/DIV
FIGURE 17. NON-SYNCHRONOUS BUCK, FORCE PWM MODE,
VIN 12V, NO LOAD
VOUT BUCK 100mV/DIV (5V OFFSET)
FIGURE 18. NON-SYNCHRONOUS BUCK, FORCE PWM MODE,
VIN 12V, 2A
VOUT BUCK 100mV/DIV (5V OFFSET)
VIN_BOOST_INPUT 5V/DIV
VIN_BOOST_INPUT 5V/DIV
PHASE_BOOST 10V/DIV
PHASE_BUCK 10V/DIV
PHASE_BOOST 10V/DIV
PHASE_BUCK 10V/DIV
20ms/DIV
FIGURE 19. BOOST BUCK MODE, BOOST INPUT STEP FROM 36V TO
3V, VOUT BUCK = 5V, IOUT_BUCK = 1A
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10ms/DIV
FIGURE 20. BOOST BUCK MODE, BOOST INPUT STEP FROM
3V TO 36V, VOUT BUCK = 5V, IOUT_BUCK = 1A
FN8631.1
March 13, 2015
ISL85403
Typical Performance Curves (Continued)
95
VOUT 5V/DIV
90
15V VIN
30V VIN
85
EFFICIENCY (%)
IL_BOOST 2A/DIV
PHASE_BOOST 20V/DIV
80
5V VIN
75
70
65
9V VIN
60
PHASE_BUCK 20V/DIV
6V VIN
55
50
0.0 0.2
0.4 0.6
0.8 1.0 1.2
10ms/DIV
1.4 1.6
1.8 2.0
2.2 2.4
LOAD CURRENT (A)
FIGURE 22. EFFICIENCY, BOOST BUCK, 500kHz, VOUT 12V,
TA = +25°C
FIGURE 21. BOOST BUCK MODE, VO = 9V, IO = 1.8A, BOOST INPUT
DROPS FROM 16V TO 9V DC
180
170
160
150
140
130
120
130
110
120
90
100
80
70
60
50
40
30
20
0
10
-10
-20
-50
-30
110
100
-40
UPPER MOSFET rDS(ON) (mΩ)
190
DIE TEMPERATURE (°C)
FIGURE 23. UPPER MOSFET rDS(ON) (mΩ) OVER-TEMPERATURE
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FN8631.1
March 13, 2015
ISL85403
Functional Description
PFM Mode Operation
Initially the ISL85403 continually monitors the voltage at the EN
pin. When the voltage on the EN pin exceeds its rising ON
threshold, the internal LDO will start-up to build up VCC. After
Power-on Reset (POR) circuits detect that VCC voltage has
exceeded the POR threshold, the soft-start will be initiated.
Soft-start
The soft-start (SS) ramp is built up in the external capacitor on
the SS pin that is charged by an internal 5µA current source.
C SS  F  = 6.5  t SS  S 
(EQ. 1)
The SS ramp starts from 0 to a voltage above 0.8V. Once SS
reaches 0.8V, the bandgap reference takes over and IC gets into
steady state operation. The soft-start time is referring to the
duration for SS pin ramps from 0 to 0.8V while output voltage
ramps up with the same rate from 0 to target regulated voltage.
The required capacitance at SS pin can be calculated from
Equation 1.
The SS plays a vital role in the hiccup mode of operation. The IC
works as cycle-by-cycle peak current limiting at over load
condition. When a harsh condition occurs and the current in the
upper side MOSFET reaches the second overcurrent threshold,
the SS pin is pulled to ground and a dummy soft-start cycle is
initiated. At dummy SS cycle, the current to charge soft-start
capacitor is cut down to 1/5 of its normal value. Thus, a dummy
SS cycle takes 5x of the regular SS cycle. During the dummy SS
period, the control loop is disabled and no PWM output. At the
end of this cycle, it will start the normal SS. The hiccup mode
persists until the second overcurrent threshold is no longer
reached.
The ISL85403 is capable of starting up with prebiased output.
To pull the MODE pin HIGH (>2.5V) or leave the MODE pin floating
will set the IC to have PFM (Pulse Frequency Modulation)
operation in light load. In PFM mode, the switching frequency is
dramatically reduced to minimize the switching loss. The
ISL85403 enters PFM mode when the MOSFET peak current is
lower than the PWM/PFM boundary current threshold. The
default threshold is 700mA when there is no programming
resistor at the MODE pin.
The current threshold for PWM/PFM boundary can be
programmed by choosing the MODE pin resistor value calculated
from Equation 2.
118500
R MODE = --------------------------------------I PFM + 0.2
(EQ. 2)
where IPFM is the desired PWM/PFM boundary current threshold
and RMODE is the programming resistor. The usable resistor
value range to program PFM current threshold is 150kΩ to
200kΩ. RMODE value out of this range is not recommended.
200
190
RMODE (kΩ)
Initialization
180
170
160
150
0.3
0.4
0.5
IPFM (A)
0.6
0.7
FIGURE 24. RMODE vs IPFM
PWM Control
Synchronous and Non-Synchronous Buck
Pulling the MODE pin to GND will set the IC in forced PWM mode.
The ISL85403 employs the peak current mode PWM control for
fast transient response and cycle-by-cycle current limiting. See
“Block Diagram” on page 5.
The ISL85403 supports both Synchronous and non-synchronous
buck operations.
The PWM operation is initialized by the clock from the oscillator.
The upper MOSFET is turned on by the clock at the beginning of a
PWM cycle and the current in the MOSFET starts to ramp up.
When the sum of the current sense signal and the slope
compensation signal reaches the error amplifier output voltage
level, the PWM comparator is triggered to shut down the PWM
logic to turn off the high-side MOSFET. The high-side MOSFET
stays off until the next clock signal comes for next cycle.
The output voltage is sensed by a resistor divider from VOUT to
the FB pin. The difference between the FB voltage and 0.8V
reference is amplified and compensated to generate the error
voltage signal at the COMP pin. Then the COMP pin signal is
compared with the current ramp signal to shut down the PWM.
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14
In synchronous buck configuration, a 5.1k or smaller value
resistor must be added from LGATE to ground to avoid falsely
turn-on of LGATE caused by coupling noise.
For a non-synchronous buck operation when a power diode is
used as the low-side power device, the LGATE driver can be
disabled with LGATE connected to VCC (before IC start-up). For
non-synchronous buck, the phase node will show oscillations
after high-side turns off (as shown in Figure 17 on page 12 - blue
trace). This is normal due to the oscillations among the parasitic
capacitors at phase node and output inductor. A RC snubber
(suggesting 200Ω and 2.2nF as typical) at phase node can
reduce this ringing.
FN8631.1
March 13, 2015
ISL85403
AUXVCC Switchover
Output Voltage
The ISL85403 has an auxiliary LDO integrated as shown in the
“Block Diagram” on page 5. It is used to replace the internal
MAIN LDO function after the IC start-up. “Typical Application
Schematic II - VCC Switchover to VOUT” on page 6 shows its basic
application setup with output voltage connected to AUXVCC. After
IC soft-start is done and the output voltage is built up to steady
state, and once the AUXVCC pin voltage is over the AUX LDO
Switchover Rising Threshold, the MAIN LDO is shut off and the
AUXILIARY LDO is activated to bias VCC. Since the AUXVCC pin
voltage is lower than the input voltage VIN, the internal LDO
dropout voltage and the consequent power loss is reduced. This
feature brings substantial efficiency improvements in light load
range, especially at high input voltage applications.
The output voltage can be programmed down to 0.8V by a
resistor divider from VOUT to FB. For Buck, the maximum
achievable voltage is (VIN*DMAX - VDROP), where VDROP is the
voltage drop in the power path including mainly the MOSFET
rDS(ON) and inductor DCR. The maximum duty cycle DMAX is
decided by (1 - fSW * tMIN(OFF)).
When the voltage at AUXVCC falls below the AUX LDO Switchover
Falling Threshold, the AUXILIARY LDO is shut off and the MAIN LDO
is reactivated to bias VCC. At the OV/UV fault events, the IC also
switches back over from AUXILIARY LDO to MAIN LDO.
The AUXVCC switchover function is offered in buck configuration.
It is not offered in boost configuration when the AUXVCC pin is
used to monitor the boost output voltage for OVP.
Input Voltage
With the part switching, the operating ISL85403 input voltage
must be under 40V. This recommendation allows for short
voltage ringing spikes (within a couple of ns time range) due to
part switching while not exceeding the 44V, as stated in the
Absolute Maximum Ratings.
The lowest IC operating input voltage (VIN pin) depends on VCC
voltage and the Rising and Falling VCC POR Threshold in
Electrical Specifications table on page 8. At IC start-up when VCC
is just over rising POR threshold, there is no switching before the
soft-start starts. Therefore, the IC minimum start-up voltage on
the VIN pin is 3.05V (MAX of Rising VCC POR). When the soft-start
is initiated, the regulator is switching and the dropout voltage
across the internal LDO increases due to driving current. Thus,
the IC VIN pin shutdown voltage is related to driving current and
VCC POR falling threshold. The internal upper side MOSFET has
typical 10nC gate drive. For a typical example of synchronous
buck with 4nC lower MOSFET gate drive and 500kHz switching
frequency, the driving current is 7mA total causing 70mV drop
across internal LDO under 3V VIN. Then the IC shutdown voltage
on the VIN pin is 2.87V (2.8V + 0.07V). In practical design, extra
room should be taken into account with concern to voltage
spikes at VIN.
Output Current
With the high-side MOSFET integrated, the maximum output
current, which the ISL85403 can support is decided by the
package and many operating conditions including input voltage,
output voltage, duty cycle, switching frequency and temperature,
etc. From the thermal perspective, the die temperature shouldn’t
exceed +125°C with the power loss dissipated inside of the IC.
Note that more temperature rise is expected at higher ambient
temperature due to more conduction loss caused by rDS(ON)
increase.
Basically, the die temperature is equal to the sum of ambient
temperature and the temperature rise resulting from the power
dissipated by the IC package with a certain junction to ambient
thermal impedance JA. The power dissipated in the IC is related
to the MOSFET switching loss, conduction loss and the internal
LDO loss. Besides the load, these losses are also related to input
voltage, output voltage, duty cycle, switching frequency and
temperature. With the exposed pad at the bottom, the heat of
the IC mainly goes through the bottom pad and JA is greatly
reduced. The JA is highly related to layout and air flow
conditions. In layout, multiple vias (≥9) are strongly
recommended in the IC bottom pad. The bottom pad with its vias
should be placed in the ground copper plane with an area as
large as possible across multiple layers. The JA can be reduced
further with air flow. Refer to Figures 8 and 9 for the thermal
performance with 100 CFM air flow.
For applications with high output current and bad operating
conditions (compact board size, high ambient temperature, etc.),
synchronous buck is highly recommended since the external
low-side MOSFET generates smaller heat than external low-side
power diode. This helps to reduce PCB temperature rise around
the ISL85403 and less junction temperature rise.
With boost buck configuration, the input voltage range can be
expanded further down to 2.5V or lower depending on the boost
stage voltage drop upon maximum duty cycle. Since the boost
output voltage is connected to the VIN pin as the buck inputs,
after the IC starts up, the IC will keep operating and switching as
long as the boost output voltage can keep the VCC voltage higher
than the falling threshold. Refer to “2-Stage Boost Buck
Converter Operation” on page 16 for more details.
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ISL85403
2-Stage Boost Buck Converter Operation
The “Typical Application Schematic III - Boost Buck Converter” on
page 6, shows the circuits of boost function. Schematic (a) shows
a boost working as a pre-stage to provide input to the following
Buck stage. This is for applications when the input voltage could
drop to a very low voltage in some constants (i.e., in some battery
powered systems), causing the output voltage to drop out of
regulation. The boost converter can be enabled to boost the input
voltage up to keep the output voltage in regulation. When system
input voltage recovers back to normal, the boost stage is
disabled while only the buck stage is switching.
The EXT_BOOST pin is used to set boost mode and monitor the
boost input voltage. At IC start-up before soft-start, the controller
will be latched in boost mode when the voltage is at or above
200mV; it will latch in synchronous buck mode if voltage on this
pin is below 200mV. In boost mode, the low-side driver output
PWM has the same PWM signal with the buck regulator.
In boost mode, the EXT_BOOST pin is used to monitor boost input
voltage to turn on and turn off the boost PWM. The AUXVCC pin is
used to monitor the boost output voltage to turn on and turn off
the boost PWM.
Referring to Figure 25, a resistor divider from boost input voltage
to the EXT_BOOST pin is used to detect the boost input voltage.
When the voltage on EXT_BOOST pin is below 0.8V, the boost
PWM is enabled with a fixed 500µs soft-start and the boost duty
cycle increases linearly from tMIN(ON)*Fs to ~50%. A 3µA sinking
current is enabled at the EXT_BOOST pin for hysteresis purposes.
When the voltage on the EXT_BOOST pin recovers to be above
0.8V, the boost PWM is disabled immediately. Use Equation 3 to
calculate the upper resistor RUP (R1 in Figure 25) for a desired
hysteresis VHYS at boost input voltage.
V HYS
R UP  M  = --------------------3  A 
(EQ. 3)
Use Equation 4 to calculate the lower resistor RLOW (R2 in
Figure 25) according to a desired boost enable threshold.
R UP  0.8
R LOW = --------------------------------------VFTH – 0.8
(EQ. 4)
Where VFTH is the desired falling threshold on boost input
voltage to turn on the boost, 3µA is the hysteresis current and
0.8V is the reference voltage to be compared with.
Note that the boost start-up threshold has to be selected in a way
that the buck is operating working well and kept in close loop
regulation before boost start-up. Otherwise, large inrush current
at boost start-up could occur at boost input due to the buck open
loop saturation. The boost start-up input voltage threshold should
be set high enough to cover the DC voltage drop of boost inductor
and diode, also the buck’s maximum duty cycle and voltage
conduction drop. This ensures buck is not reaching maximum
duty cycle before boost start-up.
Similarly, a resistor divider from the boost output voltage to the
AUXVCC pin is used to detect the boost output voltage. When the
voltage on the AUXVCC pin is below 0.8V, the boost PWM is
enabled with a fixed 500µs soft-start and a 3µA sinking current
is enabled at AUXVCC pin for hysteresis purposes. When the
voltage on the AUXVCC pin recovers to be above 0.8V, the boost
PWM is disabled immediately. Use Equation 3 to calculate the
upper resistor RUP (R3 in Figure 25) according to a desired
hysteresis VHY at boost output voltage. Use Equation 4 to
calculate the lower resistor RLOW (R4 in Figure 25) according to a
desired boost enable threshold at boost output.
Assuming VBAT is the boost input voltage, VOUT_BST is the boost
output voltage and VOUT is the buck output voltage, the steady
state DC transfer function are:
1
V OUTBST = ------------------  V BAT
1–D
(EQ. 5)
D
V OUT = D  V OUTBST = ------------------  V BAT
1–D
(EQ. 6)
BATTERY
VOUT_BST
+
+
R1
EXT_BOOST
0.8V
R2
I_HYS = 3µA
R3
LOGIC
LGATE
AUXVCC
R4
0.8V
PWM
LGATE
DRIVE
I_HYS = 3µA
FIGURE 25. BOOST CONVERTER CONTROL
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FN8631.1
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ISL85403
From Equations 5 and 6, Equation 7 can be derived to estimate
the steady state boost output voltage as function of VBAT and
VOUT:
(EQ. 7)
V OUTBST = V BAT + V OUT
Where VIN is the input voltage, VOUT is the buck boost output
voltage, D is duty cycle.
Equation 10 is another useful equation used to calculate the
inductor DC current as below:
1
IL DC = ------------------  I OUT
1–D
After the IC starts up, the boost buck converters can keep
working when the battery voltage drops extremely low because
the IC’s bias (VCC) LDO is powered by the boost output. For
example, a 3.3V output application battery drops to 2V, and the
VIN pin voltage is powered by the boost output voltage that is
5.2V (Equation 7), meaning that the VIN pin (buck input) still sees
5.2V to keep the IC working.
Where ILDC is the inductor DC current and IOUT is the output DC
current.
Note that in the previously mentioned case, the boost input
current could be high because the input voltage is very low
(VIN*IIN = VOUT*IOUT/Efficiency). If the design is to achieve the
low input operation with full load, the inductor and MOSFET have
to be selected with enough current ratings to handle the high
current appearing at boost input. The boost inductor current are
the same with the boost input current, which can be estimated as
Equation 8, where POUT is the output power, VBAT is the boost input
voltage, and EFF is the estimated efficiency of the whole boost and
buck stages.
Inductor ripple current can be calculated using Equation 11:
(EQ. 8)
Based on the same concerns of boost input current, the start-up
sequence must follow the rule that the IC is enabled after the
boost input voltage rise above a certain level. The shutdown
sequence must follow the rule that the IC is disabled first before
the boost input power source is turned off. At boost mode
applications where there is no external control signal to
enable/disable the IC, an external input UVLO circuit must be
implemented for the start-up and shutdown sequence.
Non-inverting Single inductor Buck Boost
Converter Operation
In “Typical Application Schematic III - Boost Buck Converter” on
page 6, schematic (b) shows non-inverting single inductor buck
boost configuration. The recommended setting is to use resistor
divider 1MΩ and 130kΩ (as shown in TYP Schematic III b)
connecting from VCC to both EXT_BOOST and AUXVCC pins
(EXT_BOOST and AUXVCC pin are directly connected). In this way,
the EXT_BOOST pin voltage is a fixed voltage 0.52V that is higher
than the boost mode detection threshold 0.2V to set IC in boost
mode and lower than the boost switching threshold 800mV to
have boost being constantly switching (during and after
soft-start).
As the same in 2-stage boost buck mode, LGATE is switching ON
with the same phase of upper FETs switching ON, meaning both
upper and lower side FETs are ON and OFF at the same time with
the same duty cycle. When both FETs are ON, input voltage
charges inductor current ramping up for duration of DT; when
both FETs are OFF, inductor current is free wheeling through the 2
power diodes to output and output voltage discharge the inductor
current ramping down for (1-D)T (in CCM mode). The steady state
DC transfer function is:
D
V OUT = ------------------  V IN
1–D
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(EQ. 9)
17
Equation 10 shows the inductor current is charging output only
during (1-D)T, which means inductor current has larger DC
current than output load current. Thus, for this part with high-side
FET integrated, the non-inverting buck boost configuration has
less load current capability compared with buck and 2-stage
boost buck configurations. Its load current capability depends
mainly on the duty cycle and inductor current.
V OUT  1 – D T
IL RIPPLE = ----------------------------------------------------L
(EQ. 11)
The inductor peak current is,
1
IL PEAK = IL DC + ----  IL RIPPLE
2
(EQ. 12)
In power stage DC calculations, use Equation 9 to calculate D,
then use Equation 10 to calculate ILDC. D and ILDC are useful
information to estimate the high-side FET’s power losses and
check if the part can meet the load current requirements.
Oscillator and Synchronization
The oscillator has a default frequency of 500kHz with the FS pin
connected to VCC, or ground, or floating. The frequency can be
programmed to any frequency between 200kHz and 2.2MHz with
a resistor from FS pin to GND.
145000 – 16  f SW  kHz 
R FS  k  = ----------------------------------------------------------------------------------------f SW [kHz]
(EQ. 13)
1200
1000
800
RFS (kΩ)
P OUT
IL IN = ---------------------------------------V BAT  EFF
(EQ. 10)
600
400
200
0
0
500
1000
1500
fSW (kHz)
2000
2500
FIGURE 26. RFS vs FREQUENCY
The SYNC pin is bidirectional and it outputs the IC’s default or
programmed local clock signal when it’s free running. The IC
locks to an external clock injected to the SYNC pin (external clock
frequency recommended to be 10% higher than the free running
frequency). The delay from the rising edge of the external clock
signal to the PHASE rising edge is half of the free running switching
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ISL85403
period pulse 220ns, (0.5tSW+220ns). The maximum external clock
frequency is recommended to be 1.6 of the free running frequency.
When the part enters PFM pulse skipping mode, the
synchronization function is shut off and also no clock signal
output in SYNC pin.
With the SYNC pins simply connected together, multiple
ISL85403s can be synchronized. The slave ICs automatically
have 180° phase shift with respective to the master IC.
for dummy soft-start duration equaling to 5 regular soft-start
periods. After this dummy soft-start cycle, the true soft-start cycle
is attempted again. The IOC2 offers a robust and reliable
protection against the worst case conditions.
The frequency foldback is implemented for the ISL85403. When
overcurrent limiting, the switching frequency is reduced to be
proportional to output voltage in order to keep the inductor
current under limit threshold during overload condition. The low
limit of frequency under frequency foldback operation is 40kHz.
The PGOOD pin is output of an open-drain transistor (refer to
“Block Diagram” on page 5). An external resistor is required to be
pulled up to VCC for proper PGOOD function. At start-up, PGOOD
will be turned HIGH (internal PGOOD open-drain transistor is
turned off) with 128 cycles delay after soft-start is finished
(soft-start ramp reaches 1.02V) and FB voltage is within OV/UV
window (90%REF < FB < 110%REF).
At normal operation, PGOOD will be pulled low with 1 cycle
(minimum) and 6 cycles (maximum) delay if any of the OV
(110%) or UV (90%) comparator is tripped. The PGOOD will be
released HIGH with 128 cycles delay after FB recovers to be
within OV/UV window (90%REF < FB < 110%REF). When EN is
pulled low or VCC is below POR, PGOOD is pulled low with no
delay.
In the case when the PGOOD pin is pulled up by external bias
supply instead of VCC of itself, when the part is disabled, the
internal PGOOD open-drain transistor is off, the external bias
supply can charge PGOOD pin HIGH. This should be known as
false PGOOD reporting. At start-up when VCC rise from 0, PGOOD
will be pulled low when VCC reaches 1V. After EN is pulled low
and VCC is falling, the PGOOD internal open-drain transistor will
open with high impedance when VCC falls below 1V. The time
between EN pulled low and PGOOD OPEN depends on the VCC
falling time to 1V.
Overcurrent Protection
The overcurrent function protects against any overload condition
and output short at worst case, by monitoring the current flowing
through the upper MOSFET.
There are 2 current limiting thresholds. The first one IOC1 is to
limit the high-side MOSFET peak current cycle-by-cycle. The
current limit threshold is set to default at 3.6A with ILIMIT pin
connected to GND or VCC, or left open. The current limit threshold
can also be programmed by a resistor RLIM at ILIMIT pin to
ground. Use Equation 14 to calculate the resistor.
(EQ. 14)
Note that IOC1 is higher with lower RLIM. The usable resistor
value range to program OC1 peak current threshold is 40kΩ
to 330kΩ. RLIM value out of this range is not recommended.
The second current protection threshold IOC2 is 15% higher than
IOC1 mentioned previously. Instantly after the high-side MOSFET
current reaches IOC2, the PWM is shut off after 2-cycle delay and
the IC enters hiccup mode. In hiccup mode, the PWM is disabled
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18
320
300
280
260
240
220
200
180
160
140
120
100
80
60
40
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
IOC1 (A)
FIGURE 27. RLIM vs IOC1
Overvoltage Protection
If the voltage detected on the FB pin is over 110% or 120% of
reference, the high-side and low-side driver shuts down
immediately and stays off until FB voltage drops to 0.8V. When
the FB voltage drops to 0.8V, the drivers are released ON. 110%
OVP is off during soft-start and active after soft-start is done.
120% OVP is active during and after soft-start.
Thermal Protection
The ISL85403 PWM will be disabled if the junction temperature
reaches +160°C. There is +20°C hysteresis for OTP. The part will
restart after the junction temperature drops below +140°C.
Fault Protection
300000
R LIM = -----------------------------------------------------I OC  A  + 0.018
RLIM (kΩ)
PGOOD
Component Selections
The ISL85403 iSim model can be used to simulate for both the
time domain behaviors and small signal loop stability analysis.
Output Capacitors - Buck
An output capacitor is required to filter the inductor current.
Output ripple voltage and transient response are two critical
factors when considering output capacitance choice. The current
mode control loop allows for the usage of low ESR ceramic
capacitors and thus smaller board layout. Electrolytic and
polymer capacitors may also be used.
Additional consideration applies to ceramic capacitors. While
they offer excellent overall performance and reliability, the actual
in-circuit capacitance must be considered. Ceramic capacitors
are rated using large peak-to-peak voltage swings with no DC
bias. In the DC/DC converter application, these conditions do not
reflect reality. As a result, the actual capacitance may be
considerably lower than the advertised value. Consult the
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ISL85403
manufacturers datasheet to determine the actual in-application
capacitance. Most manufacturers publish capacitance vs DC bias
so that this effect can be easily accommodated. The effects of
AC voltage are not frequently published, but an assumption of
~20% further reduction will generally suffice. The result of these
considerations can easily result in an effective capacitance 50%
lower than the rated value. Nonetheless, they are a very good
choice in many applications due to their reliability and extremely
low ESR.
In buck topology, the following equations allow calculation of the
required capacitance to meet a desired ripple voltage level.
Additional capacitance may be used.
For the ceramic capacitors (low ESR):
I
V OUTripple = ------------------------------------8 f SW C OUT
(EQ. 15)
where I is the inductor’s peak to peak ripple current, fSW is the
switching frequency and COUT is the output capacitor.
If using electrolytic capacitors then:
V OUTripple = I*ESR
(EQ. 16)
Regarding transient response needs, a good starting point is to
determine the allowable overshoot in VOUT if the load is suddenly
removed. In this case, energy stored in the inductor will be
transferred to COUT causing its voltage to rise. After calculating
capacitance required for both ripple and transient needs, choose
the larger of the calculated values. The Equation 17 determines
the required output capacitor value in order to achieve a desired
overshoot relative to the regulated voltage.
I OUT 2 * L
C OUT = -------------------------------------------------------------------------------------------V OUT 2 *  V OUTMAX  V OUT  2 – 1 
(EQ. 17)
where VOUTMAX/VOUT is the relative maximum overshoot
allowed during the removal of the load.
Input Capacitors - Buck
Depending on the system input power rail conditions, the
aluminum electrolytic type capacitor is normally needed to
provide the stable input voltage. Thus, restrict the switching
frequency pulse current in a small area over the input traces for
better EMC performance. The input capacitor should be able to
handle the RMS current from the switching power devices.
Ceramic capacitors must be used at VIN pin of the IC and
multiple capacitors including 1µF and 0.1µF are recommended.
Place these capacitors as closely as possible to the IC.
Output Inductor - Buck
The inductor value determines the converter’s ripple current.
Choosing an inductor current requires a somewhat arbitrary
choice of ripple current, I. A reasonable starting point is 30% to
40% of total load current. The inductor value is calculated using
Equation 18:
V IN – V OUT V OUT
L = --------------------------------  ---------------V IN
f SW  I
(EQ. 18)
reduce the converter’s response time to a load transient. The
inductor current rating should be as such that it will not saturate
in overcurrent conditions.
Low-side Power MOSFET
In synchronous buck application, a power N MOSFET is needed
as the synchronous low-side MOSFET and a good one should
have low Qgd, low rDS(ON) and small Rg (Rg_typ < 1.5Ω
recommended). The Vgth_min is recommended to be or higher
than 1.2V. A good example is SQS462EN.
A 5.1k or smaller value resistor has to be added to connect
LGATE to ground to avoid falsely turn-on of LGATE caused by
coupling noise.
Output Voltage Feedback Resistor Divider
The output voltage can be programmed down to 0.8V by a
resistor divider from VOUT to FB according to Equation 19.
R UP 

V OUT = 0.8   1 + -----------------
R

LOW
(EQ. 19)
In an application requiring least input quiescent current, large
resistors should be used for the divider. Generally, a resistor
value of 10k to 300k can be used for the upper resistor.
Boost Inductor (2-Stage Boost Buck)
Besides the need to sustain the current ripple to be within a
certain range (30% to 50%), the boost inductor current at its
soft-start is a more important perspective to be considered in
selection of the boost inductor. Each time the boost starts up,
there is a fixed 500µs soft-start time when the duty cycle
increases linearly from tMIN(ON)*fSW to ~50%. Before and after
boost start-up, the boost output voltage will jump from
VIN_BOOST to voltage (VIN_BOOST + VOUT_BUCK). The design target
in boost soft-start is to ensure the boost input current is
sustained to minimum but capable to charge the boost output
voltage to have a voltage step equaling to VOUT_BUCK. A big
inductor will block the inductor current to increase and not high
enough to be able to charge the output capacitor to the final
steady state value (VIN_BOOST + VOUT_BUCK) within 500µs. A
6.8µH inductor is a good starting point for its selection in design.
The boost inductor current at start-up must be checked by
oscilloscope to ensure it is under an acceptable range. It is
suggested to run the iSim model (use the ISL85403 iSim model
available on the internet) to assist in the proper inductor value.
Boost Output Capacitor (2-Stage Boost Buck)
Based on the same theory in boost start-up previously described
in the boost inductor selection, a large capacitor at boost output
will cause high inrush current at boost PWM start-up. 22µF is a
good choice for applications with a buck output voltage less than
10V. Also some minimum amount of capacitance has to be used
in boost output to keep the system stable. It is suggested to run
the iSim model, which is available on the internet to assist in
designing the proper capacitor value.
Increasing the value of inductance reduces the ripple current and
thus ripple voltage. However, the larger inductance value may
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19
FN8631.1
March 13, 2015
ISL85403
Loop Compensation Design Buck
Power Stage Transfer Functions
Transfer function F1(S) from control to output voltage is:
The ISL85403 uses constant frequency peak current mode
control architecture to achieve fast loop transient response. An
accurate current sensing pilot device in parallel with the upper
MOSFET is used for peak current control signal and overcurrent
protection. The inductor is not considered as a state variable
since its peak current is constant and the system becomes single
order system. It is much easier to design the compensator to
stabilize the loop compared with voltage mode control. Peak
current mode control has inherent input voltage feed-forward
function to achieve good line regulation. Figure 28 shows the
small signal model of a buck regulator.
^
iL
+
^
i in
^
Vin
ILd^
1:D
LP
RLP
RT
C
1
1
Where,  esr = --------------- ,Q p  R o ------o- , o = ------------------Rc Co
LP
LP Co
Transfer function F2(S) from control to inductor current is given
by Equation 24:
S
1 + -----ˆI
V in
z
o
F 2  S  = ---= ------------------------- --------------------------------------R o + R LP 2
dˆ
S
S
------- + --------------- + 1
2  Q
o
p
o
(EQ. 24)
where  z = -------------Ro Co .
Rc
Current loop gain Ti(S) is expressed as Equation 25:
Ro
The voltage loop gain with open current loop is expressed in
Equation 26:
Ti(S)
d^
(S)
Fm
T v  S  = KF m F 1  S A v  S 
-Av(S)
FIGURE 28. SMALL SIGNAL MODEL OF BUCK REGULATOR
The PWM comparator gain Fm for peak current mode control is
given by Equation 20:
(EQ. 20)
Where, Se is the slew rate of the slope compensation and Sn is
given by Equation 21:
V in – V o
S n = R t --------------------LP
Tv  S 
L v  S  = -----------------------1 + Ti  S 
(EQ. 27)
If Ti(S)>>1, then Equation 27 can be simplified as Equation 28:
PWM Comparator Gain Fm
1
dˆ
F m = ----------------- = ------------------------------- S e + S n T s
v̂ comp
(EQ. 26)
The Voltage loop gain with current loop closed is given by
Equation 27:
Tv (S)
He(S)
v^comp
(EQ. 21)
S
1 + -----------R o + R LP
 esr A v  S 
1
L v  S  = ------------------------- ---------------------- ---------------- ,  p  --------------Rt
Ro Co
S He  S 
1 + ------p
(EQ. 28)
Equation 28 shows that the system is a single order system.
Therefore, a simple type II compensator can be easily used to
stabilize the system. A type III compensator is needed to expand
the bandwidth for current mode control in some cases.
R2
C1
R3
C3
where, Rt is the gain of the current amplifier.
Current Sampling Transfer Function He(S)
In current loop, the current signal is sampled every switching
cycle. It has the following transfer function in Equation 22:
2
VO
VCOMP
R1
VREF
RBIAS
(EQ. 22)
S
S
H e  S  = ------- + --------------- + 1
2  Q
n n
n
where, Qn and n are given by
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(EQ. 25)
T i  S  = R t F m F 2  S H e  S 
Co
+
(EQ. 23)
1
Vin d^
+
GAIN (VLOOP (S(fi))
^
vo
S
1 + ----------- esr
v̂ o
- = V in --------------------------------------F 1  S  = ----2
dˆ
S
S
------- + --------------- + 1
2  Q
o
p
o
20
2
Q n = – ---  n = f SW

FIGURE 29. TYPE III COMPENSATOR
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A compensator with 2 zeros and 1 pole is recommended for this
part, as shown in Figure 29. Its transfer function is expressed as
Equation 29:
Example: VIN = 12V, Vo = 5V, Io = 2A, fSW = 500kHz,
Co = 60µF/3mΩ, L = 10µH, Rt = 0.20V/A, fc = 50kHz,
R1 = 105k, RBIAS = 20kΩ.
S
S 
 1 + ------------ 1 + -------------

 cz2
 cz1 
v̂ comp
1
A v  S  = ----------------- = ------------------- --------------------------------------------------------SR 1 C
S 
v̂ O
 1 + --------1

 cp
Select the crossover frequency to be 35kHz. Since the output
capacitors are all ceramic, use Equations 33 and 34 to
derive R3 to be 20k and C3 to be 470pF.
(EQ. 29)
Then use Equations 35 and 36 to calculate C1 to be 180pF
and R2 to be 12.7k. Select 150pF for C1 and 15k for R2.
where,
1
1
1
 cz1 = --------------- ,  cz2 = ----------------------------------  cp = -------------- R 1 + R 3 C 3
R2 C1
R3 C3
There is approximately 30pF parasitic capacitance between
COMP to FB pins that contributes to a high frequency pole.
Any extra external capacitor is not recommended between
COMP and FB.
Compensator design goal:
1
1
- f
Loop bandwidth fc:  --4- to ----10 SW
Figure 30 shows the simulated bode plot of the loop. It is
shown that it has 26kHz loop bandwidth with 70° phase
margin and -28 dB gain margin.
Gain margin: >10dB
Phase margin: 45°
The compensator design procedure is as follows:
1. Position CZ2 and CP to derive R3 and C3.
Put the compensator zero CZ2 at (1 to 3)/(RoCo)
(EQ. 30)
3
 cz2 = --------------Ro Co
Put the compensator pole CP at ESR zero or 0.35 to 0.5
times of switching frequency, whichever is lower. In
all-ceramic-cap design, the ESR zero is normally higher than
half of the switching frequency. R3 and C3 can be derived as
follows:
Note in applications where the PFM mode is desired especially
when type III compensation network is used, the value of the
capacitor between the COMP pin and the FB pin (not the
capacitor in series with the resistor between COMP and FB)
should be minimal to reduce the noise coupling for proper PFM
operation. No external capacitor between COMP and FB is
recommended at PFM applications.
In PFM mode operations, a RC filter from FB to ground (R in
series with C, connecting from FB to ground) may help to reduce
the noise effects injected to FB pin. The recommended values for
the filter is 499Ω to 1k for the R and 470pF for the C.
1
Case A: ESR zero ---------------------- less than (0.35 to 0.5)fSW
2R c C o
R o C o – 3R c C o
C 3 = ---------------------------------------3R 1
(EQ. 31)
3R c R 1
R 3 = -----------------------R o – 3R c
(EQ. 32)
1
Case B: ESR zero ---------------------- larger than (0.35 to 0.5)fSW
2R c C o
0.33R o C o f SW – 0.46
C 3 = -------------------------------------------------------f SW R
(EQ. 33)
R1
R 3 = ----------------------------------------0.73R o C o f s – 1
(EQ. 34)
1
2. Derive R2 and C1.
The loop gain Lv(S) at cross over frequency of fc has unity
gain. Therefore, C1 is determined by Equation 35.
 R 1 + R 3 C 3
C 1 = ---------------------------------2f c R t R 1 C
(EQ. 35)
o
The compensator zero CZ1 can boost the phase margin and
bandwidth. To put CZ1 at 2 times of cross cover frequency
fc is a good start point. It can be adjusted according to
specific design. R1 can be derived from Equation 36.
(EQ. 36)
1
R 2 = -------------------4f c C 1
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FN8631.1
March 13, 2015
ISL85403
Loop Compensation Design for
2-Stage Boost Buck and
Single-stage Buck Boost
For 2-stage boost buck and single-stage non-inverting buck boost
configurations, it’s highly recommended to use the iSim model
(use the ISL85403 iSim model available in internet) to evaluate
the loop bandwidth and phase margin.
80
1. Place the input ceramic capacitors as closely as possible to
the IC VIN pin and power ground connecting to the power
MOSFET or Diode. Keep this loop (input ceramic capacitor, IC
VIN pin and MOSFET/Diode) as tiny as possible to achieve the
least voltage spikes induced by the trace parasitic
inductance.
2. Place the input aluminum capacitors closely as possible to
the IC VIN pin.
3. Keep the phase node copper area small but large enough to
handle the load current.
60
4. Place the output ceramic and aluminum capacitors close to
the power stage components as well.
40
5. Place vias (≥9) in the bottom pad of the IC. The bottom pad
should be placed in ground copper plane with an area as large
as possible in multiple layers to effectively reduce the thermal
impedance.
dB
20
0
6. Place the 4.7µF ceramic decoupling capacitor at the VCC pin
(the closest place to the IC). Put multiple vias (≥3) close to the
ground pad of this capacitor.
-20
-40
-60
100
Layout Suggestions
7. Keep the bootstrap capacitor close to the IC.
1•103
1•104
1•105
1•106
FREQUENCY (Hz)
8. Keep the LGATE drive trace as short as possible and try to
avoid using via in the LGATE drive path to achieve the lowest
impedance.
9. Place the positive voltage sense trace close to the place to be
strictly regulated.
180
160
10. Place all the peripheral control components close to the IC.
140
DEGREE (°)
120
100
80
60
40
20
0
100
FIGURE 31. PCB VIA PATTERN
1•103
1•104
1•105
1•106
FREQUENCY (Hz)
FIGURE 30. SIMULATED LOOP BODE PLOT
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FN8631.1
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ISL85403
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
March 13, 2015
FN8631.1
Changed the max input Voltage (Vin) from 36V to 40V on the following pages:
On page 1: In the description and features sections
On page 4: VIN pin description
On page 7: Recommended operating conditions for VIN
On page 15: Application description for the “Input Voltage” section
On page 1, added “Related Literature” section.
On page 4, added ISL85403EVAL2Z to the Ordering Information table.
Replaced Figures 5 and 6.
Removed Figures 10 and 11 and the references on page 15.
March 12, 2014
FN8631.0
Initial Release
About Intersil
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address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
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FN8631.1
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ISL85403
Package Outline Drawing
L20.4x4C
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/06
4X
4.00
2.0
16X 0.50
A
B
16
6
PIN #1 INDEX AREA
20
6
PIN 1
INDEX AREA
1
4.00
15
2 .70 ± 0 . 15
11
(4X)
5
0.15
6
10
0.10 M C A B
4 20X 0.25 +0.05 / -0.07
20X 0.4 ± 0.10
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0 . 1
C
BASE PLANE
( 3. 8 TYP )
(
SEATING PLANE
0.08 C
2. 70 )
( 20X 0 . 5 )
SIDE VIEW
( 20X 0 . 25 )
C
0 . 2 REF
5
( 20X 0 . 6)
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
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FN8631.1
March 13, 2015
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