DATASHEET

ISL83699
®
Data Sheet
November 5, 2004
Ultra Low ON-Resistance, Low Voltage,
Single Supply, Quad SPDT (Dual DPDT)
Analog Switch
Features
The Intersil ISL83699 device is a low ON-resistance, low
voltage, bidirectional, Quad SPDT (Dual DPDT) analog
switch designed to operate from a single +1.65V to +3.6V
supply. Targeted applications include battery powered
equipment that benefit from low on-resistance (0.26Ω), and
fast switching speeds (tON = 10ns, tOFF = 7ns). The digital
logic input is 1.8V logic-compatible when using a single +3V
supply.
• Drop in Replacement for the STG3699
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This family of parts may be used to
“mux-in” additional functionality while reducing ASIC design
risk. The ISL83699 is offered in small form factor packages,
alleviating board space limitations.
The ISL83699 consists of four SPDT switches. It is configured
as a dual double-pole/double-throw (DPDT) device with two
logic control inputs that control two SPDT switches each. The
configuration can be used as a dual differential 2-to-1
multiplexer/demultiplexer. The ISL83699 is pin compatible
with the STG3699.
TABLE 1. FEATURES AT A GLANCE
FN6094.3
• Pb-Free Available as an Option (RoHS Compliant)
(see Ordering Info)
• ON Resistance (RON)
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.26Ω
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.45Ω
• RON Matching between Channels . . . . . . . . . . . . . . . .0.04Ω
• RON Flatness Across Signal Range . . . . . . . . . . . . . . .0.06Ω
• Single Supply Operation. . . . . . . . . . . . . . . . +1.65V to +3.6V
• Low Power Consumption (PD). . . . . . . . . . . . . . . . . . <0.2µW
• Fast Switching Action
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7ns
• Guaranteed Break-Before-Make
• 1.8V Logic Compatible (+3V supply)
• Available in 16 lead 3x3 QFN and 16 lead TSSOP
• ESD HBM Rating
- COM Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9kV
- All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV
Applications
ISL83699
Number of Switches
4
SW
Quad SPDT (Dual DPDT)
3.0V RON
0.26Ω
3.0V tON/tOFF
10ns/7ns
1.8V RON
0.45Ω
1.8V tON/tOFF
18ns/10ns
Packages
16 Ld 3x3 QFN, 16 Ld TSSOP
• Battery Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL83699
Pinouts
Ordering Information
(Note 1)
ISL83699 (TSSOP)
TOP VIEW
PART NO.
(BRAND)
16 V+
NO1 1
15 NC4
COM1 2
14 COM4
NC1 3
IN1-2 4
13 NO4
NO2 5
12 IN3-4
11 NC3
COM2 6
NC2 7
10 COM3
GND 8
9 NO3
COM1
NO1
V+
NC4
ISL83699 (3x3 QFN)
TOP VIEW
16
15
14
13
IN1-2
2
11
NO4
NO2
3
10
IN3-4
COM2
4
9
NC3
5
6
7
8
COM3
COM4
NO3
12
GND
1
NC2
NC1
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL83699IR
(83699IR)
-40 to 85
16 Ld 3x3 QFN
L16.3x3
ISL83699IR-T
(83699IR)
-40 to 85
16 Ld 3x3 QFN
Tape and Reel
L16.3x3
ISL83699IV
(83699IV)
-40 to 85
16 Ld TSSOP
M16.173
ISL83699IV-T
(83699IV)
-40 to 85
16 Ld TSSOP
Tape and Reel
M16.173
ISL83699IRZ
(83699IR)
(See Note)
-40 to 85
16 Ld 3x3 QFN
(Pb-free)
L16.3x3
ISL83699IRZ-T
(83699IR)
(See Note)
-40 to 85
16 Ld 3x3 QFN
Tape and Reel
(Pb-free)
L16.3x3
ISL83699IVZ
(83699IV)
(See Note)
-40 to 85
16 Ld TSSOP
(Pb-free)
M16.173
ISL83699IVZ-T
(83699IV)
(See Note)
-40 to 85
16 Ld TSSOP
Tape and Reel
(Pb-free)
M16.173
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
NOTE:
1. Switches Shown for Logic “0” Input.
Truth Table
LOGIC
NC SW
NO SW
0
ON
OFF
1
OFF
ON
NOTE:
Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.
Pin Descriptions
PIN
FUNCTION
V+
System Power Supply Input (+1.65V to +3.6V)
GND
Ground Connection
IN
Digital Control Input
COM
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
2
FN6094.3
November 5, 2004
ISL83699
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V
Input Voltages
NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA
ESD Rating:
HBM COMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>9kV
HBM NOX, NCX, INX, V+, GND . . . . . . . . . . . . . . . . . . . . . . .>4kV
MM COMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
MM NOX, NCX, INX, V+, GND . . . . . . . . . . . . . . . . . . . . . . .>300V
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1000V
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
16 Ld 3x3 QFN Package . . . . . . . . . . . . . . . . . . . . .
75
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
150
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(Lead Tips Only)
Operating Conditions
Temperature Range
ISL83699IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 6),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Full
0
-
V+
V
25
-
0.3
0.45
Ω
Full
-
-
0.6
Ω
25
-
0.04
0.08
Ω
Full
-
-
0.09
Ω
25
-
0.06
0.15
Ω
Full
-
-
0.15
Ω
25
-3
-
3
nA
Full
-20
-
20
nA
25
-4
-
4
nA
Full
-45
-
45
nA
25
-
11
17
ns
Full
-
-
20
ns
25
-
8
14
ns
Full
-
-
17
ns
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 5)
RON Matching Between Channels,
∆RON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at
max RON, (Note 9)
RON Flatness, RFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(Note 7)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V,
3V, or Floating
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 1, Note 8)
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 1, Note 8)
Break-Before-Make Time Delay, tD
V+ = 3.3V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 3, Note 8)
Full
2
3
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2)
25
-
-82
-
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 4)
25
-
68
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 6)
25
-
-98
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω
25
-
0.003
-
%
3
FN6094.3
November 5, 2004
ISL83699
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 6),
Unless Otherwise Specified (Continued)
TEMP
(°C)
(NOTE 5)
MIN
TYP
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
106
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
212
-
pF
Full
1.65
3.6
V
25
-
-
50
nA
Full
-
-
750
nA
Input Voltage Low, VINL
Full
-
-
0.5
V
Input Voltage High, VINH
Full
1.4
-
-
V
Full
-0.5
-
0.5
µA
PARAMETER
TEST CONDITIONS
COM ON Capacitance, CCOM(ON)
(NOTE 5)
MAX
UNITS
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = 3.6V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 3.6V, VIN = 0V or V+ (Note 8)
NOTES:
4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
8. Guaranteed but not tested.
9. RON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron
value, between NC1 and NC2, NC3 and NC4 or between NO1 and NO2, NO3 and NO4.
Electrical Specifications - 1.8V Supply
PARAMETER
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Notes 4, 6),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Full
0
-
V+
V
25
-
0.45
0.8
Ω
Full
-
-
0.85
Ω
25
-
18
23
ns
Full
-
-
25
ns
25
-
10
15
ns
Full
-
-
18
ns
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 5)
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.65V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF,
(See Figure 1, Note 8)
Turn-OFF Time, tOFF
V+ = 1.65V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF,
(See Figure 1, Note 8)
Break-Before-Make Time Delay, tD
V+ = 2.0V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF,
(See Figure 3, Note 8)
Full
2
5
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2)
25
-
-44
-
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 4)
25
-
68
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 6)
25
-
-98
-
dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
106
-
pF
COM ON Capacitance, CCOM(ON)
25
-
212
-
pF
4
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
FN6094.3
November 5, 2004
ISL83699
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Notes 4, 6),
Unless Otherwise Specified (Continued)
TEMP
(°C)
(NOTE 5)
MIN
TYP
Input Voltage Low, VINL
Full
-
-
0.4
V
Input Voltage High, VINH
Full
1.0
-
-
V
Full
-0.5
-
0.5
µA
PARAMETER
TEST CONDITIONS
(NOTE 5)
MAX
UNITS
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+ (Note 8)
Test Circuits and Waveforms
V+
V+
LOGIC
INPUT
50%
0V
SWITCH
INPUT
tOFF
VOUT
NO or NC
COM
IN
SWITCH
V
INPUT NO
VOUT
90%
SWITCH
OUTPUT
C
tr < 5ns
tf < 5ns
90%
LOGIC
INPUT
CL
35pF
RL
50Ω
GND
0V
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
-----------------------------V OUT = V
(NO or NC) R + R
L
( ON )
FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
V+
SWITCH
OUTPUT
VOUT
RG
∆VOUT
NO or NC
C
VOUT
COM
V+
LOGIC
INPUT
VG
ON
ON
GND
IN
CL
OFF
0V
LOGIC
INPUT
Q = ∆VOUT x CL
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
5
FN6094.3
November 5, 2004
ISL83699
Test Circuits and Waveforms (Continued)
V+
V+
NO
VNX
LOGIC
INPUT
C
VOUT
COM
NC
0V
90%
SWITCH
OUTPUT
VOUT
CL
35pF
RL
50Ω
IN
GND
LOGIC
INPUT
0V
tD
CL includes fixture and stray capacitance.
FIGURE 3B. TEST CIRCUIT
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE TIME
V+
V+
C
C
RON = V1/1mA
SIGNAL
GENERATOR
NO or NC
NO or NC
VNX
IN
1mA
0V or V+
0V or V+
COM
COM
ANALYZER
IN
V1
GND
GND
RL
FIGURE 5. RON TEST CIRCUIT
FIGURE 4. OFF ISOLATION TEST CIRCUIT
V+
C
V+
C
SIGNAL
GENERATOR
NO or NC
COM
50Ω
NO or NC
IN1
IMPEDANCE
ANALYZER
NC or NO
COM
ANALYZER
0V or V+
IN
0V or V+
GND
COM
N.C.
GND
RL
FIGURE 6. CROSSTALK TEST CIRCUIT
6
FIGURE 7. CAPACITANCE TEST CIRCUIT
FN6094.3
November 5, 2004
ISL83699
Detailed Description
Power-Supply Considerations
The ISL83699 is a bidirectional, dual double-pole/
double-throw (DPDT) analog switch that offers precise
switching capability from a single 1.65V to 3.6V supply with
low on-resistance (0.26Ω) and high speed operation
(tON = 10ns, tOFF = 7ns). The device is especially well suited
for portable battery powered equipment due to its low
operating supply voltage (1.65V), low power consumption
(2.7µW max), low leakage currents (45nA max), and the tiny
QFN and TSSOP packages. The ultra low on-resistance and
Ron flatness provide very low insertion loss and distortion to
applications that require signal reproduction.
The ISL83699 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL83699 4.7V
maximum supply voltage provides plenty of room for the
10% tolerance of 3.6V supplies, as well as room for
overshoot and noise spikes.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (See
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (See Figure 8). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low RON switch, so two small signal
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (See Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch signal range is
reduced and the resistance may increase, especially at low
supply voltages.
OPTIONAL PROTECTION
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
INX
VNO or NC
VCOM
GND
OPTIONAL PROTECTION
DIODE
The minimum recommended supply voltage is 1.65V but the
part will operate with a supply below 1.5V. It is important to
note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
curves for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.0V to 3.6V (See Figure 17). At 3.6V
the VIH level is about 1.27V. This is still below the 1.8V
CMOS guaranteed high output minimum level of 1.4V, but
noise margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 50Ω systems, the signal response is reasonably flat even
past 30MHz with a -3dB bandwidth of 104MHz (See Figure
15). The frequency response is very consistent over a wide
V+ range, and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off Isolation is
the resistance to this feedthrough, while Crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 16 details the high Off Isolation and Crosstalk
rejection provided by this part. At 100kHz, Off Isolation is
about 68dB in 50Ω systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
impedances decrease Off Isolation and Crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.
FIGURE 8. OVERVOLTAGE PROTECTION
7
FN6094.3
November 5, 2004
ISL83699
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
Typical Performance Curves TA = 25°C, Unless Otherwise Specified
0.35
0.45
V+ = 2.7V
ICOM = 100mA
ICOM = 100mA
0.4
0.3
V+ = 1.8V
RON (Ω)
RON (Ω)
85°C
0.35
0.25
25°C
0.3
0.2
V+ = 2.7V
-40°C
0.25
V+ = 3V
V+ = 3.6V
0.15
0.2
0
1
2
3
0
4
0.5
1
1.5
2
2.5
3
VCOM (V)
VCOM (V)
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
50
0.5
V+ = 1.8V
ICOM = 100mA
0.45
85°C
0
V+ = 1.8V
Q (pC)
RON (Ω)
0.4
0.35
0.3
V+ = 3V
-50
25°C
-100
-40°C
0.25
0.2
-150
0
0.5
1
1.5
VCOM (V)
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
8
2
0
0.5
1
1.5
2
2.5
3
VCOM (V)
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
FN6094.3
November 5, 2004
ISL83699
Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued)
20
50
40
15
85°C 25°C
20
5
0
1.5
2
2.5
3
V+ (V)
3.5
4
1
4.5
1.5
2
2.5
3
3.5
4
FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE
10
-10
V+ = 3V
V+ = 3V
0
4.5
V+ (V)
GAIN
PHASE (DEGREES)
0
PHASE
20
40
60
80
RL = 50Ω
VIN = 0.2VP-P to 2VP-P
1
10
100
100
FREQUENCY (MHz)
CROSSTALK (dB)
-20
-20
20
-30
30
-40
40
-50
50
60
-60
ISOLATION
70
-70
80
-80
CROSSTALK
-90
90
100
-100
-110
1K
600
FIGURE 15. FREQUENCY RESPONSE
OFF ISOLATION (dB)
1
25°C
-40°C
FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE
NORMALIZED GAIN (dB)
85°C
10
-40°C
10
0
tOFF (ns)
tON (ns)
30
10K
100K
1M
10M
FREQUENCY (Hz)
110
100M 500M
FIGURE 16. CROSSTALK AND OFF ISOLATION
1.5
1.4
Die Characteristics
1.3
SUBSTRATE POTENTIAL (POWERED UP):
VINH AND VINL (V)
1.2
GND (QFN paddle connection: to ground or float)
1.1
TRANSISTOR COUNT:
VINH
1
228
0.9
0.8
PROCESS:
VINL
Si Gate CMOS
0.7
0.6
0.5
0.4
0.3
1
1.5
2
2.5
3
3.5
4
4.5
V+ (V)
FIGURE 17. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
9
FN6094.3
November 5, 2004
ISL83699
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
E
0.25(0.010) M
2
INCHES
E1
GAUGE
PLANE
-B1
B M
L
0.05(0.002)
-A-
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.043
-
1.10
-
A1
3
A
D
-C-
e
α
c
0.10(0.004)
C A M
0.05
0.15
-
A2
0.033
0.037
0.85
0.95
-
b
0.0075
0.012
0.19
0.30
9
c
0.0035
0.008
0.09
0.20
-
B S
0.002
D
0.193
0.201
4.90
5.10
3
0.169
0.177
4.30
4.50
4
0.026 BSC
E
0.246
L
0.020
N
α
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
0.006
E1
e
A2
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
MILLIMETERS
0.65 BSC
0.256
6.25
0.028
0.50
16
0o
-
0.70
6
16
8o
0o
-
6.50
7
8o
Rev. 1 2/02
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
10
FN6094.3
November 5, 2004
ISL83699
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.3x3
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
2X
MILLIMETERS
0.15 C A
D
A
9
D/2
D1
D1/2
2X
N
6
INDEX
AREA
0.15 C B
1
2
3
E1/2
E
2X
2X
TOP VIEW
0.15 C A
A
0.90
1.00
-
-
-
0.05
-
A2
-
-
1.00
9
A3
0.20 REF
0.18
0
0.08 C
SEATING PLANE
A3
SIDE VIEW
9
5
NX b
4X P
D1
2.75 BSC
9
1.35
1.50
1.65
-
2.75 BSC
1.35
1.50
9
1.65
7, 8, 10
0.50 BSC
-
k
0.20
-
-
-
L
0.30
0.40
0.50
8
N
16
2
Nd
4
3
P
-
-
0.60
NX k
θ
-
-
12
4
3
9
9
Rev. 1 6/04
4X P
NOTES:
1
(DATUM A)
2
3
6
INDEX
AREA
NX L
N e
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
(Ne-1)Xe
REF.
E2
E2/2
2. N is the number of terminals.
7
3. Nd and Ne refer to the number of terminals on each D and E.
8
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
9
CORNER
OPTION 4X
(Nd-1)Xe
REF.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
BOTTOM VIEW
A1
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
NX b
5
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
SECTION "C-C"
C
L
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
C
L
10
7, 8, 10
3.00 BSC
Ne
D2
2 N
5, 8
-
8
7
L1
0.30
3.00 BSC
0.10 M C A B
D2
(DATUM B)
A1
0.23
9
D
e
/ / 0.10 C
C
C C
0.80
E2
A2
NOTES
A
E1
B
MAX
A1
E
0.15 C B
8
NOMINAL
D2
9
4X
MIN
b
E/2
E1
SYMBOL
L
L1
e
10
L
10. Compliant to JEDEC MO-220VEED-2 Issue C, except for the E2
and D2 MAX dimension.
e
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN6094.3
November 5, 2004
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