DATASHEET

ISL84467
®
Data Sheet
July 23, 2008
Ultra Low ON-Resistance, +1.65V to +4.5V,
Single Supply, Quad SPDT (Dual DPDT)
Analog Switch
The Intersil ISL84467 device is a low ON-resistance, low
voltage, bidirectional, Quad SPDT (Dual DPDT) analog
switch designed to operate from a single +1.65V to +4.5V
supply. Targeted applications include battery powered
equipment that benefit from low rON (0.39Ω) and fast
switching speeds (tON = 33ns, tOFF = 16ns). The digital logic
input is 1.8V logic-compatible when using a single +3V supply.
With a supply voltage of 4.2V and logic high voltage of 2.85V
at both logic inputs, the part draws only 12µA max of ICC
current.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL84467 is offered in small form factor package, alleviating
board space limitations.
The ISL84467 consists of four SPDT switches. It is configured
as a dual double-pole/double-throw (DPDT) device with two
logic control inputs that control two SPDT switches each. The
configuration can be used as a dual differential 2-to-1
multiplexer/demultiplexer.
FN6521.1
Features
• ON-Resistance (rON)
- V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.39Ω
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.45Ω
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65Ω
• rON Matching Between Channels . . . . . . . . . . . . . . . . . 0.05Ω
• rON Flatness Across Signal Range . . . . . . . . . . . . . . . 0.05Ω
• Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V
• Low Power Consumption (PD) . . . . . . . . . . . . . . . . <0.68µW
• Fast Switching Action (V+ = +4.3V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ns
• Break-Before-Make
• 1.8V Logic Compatible (+3V supply)
• Low ICC Current when VinH is not at the V+ Rail
• Available in 16 Ld 3x3 TQFN and 16 Ld TSSOP Packages
• ESD HBM Rating
- COM Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9kV
- All Othe r Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV
• Pb-Free (RoHS compliant)
Applications
TABLE 1. FEATURES AT A GLANCE
• Battery-Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
ISL84467
Number of Switches
4
SW
Quad SPDT (Dual DPDT)
4.3V rON
0.39W
4.3V tON/tOFF
33ns/16ns
3.0V rON
0.45W
3.0V tON/tOFF
34ns/18ns
Related Literature
1.8V rON
0.65W
1.8V tON/tOFF
50ns/25ns
Package
16 Ld 3x3 TQFN, 16 Ld TSSOP
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners..
ISL84467
Pinouts
Truth Table
(Note 1)
ISL84467
(16 LD TQFN)
TOP VIEW
COM1
NO1
V+
NC4
16
15
14
13
LOGIC
NC SW
NO SW
0
ON
OFF
1
OFF
ON
NOTE:
Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.
Pin Descriptions
NC1
1
12
COM4
IN1-2
2
11
NO4
NO2
3
10
IN3-4
COM2
4
9
NC3
PIN
6
System Power Supply Input (+1.65V to +4.5V)
GND
Ground Connection
IN
Digital Control Input
COM
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
7
NO3
GND
NC2
8
COM3
5
V+
FUNCTION
Analog Switch Common Pin
ISL84467
(16 LD TSSOP)
TOP VIEW
16 V+
NO1 1
15 NC4
COM1 2
14 COM4
NC1 3
IN1-2 4
13 NO4
NO2 5
12 IN3-4
11 NC3
COM2 6
NC2 7
10 COM3
GND 8
9 NO3
NOTE:
1. Switches Shown for Logic “0” Input.
Ordering Information
PART NUMBER
(Note)
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG. DWG. #
ISL84467IRTZ
67TZ
-40 to +85
16 Ld 3x3 TQFN
L16.3x3A
ISL84467IRTZ-T*
67TZ
-40 to +85
16 Ld 3x3 TQFN Tape and Reel
L16.3x3A
ISL84467IVZ
84467 IVZ
-40 to +85
16 Ld TSSOP
M16.173
ISL84467IVZ-T*
84467 IVZ
-40 to +85
16 Ld TSSOP Tape and Reel
M16.173
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-Free plastic packaged products employ special Pb-Free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-Free soldering operations).
Intersil Pb-Free products are MSL classified at Pb-Free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
2
FN6521.1
July 23, 2008
ISL84467
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
Input Voltages
NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Output Voltages
COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA
ESD Rating:
Human Body Model (COMX) . . . . . . . . . . . . . . . . . . . . . . . . .>9kV
Human Body Model (NOX, NCX, INX, V+, GND) . . . . . . . . . .>6kV
Machine Model (COMX) . . . . . . . . . . . . . . . . . . . . . . . . . . . .>700V
Machine Model (NOX, NCX, INX, V+, GND) . . . . . . . . . . . . .>300V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV
Thermal Resistance (Typical)
θJA (°C/W)
TQFN Package (Note 3) . . . . . . . . . . . . . . . . . . . . .
70
TSSOP Package (Note 4) . . . . . . . . . . . . . . . . . . . .
115
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 4.3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 5),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 6, 9)
Full
0
TYP
MAX
(Notes 6, 9) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+
(See Figure 5, Note 10)
rON Matching Between Channels,
ΔrON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = Voltage at
max rON (Notes 8, 10)
rON Flatness, rFLAT(ON)
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+
(Notes 7, 10)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 4.5V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 4.5V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V,
3V
V+
V
25
0.4
Ω
Full
0.45
Ω
25
0.05
Ω
Full
0.06
Ω
25
0.05
Ω
Full
0.05
Ω
25
-70
70
nA
Full
-165
165
nA
25
-70
70
nA
Full
-165
165
nA
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF
(See Figure 1)
Turn-OFF Time, tOFF
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF
(See Figure 1)
25
33
ns
Full
38
ns
25
16
ns
Full
21
ns
Break-Before-Make Time Delay, tD
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF
(See Figure 3)
Full
3
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (See Figure 2)
25
248
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 4)
25
65
dB
3
FN6521.1
July 23, 2008
ISL84467
Electrical Specifications - 4.3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 5),
Unless Otherwise Specified. (Continued)
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 6, 9)
TYP
MAX
(Notes 6, 9) UNITS
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 6)
25
-85
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω
25
0.008
%
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
38
pF
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
102
pF
COM ON Capacitance, CCOM(ON)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
4.5
V
25
0.15
µA
Full
1.4
µA
25
13
µA
Input Voltage Low, VINL
Full
0.5
V
Input Voltage High, VINH
Full
1.6
Full
-0.5
Positive Supply Current, I+
V+ = +4.5V, VIN = 0V or V+
Positive Supply Current, I+
V+ = +4.2V, VIN = 2.85V
1.65
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 4.5V, VIN = 0V or V+
Electrical Specifications - 3.0V Supply
PARAMETER
V
0.5
µA
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 5),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 6, 9)
Full
0
TYP
MAX
(Notes 6, 9) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+
(See Figure 5, Note 10)
rON Matching Between Channels,
ΔrON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at
max rON (Notes 8, 10)
rON Flatness, rFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+
(Notes 7, 10)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V,
3V, or Floating
25
0.55
Full
25
0.08
Full
25
0.07
Full
V+
V
0.75
Ω
0.85
Ω
0.19
Ω
0.22
Ω
0.15
Ω
0.15
Ω
25
1.1
nA
Full
30
nA
25
1.5
nA
Full
45
nA
25
34
ns
Full
39
ns
25
18
ns
Full
23
ns
Full
3
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1)
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1)
Break-Before-Make Time Delay, tD V+ = 3.3V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 3)
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (See Figure 2)
25
126
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 4)
25
65
dB
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FN6521.1
July 23, 2008
ISL84467
Electrical Specifications - 3.0V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 5),
Unless Otherwise Specified. (Continued)
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 6, 9)
TYP
MAX
(Notes 6, 9) UNITS
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 6)
25
-85
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω
25
0.012
%
NO or NC OFF Capacitance,
COFF
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
38
pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
102
pF
25
0.021
µA
Full
0.72
µA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 3.6V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full
Input Voltage High, VINH
Full
1.4
Full
-0.5
Input Current, IINH, IINL
V+ = 3.6V, VIN = 0V or V+
Electrical Specifications - 1.8V Supply
PARAMETER
0.5
V
V
0.5
µA
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 5),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 6, 9)
Full
0
TYP
MAX
(Notes 6, 9) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+
(See Figure 5, Note 10)
ON-Resistance, rON
25
0.7
Full
V+
V
0.9
Ω
0.95
Ω
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.65V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF
(See Figure 1)
Turn-OFF Time, tOFF
V+ = 1.65V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF
(See Figure 1)
Break-Before-Make Time Delay, tD V+ = 2.0V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF
(See Figure 3)
CL = 1.0nF, VG = 0V, RG = 0Ω (See Figure 2)
Charge Injection, Q
25
50
ns
Full
55
ns
25
25
ns
Full
30
ns
Full
8
ns
25
48
pC
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full
Input Voltage High, VINH
Full
1.0
Full
-0.5
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+
0.4
V
V
0.5
µA
NOTES:
5. VIN = input voltage to perform proper function.
6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
7. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
8. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value, between NC1 and NC2, NC3 and NC4 or between NO1 and NO2, NO3 and NO4.
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. Limits established by characterization and are not production tested.
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FN6521.1
July 23, 2008
ISL84467
Test Circuits and Waveforms
V+
C
V+
LOGIC
INPUT
50%
0V
SWITCH
INPUT
tOFF
COM
IN
SWITCH
V
INPUT NO
VOUT
90%
SWITCH
OUTPUT
VOUT
NO or NC
90%
LOGIC
INPUT
CL
35pF
RL
50Ω
GND
0V
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
----------------------V OUT = V
(NO or NC) R + r
L
ON
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
SWITCH
OUTPUT
VOUT
RG
DVOUT
C
VOUT
COM
NO or NC
V+
ON
ON
LOGIC
INPUT
VG
OFF
GND
IN
CL
0V
LOGIC
INPUT
Q = DVOUT x CL
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
C
V+
LOGIC
INPUT
VNX
0V
NO
VOUT
COM
NC
SWITCH
OUTPUT
VOUT
90%
LOGIC
INPUT
0V
tD
RL
50Ω
IN
CL
35pF
GND
CL includes fixture and stray capacitance.
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
6
FN6521.1
July 23, 2008
ISL84467
Test Circuits and Waveforms (Continued)
V+
V+
C
C
rON = V1/100mA
SIGNAL
GENERATOR
NO or NC
NO or NC
VNX
IN
100mA
0V or V+
IN
V1
COM
ANALYZER
0V or V+
COM
GND
GND
RL
FIGURE 5. rON TEST CIRCUIT
FIGURE 4. OFF ISOLATION TEST CIRCUIT
V+
C
V+
C
SIGNAL
GENERATOR
NO or NC
COM
50Ω
NO or NC
IN1
IN
0V or V+
COM
ANALYZER
0V or V+
IMPEDANCE
ANALYZER
NC or NO
GND
COM
NC
GND
RL
FIGURE 6. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL84467 is a bidirectional, quad single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.65V to 4.5V supply with low
ON-resistance (0.39Ω) and high speed operation (tON = 33ns,
tOFF = 16ns). The device is especially well suited for portable
battery powered equipment due to its low operating supply
voltage (1.65V), low power consumption (6.3µW max), low
leakage currents (165nA max), and the tiny TQFN package.
The ultra low ON-resistance and rON flatness provide very low
insertion loss and distortion to applications that require signal
reproduction.
FIGURE 7. CAPACITANCE TEST CIRCUIT
turn ON, creating a low impedance path from the V+ power
supply to ground. This will result in a significant amount of
current flow in the IC which can potentially create a latch-up
state or permanently damage the IC. The external V+
resistor limits the current during this over-stress situation
and has been found to prevent latch-up or destructive
damage for many overvoltage transient events.
Under normal operation, the sub-microamp IDD current of
the IC produces an insignificant voltage drop across the
100Ω series resistor resulting in no impact to switch
operation or performance.
External V+ Series Resistor
For improved ESD and latch-up immunity, Intersil
recommends adding a 100Ω resistor in series with the V+
power supply pin of the ISL84467 IC (see Figure 8).
During an overvoltage transient event, such as occurs during
system level IEC 61000 ESD testing, substrate currents can be
generated in the IC that can trigger parasitic SCR structures to
7
FN6521.1
July 23, 2008
ISL84467
.
.
V+
OPTIONAL
PROTECTION
RESISTOR
C
OPTIONAL
SCHOTTKY
DIODE
V+
100Ω
OPTIONAL
PROTECTION
RESISTOR
NOx
COMx
NCx
INX
VNX
VCOM
INx
GND
OPTIONAL
SCHOTTKY
DIODE
FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND
LATCH-UP IMMUNITY
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 9). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provide additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can be protected by adding a 1kΩ resistor in series
with the logic input (see Figure 9). The resistor limits the input
current below the threshold that produces permanent damage,
and the sub-microamp input current produces an insignificant
voltage drop during normal operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch. Connecting Schottky
diodes to the signal pins (as shown in Figure 9) will shunt the
fault current to the supply or to ground, thereby protecting
the switch. These Schottky diodes must be sized to handle
the expected fault current.
GND
FIGURE 9. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL84467 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4.7V maximum supply voltage, the ISL84467 5.5V
maximum supply voltage provides plenty of room for the
10% tolerance of 4.3V supplies, as well as room for
overshoot and noise spikes.
The minimum recommended supply voltage is 1.65V. It is
important to note that the input signal range, switching times,
and ON-resistance degrade at lower supply voltages. Refer to
the “Electrical Specifications” tables starting on page 3 and the
“Typical Performance Curves” starting on page 9 for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 3.0V to 4.5V (see Figure 19). At 3.0V
the VIL level is about 0.53V. This is still above the 1.8V
CMOS guaranteed low output maximum level of 0.5V, but
noise margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
The ISL84467 has been designed to minimize the supply
current whenever the digital input voltage is not driven to the
supply rails (0V to V+). For example, driving the device with
2.85V logic (0V to 2.85V) while operating with a 4.2V supply
the device draws only 12µA of current (see Figure 17 for
VIN = 2.85V).
8
FN6521.1
July 23, 2008
ISL84467
High-Frequency Performance
Leakage Considerations
In 50Ω systems, the ISL84467 has a -3dB bandwidth of
104MHz (see Figure 22). The frequency response is very
consistent over a wide V+ range, and for varying analog
signal levels.
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off isolation is
the resistance to this feedthrough, while crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 23 details the high off isolation and crosstalk rejection
provided by this part. At 100kHz, off isolation is about 65dB
in 50Ω systems, decreasing approximately 20dB per decade
as frequency increases. Higher load impedances decrease
off isolation and crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load
impedance.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog signal
path leakage current. All analog leakage current flows between
each pin and one of the supply terminals, not to the other
switch terminal. This is why both sides of a given switch can
show leakage currents of the same or opposite polarity.
There is no connection between the analog signal paths and
V+ or GND.
Typical Performance Curves TA = +25°C, unless otherwise specified.
0.40
0.46
ICOM = 100mA
ICOM = 100mA
0.45
0.39
0.44
0.38
0.43
V+ = 2.7V
0.42
rON (Ω)
rON (Ω)
0.37
0.36
0.35
0.40
V+ = 3V
0.39
V+ = 3.9V
0.34
0.41
0.38
V+ = 3.3V
V+ = 4.3V
0.33
0.37
V+ = 4.5V
0.32
0
1
2
0.36
3
4
5
0
0.5
1.0
1.5
2.0
VCOM (V)
VCOM (V)
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
2.5
3.0
3.5
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.8
0.45
V+ = 4.3V
ICOM = 100mA
ICOM = 100mA
V+ = 1.65V
0.7
0.40
+85°C
rON (Ω)
rON (Ω)
V+ = 1.8V
0.6
V+ = 2V
0.5
0.35
+25°C
0.30
-40°C
0.4
0.25
0
0.5
1.0
1.5
VCOM (V)
FIGURE 12. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
9
2.0
0
1
2
3
4
5
VCOM (V)
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
FN6521.1
July 23, 2008
ISL84467
Typical Performance Curves TA = +25°C, unless otherwise specified. (Continued)
0.50
0.55
V+ = 3.3V
ICOM = 100mA
V+ = 2.7V
ICOM = 100mA
0.50
0.45
+85°C
+85°C
rON (Ω)
rON (Ω)
0.45
0.40
+25°C
+25°C
0.40
-40°C
0.35
0.35
-40°C
0.30
0.30
0
0.5
1.0
1.5
2.0
VCOM (V)
2.5
3.0
3.5
0
V+ = 1.8V
ICOM = 100mA
+85°C
0.65
1.5
VCOM (V)
2.0
2.5
3.0
200
V+ = 4.2V
+25°C
0.60
SWEEPING BOTH LOGIC INPUTS
150
-40°C
0.55
ION (mA)
rON (Ω)
1.0
FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
0.70
0.5
0.50
100
0.45
50
0.40
0.35
0
0.5
1.0
VCOM (V)
1.5
0
2.o
0
FIGURE 16. ON-RESISTANCE vs SWITCH VOLTAGE
1.0
200
0.9
4
5
0.8
VINH AND VINL (V)
150
Q (pC)
2
3
VIN1, VIN 2 (V)
FIGURE 17. SUPPLY CURRENT vs VLOGIC VOLTAGE
250
100
50
V+ = 4.3V
0
VINH
0.7
0.6
VINL
0.5
0.4
V+ = 1.8V
V+ = 3V
-50
-100
1
0.3
0
1
2
3
4
5
VCOM (V)
FIGURE 18. CHARGE INJECTION vs SWITCH VOLTAGE
10
0.2
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
4.5
FIGURE 19. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FN6521.1
July 23, 2008
ISL84467
Typical Performance Curves TA = +25°C, unless otherwise specified. (Continued)
250
40
35
200
30
tOFF (ns)
tON (ns)
150
100
25
+85°C
20
+85°C
50
+25°C
+25°C
-40°C
15
-40°C
0
1.0
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
10
1.0
4.5
FIGURE 20. TURN-ON TIME vs SUPPLY VOLTAGE
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
FIGURE 21. TURN-OFF TIME vs SUPPLY VOLTAGE
-10
10
V+ = 4.3V
0
V+ = 3V
-20
20
GAIN
-30
30
-40
40
0
PHASE
20
60
80
RL = 50Ω
VIN = 0.2VP-P to 2VP-P
1M
100
10M
FREQUENCY (Hz)
100M
600M
FIGURE 22. FREQUENCY RESPONSE
PHASE (°)
40
-50
50
ISOLATION
-60
60
-70
70
-80
80
OFF ISOLATION (dB)
-20
CROSSTALK (dB)
NORMALIZED GAIN (dB)
4.5
CROSSTALK
-90
90
-100
100
-110
1k
10k
100k
1M
10M
110
100M 500M
FREQUENCY (Hz)
FIGURE 23. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND (QFN Paddle Connection: To Ground or Float)
TRANSISTOR COUNT:
228
PROCESS:
Si Gate CMOS
11
FN6521.1
July 23, 2008
ISL84467
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
E
0.25(0.010) M
E1
2
INCHES
GAUGE
PLANE
-B1
B M
0.05(0.002)
-A-
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.043
-
1.10
-
A1
3
L
A
D
-C-
e
α
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
c
0.10(0.004)
C A M
0.05
0.15
-
A2
0.033
0.037
0.85
0.95
-
b
0.0075
0.012
0.19
0.30
9
c
0.0035
0.008
0.09
0.20
-
B S
0.002
D
0.193
0.201
4.90
5.10
3
0.169
0.177
4.30
4.50
4
0.026 BSC
E
0.246
L
0.020
N
α
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
0.006
E1
e
A2
MILLIMETERS
0.65 BSC
0.256
6.25
0.028
0.50
16
0o
-
0.70
6
16
8o
0o
-
6.50
7
8o
Rev. 1 2/02
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
12
FN6521.1
July 23, 2008
ISL84467
Thin Quad Flat No-Lead Plastic Package (TQFN)
Thin Micro Lead Frame Plastic Package (TMLFP)
2X
L16.3x3A
0.15 C A
D
A
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
9
D/2
MILLIMETERS
D1
D1/2
2X
N
6
INDEX
AREA
0.15 C B
1
2
3
E1/2
E/2
MIN
NOMINAL
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
A2
-
-
0.80
9
0.30
5, 8
A3
E1
E
b
9
0.20 REF
0.18
D
2X
B
TOP VIEW
0.15 C A
D2
A2
0
A
/ / 0.10 C
C
A3
SIDE VIEW
9
5
NX b
4X P
E
3.00 BSC
-
2.75 BSC
9
1.35
1.50
1.65
7, 8, 10
0.50 BSC
-
k
0.20
-
-
-
L
0.30
0.40
0.50
8
2
8
Nd
4
3
NX k
Ne
4
3
D2
2 N
1
(DATUM A)
2
3
6
INDEX
AREA
E2/2
N e
9
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
SECTION "C-C"
C
L
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
L
L1
10
L
e
TERMINAL TIP
FOR ODD TERMINAL/SIDE
9
12
3. Nd and Ne refer to the number of terminals on each D and E.
A1
e
0.60
-
2. N is the number of terminals.
NX b
10
-
-
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
8
BOTTOM VIEW
C
L
-
θ
NOTES:
9
CORNER
OPTION 4X
(Nd-1)Xe
REF.
P
Rev. 0 6/04
(Ne-1)Xe
REF.
E2
7
NX L
C C
7, 8, 10
16
7
L1
9
1.65
N
4X P
8
1.50
0.10 M C A B
D2
(DATUM B)
A1
-
2.75 BSC
1.35
e
SEATING PLANE
9
E1
E2
0.08 C
0.23
3.00 BSC
D1
0.15 C B
2X
4X
SYMBOL
FOR EVEN TERMINAL/SIDE
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2
and D2 MAX dimension.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN6521.1
July 23, 2008
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