an1454

ISL9440BEVAL1Z: Triple PWM Step-Down
Synchronous Buck Controller and One LDO
®
Application Note
September 25, 2009
ISL9440BEVAL1Z Evaluation Board
TABLE 1. FEATURES OF ISL944X FAMILY
The ISL9440BEVAL1Z evaluation board features the
ISL9440B. The ISL9440B is quad-output controller that
integrates three PWM synchronous buck controllers and one
low-dropout linear regulator controller. Then ISL9440B offers
programmable soft-start, independent enable functions and
integrates OV/OC/OT protection. The current mode control
architecture and internal compensation network keep
peripheral components to a minimum. The strong gate drivers
of the ISL9440B are capable of driving 20A current for
PWM1 and PWM2 and 15A for PWM3.
Table 1 shows the difference in terms of ISL944xx family
features.
Electrical Specifications
AN1454.0
EARLY
WARNING
SWITCHING
FREQUENCY
(kHz)
SOFT-STARTING
TIME
(ms)
ISL9440
YES
300
1.7
ISL9440A
YES
600
1.7
ISL9441
NO
300
1.7
ISL9440B
YES
300
PROGRAMMABLE
ISL9440C
YES
600
PROGRAMMABLE
PART
NUMBER
The ISL9440BEVAL1Z is easy to set up to evaluate the
performance of the ISL9440B. Please refer to the “Electrical
Specifications” for typical performance summary.
Recommended operation conditions, unless otherwise noted. Refer to schematic and typical performance
curves.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
15
19
23
V
VOUT1
4.85
5.0
5.15
V
VOUT2
3.25
3.32
3.4
V
VOUT3
11.64
12.0
12.36
V
VOUT4
2.47
2.50
2.58
V
15
18
A
15
18
A
12
14
A
1.0
A
VIN
All outputs are in regulation
PWM1 Rated Current
VIN = 19V, TA = +25°C, No forced airflow, All three PWM
outputs are fully loaded
PWM2 Rated Current
PWM3 Rated Current
LDO Rated Current
R7 = 0Ω, R4 is not populated
0.8
VOUT1 Peak-to-Peak Ripple
VIN = 23V, All three PWM outputs are fully loaded,
Oscilloscope is with full bandwidth.
83
mVP-P
61
mVP-P
109
mVP-P
VOUT2 Peak-to-Peak Ripple
VOUT3 Peak-to-Peak Ripple
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1454
What’s Insides
Quick Set-up Guide
The Evaluation Board Kit contains the following materials:
1. Ensure that the circuit is correctly connected to the supply
and electronics loads prior to applying any power. Please
refer to Figure 1 for proper set-up.
• The ISL9440BEVAL1Z
• The ISL9440B, ISL9440C datasheet
2. Connect Jumpers J3, J4 and J5 in the ENx positions.
• This EVAL KIT document
3. Turn on the power supply
Recommended Equipment
4. Adjust input voltage VIN within the specified range and
observe output voltage. The output voltage variation
should be within 3%.
The following materials are recommended to perform
testing:
• 0V to 24V power supply with at least 20A source current
capability
• Three electronics loads capable of sinking current up to 20A
5. Adjust load current within the specified range and
observe output voltage. The output voltage variation
should be within 3%.
6. Use oscilloscope to observe output voltage ripple and
Phase node ringing. For accurate measurement, refer to
Figure 2 for proper test set-up.
• Digital multimeters (DMMs)
• 100MHz quad-trace Oscilloscope
• Signal generator (for load transient tests)
VOUT1
+
IOUT1
-
+
-
V
A
+
LOAD
IIN
A
+
+
A
VOUT2
_
_
V
V
_
VV
_
LOAD
LOAD
+
VIN
+
+
+
A
V
V
+ -
+
IOUT3
VOUT3
FIGURE 1. PROPER TEST SET-UP
2
AN1454.0
September 25, 2009
Application Note 1454
5. Apply pulse square waveform to the ISTEP_CLK1,
ISTEP_CLK2 and ISTEP_CLK3. The duty cycle of the
pulse waveform should be small (<5%) to limit thermal
stress on current sensing resistor and the MOSFETs (Q8,
Q9 and Q10
6. The amplitude of the clock sets the current step
amplitude. Adjust the clock amplitude and slew rate to set
the current step and slew rate.
OUTPUT
CAP
OUTPUT
OUTPUT
CAP
CAP
OR
ORMOSFET
MOSFET
7. Monitor overshoot and undershoot at corresponding
output.
FIGURE 2. PROPER PROBE SET-UP TO MEASURE OUTPUT
RIPPLE AND PHASE NODE RINGING.
OPT, SUD50N03-16P
Q10
3. R12, R14, R16 are 10kΩ resistors for discharging the
MOSFET gates.
4. R13, R15 and R17 are current sensing resistors to
monitor the load step. For accurate measurement, please
use 5% tolerance sensing resistor or better. To alleviate
thermal stress, use 0.1Ω or smaller resistance. The
resistance of the sensing resistors sets the current scale
on the oscilloscope.
Typical Evaluation Board Performance Curves
95
95
VIN = 16VDC
80
75
65
2
4
6
8
10
12
14
LOAD CURRENT (A)
FIGURE 4. PWM1 EFFICIENCY vs LOAD (VO = 5.0V)
3
16
VIN = 16VDC
75
65
60
VIN = 23VDC
VIN = 19VDC
80
70
0
2
85
70
60
OPT, 10k
90
VIN = 23VDC
EFFICIENCY (%)
EFFICIENCY (%)
85
J18
ISTEP1
R15
OPT, 0.01
VIN = 9V, unless otherwise specified.
100
VIN = 19VDC
R14
J17
FIGURE 3. LOAD TRANSIENT CIRCUIT FOR PWM1
100
90
1
IST EP_ CLK1
2. Install the load transient circuit as indicated on the
schematic. Refer to Figure 3 for details.
2
1. Select a DPAK N channel MOSFET with VDSS
breakdown > 20V.
1
Load Transient Circuit Set-up
0
2
4
6
8
10
12
14
16
LOAD CURRENT (A)
FIGURE 5. PWM2 EFFICIENCY vs LOAD (VO = 3.3V)
AN1454.0
September 25, 2009
Application Note 1454
Typical Evaluation Board Performance Curves
VIN = 9V, unless otherwise specified. (Continued)
100
95
EFFICIENCY (%)
90
VIN = 19VDC
VOUT1(AC), 50mV/DIV
85
VIN = 16VDC
80
75
VIN = 23VDC
70
65
60
0
2
4
6
8
10
LOAD CURRENT (A)
12
FIGURE 6. PWM3 EFFICIENCY vs LOAD (VO = 12V)
14
2.0µs/DIV
FIGURE 7. PWM1 OUTPUT RIPPLE UNDER MAX LOAD
(VIN = 23V, IO1 = IO2 = 15A, IO3 = 12A, FULL
BANDWIDTH
VOUT3(AC), 50mV/DIV
VOUT2(AC), 50mV/DIV
2.0µs/DI
2.0µs/DI
FIGURE 8. PWM2 OUTPUT RIPPLE UNDER MAX LOAD
(VIN = 23V, IO1 = IO2 = 15A, IO3 = 12A, FULL
BANDWIDTH
FIGURE 9. PWM3 OUTPUT RIPPLE UNDER MAX LOAD
(VIN = 23V, IO1 = IO2 = 15A, IO3 = 12A, FULL
BANDWIDTH
VOUT1(AC), 100mV/DIV
VOUT2(AC), 100mV/DIV
ISTEP, 5.0A/DIV
ISTEP, 5.0A/DIV
50µs/DIV
FIGURE 10. PWM1 LOAD TRANSIENT RESPONSE
(LOAD STEP FROM 3.75A TO 11.25A
4
50µs/DIV
FIGURE 11. PWM2 LOAD TRANSIENT RESPONSE
(LOAD STEP FROM 3.75A TO 11.25A
AN1454.0
September 25, 2009
Application Note 1454
Typical Evaluation Board Performance Curves
VIN = 9V, unless otherwise specified. (Continued)
VOUT3(AC), 200mV/DIV
ISTEP, 5.0A/DIV
50µs/DI
FIGURE 12. PWM3 LOAD TRANSIENT RESPONSE (LOAD STEP FROM 3A TO 9A)
5
AN1454.0
September 25, 2009
Schematic
Load Transient Circuit 2
1
O PT, SU D50 N03- 16 P
VI N
100 u
35V
10 0u
35 V
1 00u
3 5V
CI N3
10 u
35 V
1 0u
3 5V
QU1
R JK030 5DPB
TP2 1
Q5
OPT
CI N5
CI N7
OPT
3 5V
10 u
35 V
Q6
OPT
QU2
RJK03 05DPB
CIN 8
C IN6
10u
35V
1 0u
3 5V
GND
U G1
1
CO1 3
CO1 2
CO 15
CO11
10u
10V
10 u
10 V
OPT
33 0u
6. 3V
330 u
6.3 V
CB1 0 .22 u
CL1
82 0p
10 u
10 V
J9 V 02-
X5R
1 TP8
GND
1 TP19
GND
Cp1
OPT
25
PH ASE2
27
28
29
30
26
BOOT2
UGATE2
LGATE2
LGATE1
UGATE1
32
31
BO OT3
FB1
PHASE3
ISEN3
EN/ SS3
24
23
CIN4
C IN1 1
10u
35V
1 0u
3 5V
QU 3
RJ K0 332 DPB
UG3
22
1
21
IH LP505 0FDER3R 3M0 1
PH3
CB3 0 .2 2u 16 V
20
VO 3
L3
TP9
VO3
J 10 V03 +
1
3.3 u
LG3
19
Q3
OPT
Rse n3 1. 69 K
18
17
RL3
1.6
Q L3
R JK033 0DPB
FB3
EN/SS2
RST_ N
OC SET3
OCSET1
Q7
OPT
CO3 5
CO 32
CO 31
CO3 3
CO 34
150 u
16V
15 0u
16 V
OPT
10 u
16 V
10 u
16 V
12V @ 12A
J11 V03 1
CL3
820 p
1 TP1 0
G ND
16
R OC1
1 69K
220p
EN/SS1
15
Cf f 1
UGATE3
ISL9440B
14
2 2n
1
VIN
FB2
CSS1
ISEN2
PGND
13
R1 10 5K 1%
VIN
LGATE3
O CSET2
8
VO1
3
6
7
23 EN 1
TP18
GN D
CO 24
10 u
10 V
1
2.0 K
VCC_ 5V
SGND
VFB1
1
GN D
CO2 3
O PT
Rsen 2
PGOO D
12
0 .47 u
3 5V
D isabl ed
TP17
CFIN1
3
1
2
4
Int. V CC
J3
EN1
3
5
23
2
13
SVIN
VIN RFI N1
Ext. V CC 1
1
1
C O21
330 u
6.3 V
Sany o, 16 SVP15 0MX
R2
20 K
VO3
1%
C f f3
1
2
ROC3
169 K
C p3
R6
10K
1%
CSS3
O PT
22n
J5
EN2
4
TP15
VO 4
Q4
VO2
R9 21. 5K1 %
1
1 0u
TP16
GND
1
Cf f 2 2 20p
CO 42
2. 5V @ 1A
1 50u
6. 3V
Sany o, 6TPE1 50MAZB
EN 2
1%
2
1
TP14
EN2
R 16
R1 7
R18
O PT, 10KOPT, 0 .1 OPT, 0. 1
J 16
I STEP3
Enabl
ed
3
2
Di sable d
FB2
C2 O PT
C O41
R8 3 4K
L DOFB
1
J1 5
3
8
7
6
5
D4
D3
D2
D1
G
Q9
O PT, SUD 50N 03- 16P
1
S3
S2
S1
Visha y , P C han nel MOSFET, Si4 423 DY
Load Transient Circuit 3
3
Enabl ed
D isabl ed
1
RO C2
16 9K
EN3
2
C1 0. 22u
R7 0
2
FB3
R5 4 7
3
2
1
VO2
R4 O PT
1 TP1 3EN 3
J4
EN3
1
VO1
3 30p
2
1
ISTEP_ CLK3
RST
1
140 K
1%
3
R3
TP4
R 10
1 0K
1%
R11
10. 7K
1%
C p2
O PT
CSS2
En gine er: Ma njing Xie
Title
I SL 944 0B HI GH CUR RENT TRI PPLE VO UT EV BO AR D
22 n
Size
Do cumen t Numbe r
Re v
2
Cu st om REV 0. 0
Dat e:
Mon day , Ja nua ry 26 , 200 9
Sh eet
1
of
1
Application Note 1454
TP12
VCC 5V
J1 2
1 EXTVCC
ISEN1
11
2
BOOT1
1
LDOFB
C VC C1 4 .7u
PHASE1
Rs en1 U1
2K
RPG1
10 0K
G4
J 18
I STEP1
2
TP11
1
PGOOD
Enabled
CO2 2
33 0u
6. 3V
CL2
82 0p
16V
10
R15
OPT, 0. 01
O PT, 10K
PGND (PAD)
R 14
Ext. VCC
EN1
CO 25
3. 3V @ 14A+1A
QL2
RJK0 330 DPB
Sany o, 6TPF3 30M9L
TP3
1
LG2
LG2
CB2 0 .22 u
16V
10V
PGOOD
Q2
OPT
1
1
J17
2
ISTEP_C LK1
Q10
RL2
1.6
LG 1
Q1
OPT
Q L1
RJK03 30D PB
O PT, SU D50 N03- 16 P
TP7
VO 2
J8 V02 +
1
L 2 1 .5u
RL1
1.6
6
1
G ND
VO 2
2 .2u
1
TP6
1
PH2
9
J
7
V 01-
CO14
J1 3
ISTEP2
IH LP505 0FDER1R 5M0 1
PH1
L1
5V @ 15A
R12
OPT, 10 K R13
OPT, 0. 01
J1 4
UG 2
IHL P5 050 FD ER2R2 M01
Sany o, 6TPF3 30M9L
VO1
33
TP5
J 6 VO1
V 01+
1
1
VI N1
CI N9
2
J2
Q8
C IN1 0
1
CI N2
ISTEP_ CLK2
CIN 1
16V to 23V
2
TP1
J1 VIN
VI N+
1
AN1454.0
September 25, 2009
Application Note 1454
TABLE 2. BILL OF MATERIALS
ITEM QTY
PART REFERENCE
VALUE
DESCRIPTION
PART NUMBER
MANUFACTURER
1
1
C1
0.22µF
2
3
CB1, CB2, CB3
3
1
CFIN1
0.47µF
CERAMIC CAPS, X5R, 35V
AVX, TDK, Murata
4
3
CIN1, CIN2, CIN11
150µF
ALUM. ELEC. CAPS, 35V
Panasonic
5
6
CIN3, CIN4, CIN6, CIN7, CIN8, CIN9
10µF
CERAMIC CAPS, X5R, 35V
AVX, TDK, Murata
6
2
CO11, CO12, CO21, CO22
330µF
POSCAP, 6.3V, ESR 9m
7
5
CO13, CO14, CO23, CO24, CO41
10µF
CERAMIC CAPS, 0805, X5R, 6.3V
AVX, TDK, Murata
8
2
CO31, CO32
150µF
SANYO, OSCON, 16V
Sanyo
9
2
CO33, CO34
10µF
CERAMIC CAPS, X5R, 25V
AVX, TDK, Murata
10
1
CO42
150µF
POSCAP, 6.3V
11
1
CVCC1
4.7µF
CERAMIC CAPS, X5R, 16V
AVX, TDK, Murata
12
2
CFF1, CFF2
220pF
CERAMIC CAPS, NP0, 50V
Generic
13
1
CFF3
330pF
CERAMIC CAPS, NP0, 50V
Generic
14
3
CSS1, CSS2, CSS3
22nF
CERAMIC CAPS, NP0, 50V
Generic
15
1
L1
2.2µH
POWER INDUCTOR
IHLP5050FDER2R2M01 Vishay
16
1
L2
1.5µH
POWER INDUCTOR
IHLP5050FDER1R5M01 Vishay
17
1
L3
3.3µH
POWER INDUCTOR
IHLP5050FDER3R3M01 Vishay
18
3
QL1, QL2, QL3
N MOSFET, 30V
RJK0330DPB
Renesas
19
2
QU1, QU2
N MOSFET, 30V
RJK0305DPB
Renesas
20
1
QU3
N MOSFET, 30V
RJK0332DPB
Renesas
21
1
Q4
P MOSFET, 20V
Si4423DY
Vishay
22
1
R1
105kΩ
RESISTOR, 0603, 1/16W
Generic
23
1
R2
20kΩ
RESISTOR, 0603, 1/16W
Generic
24
2
R6, R10
10kΩ
RESISTOR, 0603, 1/16W
Generic
25
1
R3
140kΩ
RESISTOR, 0603, 1/16W
Generic
26
1
R5
47Ω
RESISTOR, 0603, 1/16W
Generic
27
1
R8
34kΩ
RESISTOR, 0603, 1/16W
Generic
28
1
R9
21.5kΩ
RESISTOR, 0603, 1/16W
Generic
29
1
R11
10.7kΩ
RESISTOR, 0603, 1/16W
Generic
30
1
RFIN1
4.7Ω
RESISTOR, 0603, 1/16W
Generic
31
3
ROC1, ROC2, ROC3
169kΩ
RESISTOR, 0603, 1/16W
Generic
32
1
RPG1
100kΩ
RESISTOR, 0603, 1/16W
Generic
33
2
RSEN1, RSEN2
2.0kΩ
RESISTOR, 0603, 1/16W
Generic
34
1
RSEN3
1.69kΩ
RESISTOR, 0603, 1/16W
Generic
35
1
U1
0.22µFF CERAMIC CAPS, X5R, 16V
QUAD OUTPUT CONTROLLER
AVX, TDK, Murata
6TPF330M9L
4TPE100MZB
ISL9440B
Sanyo
Sanyo
Intersil
OPTIONAL COMPONENTS OR RESISTOR JUMPERS
1
1
C2
OPT
2
3
CL1, CL2, CL3
3
0
CIN11,CIN5
OPT
Generic
4
0
CO15, CO25, CO35
OPT
Generic
820pF
7
Generic
CERAMIC CAPS, 0805
Generic
AN1454.0
September 25, 2009
Application Note 1454
TABLE 2. BILL OF MATERIALS (Continued)
ITEM QTY
PART REFERENCE
VALUE
DESCRIPTION
5
0
CP1, CP2, CP3
OPT
6
0
Q1, Q2, Q3, Q5, Q6, Q7
OPT
N MOSFET, 30V
7
3
RL1, RL2, RL3
1.6Ω
RESISTOR, 0805, 1/8W
8
0
R4
OPT
9
1
R7
0
PART NUMBER
MANUFACTURER
Generic
Generic
Generic
Resistor jumper
Generic
EVALUATION BOARD HARDWARE
1
8
J1, J2, J6, J7, J8, J9, J10, J11
Big Lug
2
1
J3, J4,J5, J12
3 HEAD JUMPER
3
15
TP1 ~ TP15
TEST POINT
4
4
STAND OFF
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
AN1454.0
September 25, 2009
ISL9440BEVAL1Z PCB Layout
9
Application Note 1454
FIGURE 13. TOP COMPONENTS
AN1454.0
September 25, 2009
ISL9440BEVAL1Z PCB Layout
(Continued)
10
Application Note 1454
FIGURE 14. TOP LAYER ETCH
AN1454.0
September 25, 2009
ISL9440BEVAL1Z PCB Layout
(Continued)
11
Application Note 1454
FIGURE 15. SECOND LAYER ETCH
AN1454.0
September 25, 2009
ISL9440BEVAL1Z PCB Layout
(Continued)
12
Application Note 1454
FIGURE 16. THIRD LAYER ETCH
AN1454.0
September 25, 2009
ISL9440BEVAL1Z PCB Layout
(Continued)
13
Application Note 1454
FIGURE 17. BOTTOM LAYER ETCH (MIRRORED)
AN1454.0
September 25, 2009
ISL9440BEVAL1Z PCB Layout
(Continued)
14
Application Note 1454
FIGURE 18. BOTTOM COMPONENTS (MIRRORED)
AN1454.0
September 25, 2009
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