UCC1913 UCC2913 UCC3913 Negative Voltage Hot Swap Power Manager FEATURES DESCRIPTION • Precision Fault Threshold The UCC1913 family of negative voltage circuit breakers provides complete power management, hot swap, and fault handling capability. The IC is referenced to the negative input voltage and is driven through an external resistor connected to ground, which is essentially a current drive as opposed to the traditional voltage drive. The on-board 10V shunt regulator protects the IC from excess voltage and serves as a reference for programming the maximum allowable output sourcing current during a fault. All control and housekeeping functions are integrated, and externally programmable. These include the fault current level, maximum output sourcing current, maximum fault time, soft start time, and average power limiting. In the event of a constant fault, the internal timer will limit the on-time from less than 0.1% to a maximum of 3%. The duty cycle modulates depending on the current into the PL pin, which is a function of the voltage across the FET, and will limit average power dissipation in the FET. The fault level is fixed at 50mV across the current sense amplifier to minimize total dropout. The fault current level is set with an external current sense resistor. The maximum allowable sourcing current is programmed with a voltage divider from VDD to generate a fixed voltage on the IMAX pin. The current level, when the output appears as a current source, is equal to VIMAX/RSENSE. If desired, a controlled current startup can be programmed with a capacitor on the IMAX pin. • Programmable Average Power Limiting • Programmable Linear Current Control • Programmable • Overcurrent Limit • Programmable Fault Time • Fault Output Indication • Shutdown Control • Undervoltage Lockout • 8-Pin SOIC When the output current is below the fault level, the output device is switched on. When the output current exceeds the fault level, but is less than the maximum sourcing level programmed by the IMAX pin, the output remains switched on, and the fault timer starts charging CT. Once CT charges to 2.5V, the output device is turned off and performs a retry some time later. When the output current reaches the maximum sourcing current level, the output appears as a current source, limiting the output current to the set value defined by IMAX. Other features of the UCC1913 family include undervoltage lockout, and 8-pin small outline (SOIC) and Dual-In-Line (DIL) packages. BLOCK DIAGRAM VDD IMAX 3 2 UVLO LOGIC SUPPLY 5.0V REF 1= UNDERVOLTAGE 0.2V 7 OUT 6 SENSE 5 VSS 4 CT 5.0V VDD LINEAR CURRENT AMPLIFIER OVERLOAD COMPARATOR SD/FLT PL VDD VDD + 9.5V SHUNT REGULATOR 8 50Ω DISABLE 1 + 20µA SOURCE ONLY ON-TIME CONTROL 50mV OVERCURRENT COMPARATOR SLUS274 - JANUARY 1999 UDG-99001 UCC1913 UCC2913 UCC3913 CONNECTION DIAGRAMS ABSOLUTE MAXIMUM RATINGS IVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA SHUTDOWN Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA PL Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA IMAX Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C DIL-8, SOIC-8 (Top View) N or J, D Package SD/FLT 1 8 PL IMAX 2 7 OUT VDD 3 6 SENSE CT 4 5 VSS All voltages are with respect to VSS (The most negative voltage). All currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications apply for TA = –55°C to +125°C for UCC1913; –40°C to +85°C for UCC2913; 0°C to +70°C for UCC3913; IVDD = 2mA, CT = 4.7pF, TA = TJ PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VDD Section IDD Regulator Voltage ISOURCE = 2mA to 10mA UVLO Off Voltage 1.0 2.0 mA 8.5 9.5 10.5 V 6 7 8 V 47.5 50 53 mV 50 53.5 mV 50 500 nA Fault Timing Section Overcurrent Threshold TJ = 25°C Over Operating Temperature 46 Overcurrent Input Bias CT Charge Current CT Discharge Current VCT = 1.0V, IPL = 0 –50 –36 –22 µA Overload Condition, VSENSE – VIMAX = 300mV –1.7 –1.2 –0.7 mA VCT = 1.0V, IPL = 0 CT Fault Threshold CT Reset Threshold Output Duty Cycle 0.6 1 1.5 µA 2.2 2.4 2.6 V 0.32 0.5 0.62 V Fault Condition, IPL = 0 1.7 2.7 3.7 % IOUT = 0A 8.5 10 Output Section Output High Voltage IOUT = –1mA Outut Low Voltage 6 IOUT = 0A; VSENSE – VIMAX = 100mV IOUT = 2mA; VSENSE – VIMAX = 100mV V 8 V 0 0.01 V 0.2 0.6 V Linear Amplifier Section Sense Control Voltage IMAX = 100mV 85 100 115 mV IMAX = 400mV 370 400 430 mV 50 500 nA 1.4 1.7 2.0 V 15 25 45 µA 6 7.5 9 V 0 0.01 V 150 300 ns Input Bias Shutdown/Fault Section Shutdown Threshold Input Current Shutdown = 5V Fault Output High Fault Output Low Delay to Output (Note 1) 2 UCC1913 UCC2913 UCC3913 ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications apply for TA = –55°C to +125°C for UCC1913; –40°C to +85°C for UCC2913; 0°C to +70°C for UCC3913; IVDD = 2mA, CT = 4.7pF, TA = TJ PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 4.35 4.85 5.35 Power Limiting Section VSENSE Regulator Voltage IPL = 64 A V Duty Cycle Control IPL = 64µA 0.6 1.2 1.7 % IPL = 1mA 0.045 0.1 0.17 % 300 500 ns Overload Section Delay to Output (Note 1) Output Sink Current VSENSE = VIMAX = 300mV 40 100 Threshold Relative to IMAX 140 200 mA 260 mV Note 1: Guaranteed by design. Not 100% tested in production. PIN DESCRIPTIONS CT: A capacitor is connected to this pin in order to set the maximum fault time. The maximum fault time must be more than the time to charge external load capacitance. The maximum fault time is defined as: TFAULT = from this pin to the drain of the NMOS pass element. When the voltage across the NMOS exceeds 5V, current will flow into the PL pin which adds to the fault timer charge current, reducing the duty cycle from the 3% level. When IPL>>36µA then the average MOSFET power dissipation is given by: ( 2 • CT ) ICH PFET ( avg ) = IMAX • 1 • 10 −6 • RPL where ICH = 36µA + IPL , SENSE: Input voltage from the current sense resistor. When there is greater than 50mV across this pin with respect to VSS, then a fault is sensed, and CT starts to charge. and IPL is the current into the power limit pin. Once the fault time is reached the output will shutdown for a time given by: SD/FLT: This pin provides fault output indication and shutdown control. Interface into and out of this pin is usually performed through level shift transistors. When 20µA is sourced into this pin, shutdown drives high causing the output to disable the NMOS pass device. When opened, and under a non-fault condition, the SD/FLT pin will pull to a low state. When a fault is detected by the fault timer, or undervoltage lockout, this pin will drive to a high state, indicating the output FET is off. TSD = 2 • 106 • CT IMAX: This pin programs the maximum allowable sourcing current. Since VDD is a regulated voltage, a voltage divider can be derived from VDD to generate the program level for the IMAX pin. The current level at which the output appears as a current source is equal to the voltage on the IMAX pin over the current sense resistor. If desired, a controlled current startup can be programmed with a capacitor on the imax pin, and a programmed start delay can be achieved by driving the shutdown with an open collector/drain device into an RC network. VDD: Current driven with a resistor to a voltage at least 10V more positive than VSS. Typically a resistor is connected to ground. The 10V shunt regulator clamps VDD at 10V above the VSS pin, and is also used as an output reference to program the maximum allowable sourcing current. OUT: Output drive to the MOSFET pass element. PL: This feature ensures that the average MOSFET power dissipation is controlled. A resistor is connected VSS: Ground reference for the IC and the most negative voltage available. 3 UCC1913 UCC2913 UCC3913 APPLICATION INFORMATION LOAD PL RPL + 0.2V OVERLOAD COMPARATOR VDD SENSE IMAX 8 I1 36µA 5.0V OUTPUT 6 RS + SENSE I3 1mA OVERCURRENT COMPARATOR 2.5V 50mV H=CLOSE VSS H=CLOSE I2 1µA 5 S Q R Q TO OUTPUT DRIVE H=OFF 0.5V VSS INPUT VOLTAGE CT FAULT TIMING CIRCUITRY 4 CT UDG-99004 VSS Figure 1. Fault timing circuitry for the UCC1913, including power limit overload. During a fault, CT will charge at a rate determined by the internal charging current and the external timing capacitor. Once CT charges to 2.5V, the fault comparator switches and sets the fault latch. Setting of the fault latch causes both the output to switch off and the charging switch to open. CT must now discharge with the 1µA current source, I2, until 0.5V is reached. Once the voltage at CT reaches 0.5V, the fault latch resets, which re-enables the output and allows the fault circuitry to regain control of the charging switch. If a fault is still present, the fault comparator will close the charging switch causing the cycle to begin. Under a constant fault, the duty cycle is given by: Figure 1 shows the detailed circuitry for the fault timing function of the UCC1913. For the time being, we will discuss a typical fault mode, therefore, the overload comparator, and current source I3 does not work into the operation. Once the voltage across the current sense resistor, RS, exceeds 50mV, a fault has occurred. This causes the timing capacitor to charge with a combination of 36µA plus the current from the power limiting amplifier. The PL amplifier is designed to only source current into the CT pin and to begin sourcing current once the voltage across the output FET exceeds 5V. The current IPL is related to the voltage across the FET with the following expression: IPL = VFET − 5V RPL DutyCycle = 1 µA IPL + 36 µA Average power dissipation in the pass element is given by: Where VFET is the voltage across the NMOS pass device. Later it will be shown how this feature will limit average power dissipation in the pass device. Note that under a condition where the output current is more than the fault level, but less than the max level, VOUT ~ VSS (input voltage), IPL = 0, the CT charging current is 36µA. PFET ( avg ) = VFET • IMAX • 1 µA IPL + 36 µA where VFET >> 5V IPL can be approximated as : VFET RPL and where IPL>>36µA, the duty cycle can be approximated as : 4 UCC1913 UCC2913 UCC3913 APPLICATION INFORMATION (cont.) IOUT Output Current IMAX IFAULT Io(nom) t 0A VCT 2.5V CT Voltage (w/respect to VSS) 0.5V t 0V VOUT 0V Output Voltage (w/respect to GND) VSS t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t t0: safe condition – output current is nominal, output voltage is at the negative rail, VSS. t5: t5 = t3: illustrates 3%duty cycle. t1: fault control reached – output current rises above the programmed fault value, CT begins to charge at ≅ 36µA. t7: output short circuit - if VOUT is short circuited to ground, CT charges at a higher rate depending upon the values for VSS and RPL. t2: max current reached – output current reaches the programmed maximum level and becomes a constant current with value IMAX. t8: fault occurs – output is still short circuited, but the occurrence of a fault turns the FET off so no current is conducted. t3: fault occurs – CT has charged to 2.5V, fault output goes high, the FET turns off allowing no output current to flow, VOUT floats up to ground. t9: t9 = t4; output short circuit released, still in fault mode. t6: t6 = t4 t10: t10 = t0; fault released, safe condition – return to normal operaton of the circuit breaker. t4: retry – CT has discharged to 0.5V, but fault current is still exceeded, CT begins charging again, FET is on, VOUT pulled down to VSS. Figure 2. Typical timing diagram. 5 UCC1913 UCC2913 UCC3913 APPLICATION INFORMATION (cont.) 1µA • RPL VFET Therefore, the maximum average power dissipation in the MOSFET can be approximated by: PFET ( avg ) = VFET • IMAX • 1 µA • RPL = IMAX • 1µA • R PL VFET Notice that in the approximation, VFET cancels. therefore, average power dissipation is limited in the NMOS pass element. Overload Comparator Figure 3. The linear amplifier in the UCC1913 ensures that the output NMOS does not pass more than IMAX (which is VIMAX/RS). In the event the output current exceeds the programmed IMAX by 0.2V/RS, which can only occur if the output FET is not responding to a command from the IC, the CT pin will begin charging with I3, 1mA, and continue to charge to approximately 8V. This allows a constant fault to show up on the SD/FLT pin, and also since the voltage on CT will only charge past 2.5V in an overload fault mode, it can be used for detection of output FET failure or to build in redundancy in the system. ∞ Determining External Component Values Referring now to Figure 3. To set RVDD the following must be achieved: VIN (min ) RVDD 10 V (R1 + R 2) + 2 mA In order to estimate the minimum timing capacitor, CT, several things must be taken into account. For example, given the schematic below as a possible (and at this point, a standard) application, certain external component values must be known in order to estimate CT(min). Figure 4. Plot average power vs. FET voltage for increasing values of RPL. Now, given the values of COUT, Load, RSENSE, VSS, and the resistors determining the voltage on the IMAX pin, the user can calculate the approximate startup time of the node VOUT. This startup time must be faster than the time it takes for CT to charge to 2.5V (relative to VSS), and is the basis for estimating the minimum value of CT. In order to determine the value of the sense resistor, RSENSE, assuming the user has determined the fault current, RSENSE can be calculated by: LOCAL VDD R3 SHUTDOWN FAULT OUT R4 LOCAL GND LEVEL SHIFT > 7 R SENSE = SD/FLT VSS Figure 5. Possible level shift circuitry to interface to the UCC1913. 6 50mV IFAULT UCC1913 UCC2913 UCC3913 APPLICATION INFORMATION (cont.) Next, the variable IMAX must be calculated. IMAX is the maximum current that the UCC1913 will allow through the transistor, M1, and it can be shown that during startup with an output capacitor the power MOSFET, M1, can be modeled as a constant current source of value IMAX where: IMAX = TSTART = COUT • VSS IMAX − ILOAD Resistive Load: IMAX • ROUT TSTART = COUT • ROUT • n IMAX • ROUT − VSS VIMAX R SENSE Once TSTART is calculated, the power limit feature of the UCC1913 must be addressed and component values derived. Assuming the user chooses to limit the maximum allowable average power that will be associated with the circuit breaker, the power limiting resistor, RPL, can be easily determined by the following: where VIMAX = voltage on pin IMAX. Given this information, calculation of the startup time is now possible via the following: Current Source Load: CVDD R1 R2 VSS RVDD CSS VDD IMAX 3 OUTPUT 2 PL R T UVLO LOGIC SUPPLY 5.0V REF 8 1= UNDERVOLTAGE VDD VDD 9.5V SHUNT REGULATOR + OUT VDD SD/FLT LINEAR CURRENT AMPLIFIER 7 50Ω DISABLE 1 SENSE + 20µA SOURCE ONLY ON-TIME CONTROL 6 FAULT= 50mV RS VSS 5 CT CT 4 VSS UDG-99002 Figure 6. Typical application diagram. 7 UCC1913 UCC2913 UCC3913 APPLICATION INFORMATION (cont.) RPL = PFET (avg ) Resistive Load: CT (min ) = 1µA • IMAX where a minimum RPL exists defined by RPL (min ) = 3 • TSTART (31 µA • RPL + VSS − 5V − IMAX • ROUT 5 • RPL VSS 5mA ) + 3 • ROUT • VSS • COUT 5 • RPL Finally, after computing the aforementioned variables, the minimum timing capacitor can be derived as such: Current Source Load: CT (min ) = (3 • TSTART • 62µA • RPL + VSS − 10V ) 10 • RPL SAFETY RECOMENDATION Although the UCC3913 is designed to provide system protection for all fault conditions, all integrated circuits can ultimately fail short. For this reason, if the UCC3913 is intended for use in safety critical applications where UL or some other safety rating is required, a redundant safety device such as a fuse should be placed in series with the device. The UCC3913 will prevent the fuse from blowing for virtually all fault conditions, increasing system reliability and reducing maintenance cost, in addition to providing the hot swap benefits of the device. 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