DATASHEET

DATASHEET
Laser Diode Driver with Serial Control and Write
Current DAC
ISL58781
Features
The ISL58781 is a highly integrated laser diode driver
designed to support multi-standard writable optical
drives in CD, DVD, and Blu-Ray at various speeds. It is a
‘hybrid’ part having an interface compatible with a
conventional LDD, but an internal architecture similar to
a write strategy LDD. This combination adds versatility to
the conventional interface.
• Compatible with all Conventional Controllers Having
a Serial Port, with Some Programming
The rise and fall times and overshoot of the blue output
are adjustable to compensate for high and low resistance
lasers.
There are two banks of write currents with a bank select
line, BSEL. This eliminates the need to synchronize the
serial port to the media.
• Programmable Snubber on all Outputs
• Compatible with Future Controllers Having Gray
Coded WEN Lines for Glitchless High-Speed
Operation
• WEN Line Skew Detection
• 1000mA Maximum Total Output
• 10-bit x 10-bit Multiplying DAC Output Provides
10-bit Full Scale Adjustment and 10-bit Resolution at
any Full Scale Output
• Three Laser Outputs Allow Read/Write DVD, CD, and
Blue Combinations
The oscillator can be controlled by external LVDS lines, or
internally activated through program assignment to any
WEN state.
• Analog Inputs Supports Read APC
The WEN lines have internal 100Ω terminators. There is a
skew detector on the WEN receiver outputs.
• Programmable HFM On, Off and Cooling Levels
The ISL58781 requires a single 5V supply.
• Built-in ADC to Sample Laser Voltage Allows Power
Reduction by Optimizing Headroom
• HFM Oscillator Programmable to 100mAP-P and
Range from 100MHz to >1GHz
• Programmable Spread Spectrum for Low EMI
• Built-in Thermal Sensor Aids in Thermal Design
• Serial Input Works up to 50MHz
• Pb-Free (RoHS Compliant)
Applications
• Combination DVD, CD, and Blue Writable Drives
• BD Camcorders
• BD Video Recorders
December 3, 2015
FN6909.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2009, 2011, 2013, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL58781
Application Block Diagram
0.1µ
2.2µ
2.2µ
BEAD
0.1µ
5V TO 9V
4.7µ
0.1µ
WEB
SCLK
SDIO
GND
SEN
IBLUE
BEAD
5V
4.7µ
MAIN BOARD CONTROLLER
SERIAL
INTERFACE
TR TF OVERSHOOT
ADJUST
WEN0
WEN0B
WDAC2
AMPLITUDE
REGISTERS
(8EA)
WEN1
WEN1B
WEN2
VSO
WRITE
REGISTER
SELECTOR
WDAC1
IOUT1
BLUE
WDAC
SKEW
DETECT
GND
SCALE
DAC
WEN2B
VSO
AMPLITUDE
OSCEN
OSCENB
LVDS
OSC
AND
BUFFER
SS
BSEL
FREQ
X
0.1µ
IOUT2
GAIN
CONTROL
RFREQ
READ
DAC
+
READ
MAIN BOARD
AFE
+
VSO
IAPC
REFERENCE
BIAS AND
POWER
GND
VSL
ENA
0.1µ
RSET
1µF
ENA
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FN6909.3
December 3, 2015
ISL58781
Pin Configuration
23 IBLUE
24 GND
22 VSO
WEN0B 2
21 IOUT1
WEN1 3
20 GND
WEN1B 4
19 VSO
THERMAL
PAD
WEN2 5
18 IOUT2
WEN2B 6
17 IOUT2
16 VSO
OSCENB 8
15 ENA
RSET 14
OSCEN 7
BSEL 9
3. For Moisture Sensitivity Level (MSL), please see device
information page for ISL58781. For more information on
MSL please see techbrief TB363.
WEN0 1
GND 13
2. These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die
attach materials, and 100% matte tin plate plus anneal (e3
termination finish, which is RoHS compliant and compatible
with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements
of IPC/JEDEC J STD-020.
VSL 12
1. Please refer to TB347 for details on reel specifications.
25 SEN
58781 CRZ -10 to +85 28 Ld QFN L28.4x5A
26 SDIO
ISL58781
(28 LD QFN)
TOP VIEW
PACKAGE
PKG.
(Pb-free) DWG.#
IAPC 11
ISL58781CRZ-T13
(Notes 1, 2, 3)
TEMP
RANGE
(°C)
27 SCLK
PART
MARKING
28 WEB
PART
NUMBER
RFREQ 10
Ordering Information
Pin Descriptions
PIN
NAME
PIN
NUMBER I/O
PIN
TYPE
PIN DESCRIPTION
WEN0,
WEN0B
1, 2
I
LVDS
Write Enable 0. When WEN0 > WEN0B, the result is a logic 1 in the write current selection.
Otherwise it is logic 0.
WEN1,
WEN1B
3, 4
I
LVDS
Write Enable 1. When WEN1 > WEN1B, the result is a logic 1 in the write current selection.
Otherwise it is logic 0.
WEN2,
WEN2B
5, 6
I
LVDS
Write Enable 2. When WEN2 > WEN2B, the result is a logic 1 in the write current selection.
Otherwise it is logic 0.
OSCEN,
OSCENB
7, 8
I
LVDS
Oscillator Enable. When OSCEN > OSCENB, the result is a logic 1, which may be used to
turn on the oscillator. When 0, the oscillator will output a DC current that is programmable.
BSEL
9
I
Digital
Bank Select input selects the write current register banks.
RFREQ
10
I/O
Analog
A resistor from RFREQ to GND sets the range of the HFM frequency.
IAPC
11
I
Analog
A 1k impedance current input; 100*IAPC flow to the output. This controls the read
current, which may also include a current from an internal DAC.
VSL
12
O
Power
The internal 2.5V regulator needs a 1µF capacitor from VSL to GND. Do not use VSL for
other loads.
GND
13, 20
RSET
14
I/O
Analog
I
Digital
Chip enable input (H = enable, L = disable)
Power
Supply voltage for the output drivers only (connect all pins)
Ground Ground
A resistor from RSET to analog ground calibrates the DAC full-scales
ENA
15
VSO
16, 19, 22
IOUT2
17, 18
O
Analog
Laser diode output #2
IOUT1
21
O
Analog
Laser diode output #1
IBLUE
23
O
Analog
Blue laser diode output
SEN
25
I
Digital
Serial control enable (H = enable, L = disable)
SDIO
26
I/O
Digital
Serial data for parameters and control; in/out
SCLK
27
I
Digital
Serial control clock
WEB
28
I
Digital
Write enable Bar. When low, write current is enabled.
PD
Thermal The Thermal pad should be grounded and connected to a heat sink.
NOTE: Pins with the same name are internally connected together; however, LDD pins must not be used for connecting together
external components or features.
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FN6909.3
December 3, 2015
ISL58781
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VSO, Supply Voltages . . . . . . . . . .
IBLUE, Voltage at IBLUE . . . . . . . .
IOUT1,2, Output Current . . . . . . . .
IBLUE, Output Current. . . . . . . . . .
VIN, Logic Input Voltages . . . . . . .
IIN, Current into RSET, RFREQ, IAPC .
ESD Rating
Human Body Model . . . . . . . . . .
Thermal Resistance (Typical)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . . . . . . . 6V
. . . . . . . . . . . . 7V
. . . . . . 1000mApk
. . . . . . . 600mApk
-0.5V to VSO +0.5V
. . . . . . . . . . . 5mA
. . . . . . . . . . . . . 2500V
JA (°C/W) JC (°C/W)
28 Lead QFN (Notes 4, 5) . . . . . . .
37
2.9
PD, Maximum Power Dissipation . . . . . see curves on page 12
TS, Storage Temperature Range . . . . . . . . -60°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
TA, Ambient Temperature Range . . . . . . . . . -10°C to +85°C
TJ, Junction Temperature Range . . . . . . . . -10°C to +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless
otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications Unless otherwise indicated, all of the following tables are: VSO = VHI = 5V, RSET = 620,
RFREQ = 4.7k, RLOAD-IOUT1/2 = 8 to GND, RLOAD-BLUE = 10 to VHI, PMAX = 0x3FF,
Reg 1 21 = 88h, Reg x-00 bit6 = 0b, TA = +25°C.
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
5.7
V
7.0
V
DC ELECTRICAL SPECIFICATIONS
VSO
(Notes 6, 7)
VIBLUE
IBLUE pin; RLOAD = 10
IVSO
Supply Current (No Current Output)
25
35
mA
IS, dis(nom)
Supply Current, Disable Mode
3.5
6
mA
IS, dis(high)
Supply Current; VSO = 5.5V, Disable Mode
3.9
7
mA
VSO, good
VSO Voltage above which STATUS: VDDOK = 1
3.5
V
IBLUE-LEAK(SEL)
VIBLUE = 7.0V; IBLUE is selected
150
400
µA
IBLUE-LEAK(DE-SEL)
VIBLUE = 7.0V; IBLUE is not selected
1.1
1.6
mA
VIH
Input Logic High Level
VIL
Input Logic Low Level
VOH
SDIO High Level, IL = -5mA
VOL
SDIO Low Level, IL = 5mA
IINH
Logic Input Current High Level
IINL
Logic Input Current Low Level
4.5
2.9
2.0
V
0.8
2.4
V
V
0.4
V
-15
+10
µA
-15
+10
µA
NOTES:
6. Required voltage at the device pins. Allowance must be made for any voltage drop between the power supply and the device.
7. Required voltage also depends on laser diode manufacturer and pickup optical efficiency. Also, see ROUT spec of WDAC.
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FN6909.3
December 3, 2015
ISL58781
PMAX DAC (10-bit) DC Specifications Standard conditions unless otherwise noted.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
DNL-PMAX
Differential Non-Linearity
(Note 8)
INL-PMAX
Integral Non-Linearity
At 200h Resistive Load ~0V to ~3V
ZS-PMAX
Zero-Scale Error
(Note 9)
VRSET
RSET Pin Voltage
TYP
-3.5
MAX
UNIT
+3.5
LSB
+40
LSB
-2
0
+2
LSB
1.03
1.06
1.11
V
NOTES:
8. Differential non-linearity (DNL) is the differential between the measured and ideal 1 LSB change of any two adjacent codes.
9. Zero-scale error (ZS) is the deviation from zero current output when the digital input code is zero.
IOUT1/2 Write Power DAC (10-bit) DC Specifications
PARAMETER
DESCRIPTION
Standard conditions unless otherwise noted.
CONDITIONS
MIN
MAX
(Note 14) TYP (Note 14)
-1.7
+1.0
UNIT
DNL-W
Differential Non-Linearity
LSB
INL-W
Integral Non-Linearity
At 200h Resistive Load
~0V to ~3V
FSOUT-W620
Write DAC Full-Scale Output
Current RSET = 620
WriteDAC = 0x3FF. Headroom
depends on IOUT.
Reg 1-21 = 8F
FSOUT-H1.1
Write DAC Full-Scale Output
Current
WriteDAC = 0x3FF, Reg 1-21 = 8F
Fixed Headroom = 1.1V
PSRR-FS
Power Supply Rejection -Full-Scale
Current
vs VSO (Note 10)
-30
dB
TC-FS-IOUT
Temperature Coefficient -Full-Scale
Current
(Note 11) 0°C to +85°C
-32
ppm/C
ZS-W
Zero-scale error
(Note 12)
ROUT-WDAC
Write DAC Output Series Resistance WriteDAC = PMAX = 0x3FF
PMAX bias overdriven (Note 13)
+21
LSB
475
500
mA
700
773
-2
875
mA
0
+2
LSB
1.1
1.4

NOTES:
10. Full scale output current power supply sensitivity (SFS) is measured by varying the VSO from 4.5V to 5.5V DC and measuring
the effect of this signal on the full-scale output current.
11. Full scale output current temperature coefficient (TFS) is given by delta (full scale output current)/(T).
12. Zero-scale error (ZS) is the deviation from zero current output when the digital input code is zero.
13. PMAX bias overdriven via RSET.
14. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
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FN6909.3
December 3, 2015
ISL58781
IBLUE Write Power DAC (10-bit) DC Specifications Standard conditions unless otherwise noted.
PARAMETER
DESCRIPTION
CONDITIONS
MIN TYP MAX
DNL-W
Differential Non-Linearity
-4.9
INL-W
Integral Non-Linearity
At fixed 2.5V headroom
FSOUT-H2.0
Write DAC Full-Scale Output Current
RSET = 620
WriteDAC = 0x3FF;
Fixed Headroom = 2.0V; Reg 1-21 = 8F
TRRANGE
Tr Tf adjustment Range
Reg 1-0A from X0h to X7h
PSRR-FS
Power Supply Rejection -Full -Scale
Current
TCFS-IBLUE
+2.0
+60
380
UNIT
LSB
LSB
445
575
mA
1
ns
vs VSO (Note 15)
-40
dB
Temperature Coefficient -Full-Scale
Current
(Note 16)
600
ppm/C
ZS-W
Zero-Scale Error
VIOUT = 2V (Note 17)
ROUT-WDAC
Write DAC Output Series Resistance
WriteDAC = PMAX = 0x3FF
PMAX bias overdriven (Note 18)
-8
0
+8
LSB
2.9
4.5

NOTES:
15. Full scale output current power supply sensitivity (SFS) is measured by varying the VSO from 4.5V to 5.5V DC and measuring
the effect of this signal on the full-scale output current.
16. Full scale output current temperature coefficient (TFS) is given by delta (full scale output current)/(T).
17. Zero-scale error (ZS) is the deviation from zero current output when the digital input code is zero.
18. PMAX bias overdriven via RSET.
IBLUE Read APC Amplifier DC Specifications
PARAMETER
Standard conditions unless otherwise noted.
DESCRIPTION
CONDITIONS
MIN TYP MAX
UNIT
IAPCMIN-GAIN
Current Gain @Min Gain
Reg1-21h = 1X, IAPC = 0µA, 500µA
8
12
22
mA/mA
IAPCMAX-GAIN
Current Gain @ Max Gain
Reg1-21h = FX, IAPC = 0µA, 500µA
180
220
280
mA/mA
IAPCGAIN
Current Gain
IAPC = 0µA, 500µA
80
101
150
mA/mA
IAPCOS
Current Offset
IAPC = 0µA
-2
1
3
mA
LINAPC
Output Current Linearity
IAPC = 0µA, 500µA, 1.0mA
0
6
%
IOUT-R-APC
Blue Read Output Current, Using IAPC Input IAPC = 1.5mA
150
RIN
IAPC Input Impedance to GND
800
PSRRAPC
IAPC Current Power Supply Rejection
IOUT-average = 100mA, varying VSO
OUT1/2 Read APC Amplifier DC Specifications
PARAMETER
1300
-46

dB
Standard condition unless otherwise noted.
CONDITIONS
MIN
TYP
MAX
UNIT
Reg1-21h = 1X, IAPC = 0µA, 500µA
10.5
14
17.5
mA/mA
IAPCMAX-GAIN Current Gain @ Max Gain
Reg1-21h = FX, IAPC = 0µA, 500µA
145
163
185
mA/mA
IAPCGAIN
Current Gain
IAPC = 0µA, 500µA
82
92
108
mA/mA
IAPCOS
Current Offset
IAPC = 0µA
-2
1
3
mA
LINAPC
Output Current Linearity
IAPC = 0µA, 500µA, 1.0mA
0
6
%
IOUT-R-APC
Read Output Current, Using IAPC
Input
IAPC = 1.5mA
RIN
IAPC Input Impedance to GND
PSRRAPC
IAPC Current Power Supply Rejection IAPC-IN = 0.45mA, varying VSO
IAPCMIN-GAIN
DESCRIPTION
mA
Current Gain @ Min Gain
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6
120
mA
800
1300
-48

dB
FN6909.3
December 3, 2015
ISL58781
Read DAC (12-bit) DC Specifications
PARAMETER
Standard conditions unless otherwise noted.
DESCRIPTION
CONDITIONS
DNL-R
Read DAC Differential Non-Linearity PREAD: Reg 0-19 + Reg 1-09
INL-R
Read DAC Integral Non-Linearity
@ 900h on Resistive Load.
0V to ~3V
IOUT-R-DAC-RED
Read Output Current, Read DAC at
Full-Scale, IOUT1 or IOUT2
PREAD = 0xFFF, IAPC = 0,
Reg 1-21 = 8F
PSRR-FS
Power Supply Rejection - Ful-Scale
Current
varying the VSO (Note 14)
TC-FS-IOUT
Temperature Coefficient - Full-Scale Not including the RSET
Current
tempco
(Note 20) 0°C to +85°C
ZS-R
Zero-Scale Error
MIN
MAX
(Note 22) TYP (Note 22)
VIOUT = 2V (Note 16)
-2
+2
LSB
+90
110
UNIT
LSB
130
170
mA
-42
dB
-48
ppm/C
-80
0
80
LSB
NOTES:
19. Full scale output current power supply sensitivity (SFS) is measured by varying the VSO from 4.5V to 5.5V DC and measuring
the effect of this signal on the full-scale output current.
20. Full scale output current temperature coefficient (TFS) is given by delta (full scale output current)/(T).
21. Zero-scale error (ZS) is the deviation from zero current output when the digital input code is zero.
22. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
HFM (High Frequency Modulator)
PARAMETER
IMAX-RED-OFF-LINK
Standard conditions unless otherwise noted.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
Max HFM Off DC Output, IOUT1 or
IOUT2 in Link Mode
HFMOFF = 0xFFF
90
120
160
mA
IMAX-RED-OFF-UNLINK Max HFM Off DC Output, IOUT1 or
IOUT2 in Unlink mode
HFMOFF = 0xFFF
80
115
150
mA
IMAX-BLUE-OFF
Max HFM Off DC Output, IBLUE
HFMOFF = 0xFFF
50
62
80
mA
IMIN-RED-OFF
Min HFM Off DC Output, IOUT1 or
IOUT2
HFMOFF = 0x000
-3
0
3
mA
IMIN-BLUE-OFF
Min HFM Off DC Output, IBLUE
HFMOFF = 0x000
-3
0
3
mA
IMAX-RED-ON-LINK
Max HFM Oscillator Output, IOUT1 or
IOUT2 in Link Mode
HFMON = Reg 0-17h = 0xFF
118
mAP-P
IMAX-RED-ON-UNLINK
Max HFM Oscillator Output, IOUT1 or
IOUT2 in Unlink Mode
HFMON = Reg 0-17h = 0xFF
114
mAP-P
IMAX-BLUE-ON
Max HFM Oscillator Output, IBLUE
HFMON = 0xFF
60
mAP-P
FOSC-HI-MAX
Max HFM Frequency, High Range
Reg 0-16 = FFh, Reg X-00 bit 6 = 0 900
1020
1250
MHz
FOSC-HI-MIN
Min HFM Frequency, High Range
Reg 0-16 = 01h, Reg X-00 bit 6 = 0 120
175
240
MHz
FOSC-LO-MAX
Max HFM Frequency, Low Range
Reg 0-16 = FFh, Reg X-00 bit 6 =1
425
525
625
MHz
FOSC-LO-MIN
Min HFM Frequency, Low Range
Reg 0-16 = 01h, Reg X-00 bit 6 = 1
55
78
105
MHz
PSRROSC-FREQ
PSRR -HFM Frequency
VSO from 4.5V to 5.0V
PSRROSC-AMP-IOUT
PSRR - HFM Amplitude
PSRROSC-AMP-IBLUE
0.5
%/V
350MHz; HFMON = FFh; Link
3
%/V
PSRR - HFM Amplitude
700MHz; HFMON = FFh; Link
1.2
%/V
TFOSC400MAX
HFM Frequency Temperature
Coefficient
Range from 200MHz to 400MHz
0 - 900
ppm/C
TFOSC900MAX
HFM Frequency Temperature
Coefficient
Range from 400MHz to 900MHz
±250
ppm/C
VRFREQ
RFREQ Pin Voltage
RFREQ = 4.7k
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0.9
1.11
1.2
V
FN6909.3
December 3, 2015
ISL58781
HFM (High Frequency Modulator)
PARAMETER
Standard conditions unless otherwise noted. (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
0.1
0.525
1.1
%
SS-WIDTH-RANGE
Spread Spectrum Spreading Width
Adjustment Range
RFREQ = 4.7kReg 1-18 = 10h,
Reg 0-16 = 26h; Reg X-00 bit 6 = 0
SS_Shift
Shift of Center Frequency when SS is
Enabled vs when it’s Disabled
RFREQ = 4.7kReg 1-18-00h to
30h, Reg 0-16 = 26h; Reg X-00 bit
6=0
SS_Mod
Spread Spectrum Modulation
Frequency
REG 1-18h Bit 7 = 0; Reg X-00 bit
6=0
30
53
80
kHz
SS_Mod
Spread Spectrum Modulation
Frequency
REG 1-18h Bit 7 = 1; Reg X-00 bit
6=0
15
34
55
kHz
Serial Interface AC Performance
PARAMETER
0.7
%
Standard conditions unless otherwise noted.
DESCRIPTION
CONDITIONS
MIN TYP MAX UNIT
FSER
SCLK Operating Range
Static logic not limited at low frequency
tEH
SEN “H” Time
@ 50MHz
320
ns
tEL
SEN “L” Time
@ 50MHz
160
ns
tERSR
SEN Rising Edge to the First SCLK Rising Edge @ 50MHz
10
ns
tCDS
SDIO Set Up Time
@ 50MHz
10
ns
tCDH
SDIO Hold Time
@ 50MHz
10
ns
tSREF
Last SCLK Rising Edge to SEN Falling Edge
@ 50MHz
10
ns
tCC
SCLK Cycle Time1
@ 50MHz
20
ns
Duty
SCLK “H” Duty Cycle
@ 50MHz
40
tCDD
SDIO Output Delay
@ 50MHz
tEDH
SDIO Output Hold Time
@ 50MHz
LVDS Specifications
PARAMETER
50
50
MHz
60
%
4
ns
2
ns
Standard conditions unless otherwise noted.
DESCRIPTION
CONDITIONS
MIN TYP MAX UNIT
VIN-HIGH
Maximum Single Line Voltage
2.4
V
VIN-LOW
Minimum Single Line Voltage
0
V
CIN
Input Capacitance
2
pF
RIN
Input Resistance
VMIN
Minimum Differential Voltage
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8
85
Signal tested with ±240mV differential input
240
100
115

mVPK
FN6909.3
December 3, 2015
ISL58781
Laser Driver AC Performance
PARAMETER
Demoboard test, 10% duty cycle pulse, load = equivalent circuitry to [laser + flex
cable] and/or as noted. VSO = 5V. TA = +25°C
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
tR-IOUTx
IOUT1/2 Write Rise Time (10% to 90%) 300mW Optical ML229U7 (Note 23)
1.3
ns
tF-IOUTx
IOUT1/2 Write Fall Time (10% to 90%)
300mW Optical ML229U7 (Note 23)
800
ps
O/S-IOUTx
IOUT1/2 Write Pulse Overshoot
300mW Optical ML229U7 (Note 23)
11
%
tD-IOUTx
IOUT1/2 Write Pulse Delay From
(Note 23)
LVDS = Zero crossing to IOUT rise 10%
5.3
ns
tR-BLUE
IBLUE Write Rise Time (10% to 90%)
250mW Optical (Note 23)
600
ps
tF-BLUE
IBLUE Write Fall Time (10% to 90%)
250mW Optical (Note 23)
450
ps
O/S-BLUE
IBLUE Write Pulse Overshoot
250mW Rising Optical (Note 23)
6
%
tD-BLUE
IBLUE Write Pulse Delay From
(Note 23)
LVDS = Zero crossing to IOUT rise 10%
5.2
ns
INOISE-IOUTx
IOUT1/2 Read Output Current Noise
IOUT = 50mA, measured @ 10MHz
0.55
nA/Hz
INOISE-IOUTx
IOUT1/2 Read & HFM Output Current
Noise
IOUT = 50mA+30mAP-P;
Measured @ 10MHz
0.96
nA/Hz
INOISE-BLUE
IBLUE Read Output Current Noise
IOUT = 50mA, measured @ 10MHz
0.37
nA/Hz
INOISE-BLUE
IBLUE Read & HFM Output Current Noise IOUT = 50mA+10mAP-P;
Measured @ 10MHz
0.47
nA/Hz
BWAPC
Read Amplifier 3dB Bandwidth
0.5
MHz
IOUT = 50mA
NOTE:
23. Limits established by characterization and are not production tested
TABLE 1. AMPLITUDE SELECTION REGISTER ACTIVATION
NAME
ENA
WEB
CR0
Bit 2
WEN2
WEN1
WEN0
MSB
BSEL = 0
LSB
BSEL = 0
MSB
BSEL = 1
LSB
BSEL = 1
OFF
0
X
x
X
X
X
X
X
X
X
READ
1
1
0
X
X
X
0-19
1-09
0-19
1-09
W0
1
0
1
0
0
0
0-10
2-10
0-11
2-11
W1
1
0
1
0
0
1
0-04
2-04
0-05
2-05
W2
1
0
1
0
1
0
0-06
2-06
0-07
2-07
W3
1
0
1
0
1
1
0-08
2-08
0-09
2-09
W4
1
0
1
1
0
0
0-0A
2-0A
0-0B
2-0B
W5
1
0
1
1
0
1
0-0C
2-0C
0-0D
2-0D
W6
1
0
1
1
1
0
0-0E
2-0E
0-0F
2-0F
W7
1
0
1
1
1
1
0-12
2-12
0-13
2-13
NOTES:
24. There are two sets of write current registers. When BSEL = 1, bank 1 is selected. When BSEL = 0, bank 0 is selected.
25. Read and write are independent. Read is enabled with a control bit.
26. Register terminology is page Number-Register number (hex). Thus 1-09 is page 1, register 09h
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FN6909.3
December 3, 2015
ISL58781
Applications Information
IOUT
The data sheet values for oscillator current, and write
current are based on an RSET of 620 when PMAX and
WriteDAC are both set to full scale. The user may choose
RSET to match the output current needs of the
application.
The PMAX DAC is biased by IRSET (= VRSET/RSET). See
the “Typical Performance Curves” on page 10.
The write channel output capability for a typical part is
shown in Figure 1. The amount of IOUT will be limited by
the available headroom voltage at the IOUTx pins.
A four input DAC (Reg 1-0A bits 3, 2, 1, 0) can be used
to control the amount of RC snubbing applied to the
outputs.
Read current may be controlled by either the Read DAC
or the IAPC input. When set by PREAD, IREAD is limited
to the data sheet value, whereas the IAPC input will allow
a significantly higher value to be obtained. The ReadDAC
and IAPC currents sum together.
Glitches could occur if two or three WEN lines are
changed simultaneously, and the propagation delay is
different for the two lines between the inner circuits of
the controller and the inner circuits of the LDD. Because
the WEN lines are encoded, the selected write current will
be correct before the change in code, and again after the
code changes. But some other output could result
momentarily if the propagation delays are not matched.
The skew detector detects the first rising edge at the
LVDS outputs.
FOSC
DAC. Although FOSC is relatively linear with DAC code,
monotonicity is not guaranteed (see Figure 5). Under
extreme conditions, where VSO = 4.5V and temperature
is +125°C, the HFM frequency is only capable of 900MHz
(see Figure 6).
The oscillator may be turned on either by the OSCEN
lines or by the WEN code selected. The particular code
that selects the oscillator is under program control. The
Pcool function is only available through the program
control and WEN selection.
The WEB enables write current. Thus WEN code 000 may
also select a write current.
Power
The main power consumption is caused by the headroom
voltage across the output stage (VSO - VIOUT) xIOUT. For
IOUT1 and IOUT2, the VSO can be reduced below 5.0V
(but above VSO-GOOD), as long as sufficient headroom
voltage is available to obtain the desired output current.
For the blue outputs, the built in ADC can be used to
obtain the output voltage, which is also the headroom
voltage. The HFM oscillator power consumption will
increase with increasing frequency and amplitude (see
Figure 7).
Note that in the QFN package, the die is mounted directly
on the thermal pad. This provides a very low thermal
resistance Junction to thermal pad of just a few °C/W.
The problem is in moving the heat from the thermal pad
to some other heat sink.
Figure 10 shows that when mounted well on a 4-layer
PCB with 3 ground plane layers, and an area of
10cmx10cm, the JA is +37°C/W. The typical application
will not afford this good of a heat sink.
Both FOSC and RFREQ may be chosen to accommodate
the desired range or operating point of the HFMFREQ
Typical Performance Curves
IOUT2 (mA)
1000
800
500
IOUT2 vs VHEAD vs PMAX CODE
3FFh
(REG 1-21 = 88h) (VSO = 4.5V)
(RSET = 620)
300h
200h
600
100h
400
80h
200
0
0.0
0.5
1.0
1.5 2.0 2.5 3.0
VHEADROOM (V)
3.5
FIGURE 1. IOUT WRITE CURRENT vs VSD vs
IPMAX_BIAS
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10
3FFh
400
40h
4.0 4.5
IBLUE (mA)
1200
300h
300
200h
200
100h
100
0
40h
001h
0
1
2
3
4
5
VHEADROOM (V)
6
7
8
FIGURE 2. IBLUE vs PMAX vs VHEADROOM
(VSO = 5.0V) (RSET = 620)
(1-21 = FFh), (RLOAD = 10)
FN6909.3
December 3, 2015
ISL58781
Typical Performance Curves
IBLUE (mA)
250
IBLUE vs VHEAD vs PMAX CO
(Reg 1-21 = 88h) (VSO = 4.5V)
200
300h
150
200h
100
100h
200
50
0
40h
0
1
2
3
4
VHEADROOM (V)
5
1000
6
1200
CR0 - 6 = 0b
400
CR0 - 6 = 1b
200
0x00
0x40
1
0x80
0xC0
4
VHEADROOM (V)
5
6
7
800
600
400
200
0
0x00
0xFF
0x40
0x80
0xC0
0xFF
HFMFREQ CODE
FIGURE 5. HFM CONTROL
FIGURE 6. HFM CONTROL; VSO = 4.5V;
TEMP = +125°C
90
10
80
HFMON = 80
HFMON = FF
70
60
50
40
HFMON = 01
0
HFMON = 40
100 200 300 400 500 600 700 800 900 1G
CHCLK FREQ (MHz)
FIGURE 7. HFM OSCILLATOR CURRENT
CONSUMPTION
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11
NOISE (nARMS/(Hz))
ISO CONSUMPTION (mA)
0.441mA
3
CR0 - 6 = 0b
HFMFREQ CODE
30
2
RFREQ = 3900
1000
800
0
0
FIGURE 4. IBLUE READ vs VHEADROOM vs IAPC,
(REG 1-212 = 88h) (VSO = 5.0V)
(RSET = 620)
RFREQ = 4700
600
0.836mA
0mA
FOSC (MHz)
1200
1.228mA
100
80h
0
1.622mA
150
50
FIGURE 3. IBLUE WRITE CURRENT vs VDS vs
IPMAX_BIAS
FOSC (MHz)
250
(RSET = 620)
3FFh
IBLUE (mA)
300
(Continued)
50mA + 30mAP-P
1.0
50mA
0.1
0.1
1M
10M
100M
FREQUENCY (Hz)
FIGURE 8. IOUTx NOISE vs FREQUENCY
FN6909.3
December 3, 2015
ISL58781
Typical Performance Curves
(Continued)
700
BANDWIDTH (kHz)
NOISE (nARMS/(÷Hz))
10.0
50mA + 10mAP-P
1.0
50mA
0.1
0.1
1M
10M
100M
600
500
400
300
200
0.0
0.6
FREQUENCY (Hz)
POWER DISSIPATION (W)
4.0
2.4
3.0
FIGURE 10. IOUT/IAPC BANDWIDTH vs IAPC
FIGURE 9. IBLUE NOISE vs FREQUENCY
4.5
1.2
1.8
IAPC (mA)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
3.378W
3.5

JA
=
3.0
2.5
2.0
QF
N2
8
+3
7°
C/
W
1.5
1.0
0.5
0
0
125
25
50
75 85
100
AMBIENT TEMPERATURE (°C)
150
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN6909.3
December 3, 2015
ISL58781
0.100 ±0.03
SEATING PLANE
0.00-0.05
0.2000
0.150 ±0.05
0.6250
NOTE: THE TIE BAR DIMENSIONS ARE
SUBJECT TO CHANGE WITHOUT NOTICE
FIGURE 12. TIE BAR LOCATION FOR 4X5 QFN
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FN6909.3
December 3, 2015
ISL58781
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
12/3/15
FN6909.3
Removed ISL58781CRZ-EVAL from Ordering Information table.
7/22/13
FN6909.2
Updated datasheet by changing Logo, removed side bar with part number, copyright on page 1
and changed Product Information verbiage to About Intersil verbiage on page 14.
11/12/09
FN6909.1
Added Figure 12 “TIE BAR LOCATION FOR 4X5 QFN” on page 13
Added “Pin Number” column to “Pin Descriptions” on page 3
On page 7: In HFM spec Table, for IMAX-RED-OFF-LINK, IMAX-RED-OFF-UNLINK & IMAXBLUE-OFF parameters, changed "HFMOFF = 0x7FF" test condition to "HFMOFF = 0xFFF": since
HFMOFF DAC is 12 bits now.
On page 7: In HFM spec Table, Reg 1-21h=x7h for Imax_Blue_ON:
Imax_Blue_On (Blue HFM ON amplitude) does not depend on Reg 1-21h setting.
So, deleted "Reg 1-21h=x7h" condition
9/2/09
FN6909.0
Initial release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN6909.3
December 3, 2015
ISL58781
Package Outline Drawing
L28.4x5A
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 06/08
2.50
4.00
B
22
5.00
PIN #1 INDEX AREA
28
23
6
PIN 1
INDEX AREA
(4X)
6
24X 0.50
A
1
3.50
Exp. DAP
3.50
0.10 M C A B
4
28X 0.25
0.15
8
15
9
14
SIDE VIEW
TOP VIEW
2.50
Exp. DAP
28X 0.400
BOTTOM VIEW
SEE DETAIL "X"
( 3.80 )
0.10 C
Max 0.90
( 2.50)
C
SEATING PLANE
0.08 C
SIDE VIEW
( 4.80 )
( 24X 0.50)
( 3.50 )
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
(28X .250)
DETAIL "X"
( 28 X 0.60)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6.
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15
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6909.3
December 3, 2015
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