DN1032 - DC Accurate Driver for the LTC2377-20 Achieves 2ppm Linearity

DC Accurate Driver for the LTC2377-20 Achieves
2ppm Linearity – Design Note 1032
Guy Hoover
Introduction
As resolution and sample rates continue to rise for
analog-to-digital converters (ADCs), the driver circuitry
for the ADC analog input, not the ADC itself, has increasingly become the limiting factor in determining
overall circuit accuracy. First, the driver circuitry must
buffer the input signal and provide gain. In addition,
it must level shift or convert a single-ended signal to
a fully differential signal to satisfy the input voltage
range and common mode requirements of the ADC.
All must be done without adding distortion to the
original signal.
by the LTC2377-20 (U1). The LTC2377-20 is a 20-bit,
500ksps, low power SAR ADC with a typical integral
nonlinearity (INL) of ±0.5ppm. The voltage at AIN is
buffered by U4, which in turn drives the U5 resistor
string, acting as a precision divider. U3 operates in
a gain of minus one-half and drives the center of the
U5 resistor string to maintain the ADC common mode
voltage at VREF/2.
U3 and U4 are LT®1468A low offset highly linear
op amps. U5 is a LT5400A quad matched resistor
network with a guaranteed maximum mismatch of
0.01%. Matched resistor values in U5 are important
because any mismatch contributes to both offset
and full-scale error in this circuit. For this reason and
because of their extremely low voltage coefficient, do
not use discrete resistors instead of the LT5400A. R4
provides a quarter-scale shift to the output of U3. R1
This Design Note presents a simple ADC driver circuit that converts a ±10V single-ended input signal
into a fully differential signal capable of driving the
LTC ®2377-20 20-bit SAR ADC with a combined linearity error of only 2ppm. Options for providing higher
input impedance and a lower overall supply current
are also examined.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered
trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
Circuit Description
The circuit of Figure 1 converts a ±10V single-ended
signal into the ±5V fully differential signal required
C11
0.1µF
VREF
3
4
SHDN
GND
VIN
OUTF
GND
OUTS
GND
GND
C6
10µF
7
6
5
V+
OUT
–IN
R2
10k
R5
10k
8
2
1k
7
6
V–
4
1k
3
–15V
C2
10µF
4
1k
1k
9
6
C9
10µF
4
C10
220pF
C0G
5
5
C12
220pF
C0G
2 15 7
IN+
REF
7
1
U1
LTC2377-20
–
IN
3
6
8
CNV
SCK
SDO
CHAIN
2
+IN
C1
10µF
REF/DGC
3
C3
10µF
R6
20k
R4
20k
U3
LT1468A
GND
R1
10k
GND
–15V
C5
10µF
C7
2.5V 0.1µF
U5
LT5400A-4
15V
BUSY
RDL/SDI
10 16 1
DN4GH2 F01
C4
10pF
C0G
Figure 1. ±10V Input Range, 20-Bit, 500ksps Data Acquisition System with 2ppm INL
01/16/1032
C14
0.1µF
C13
47µF
10V
X7R
1210
3.3V
6
VDD
7
V+
OUT
V–
4
8
OVDD
3
+IN
C8
3300pF
C0G 2
–IN
2
GND
R3
49.9Ω
U4
LT1468A
10V
U2
LTC6655AHMS8-5
GND
J1
AIN
±10V
15V
1
9
13
14
11
12
CNV
SCK
SDO
BUSY
and R2 form a divider that biases the noninverting
input of U3 at VREF/2.
VOS(MAX) = BZE(Max)U1 + VOS(MAX)U4/2 +
(VREF/2 – VREF/(2 + ∆R/R(Max)U5))
R5 and R6 set the gain of inverting amplifier U3 at –0.5.
C10 and C12 in combination with the resistors of U5
form 1.4MHz filters on the ADC inputs. Additionally, the
resistor between Pins 1 and 8 of U5 helps to isolate the
output of U4 from the charge spike that occurs when
the ADC goes from hold mode to sample mode. The
LTC6655A-5 (U2) was selected as the reference for
this circuit due to its ability to settle quickly from the
transients that occur on the REF pin during conversions and because of its low noise.
VOS(MAX) = 13ppm • 10µV/ppm + 75µV/2 +
(5/2 – 5/(2.0001)) • 1E6µV
Circuit Performance
Typical AC performance for this circuit includes THD
of –123.5dB and SNR of 102.7dBFS at a sample rate of
500ksps with a 100Hz input signal. This performance
can be seen in the FFT of Figure 2. The THD and SNR
performance are close to the typical numbers found
in the LTC2377-20 data sheet, indicating minimal
performance degradation when using this driver.
Typical linearity performance for the combined circuit
over the entire ±10V input signal range, as shown
in Figure 3, is +2ppm, –1.3ppm at a sample rate of
500ksps. Linearity is limited by the INL of the ADC
and the CMRR of op amp U4.
The combined offset at the ADC input, including the
contributions of U4, U5 and U1, was measured at
+50µV. The offset of U3 has no effect on the offset of
this driver. A worst case analysis of offset at the ADC
input is calculated by adding the maximum offsets
of U1, U4 and U5:
0
The LT1468A has a maximum input bias current of
±40nA. For applications that require higher input impedance, U4 can be replaced with the LT1122A. The
LT1122A is a fast settling, JFET input op amp with a
maximum input bias current of 75pA. Using the LT1122A
in this circuit, the INL is +6ppm, –1.1ppm, as shown in
the op amp performance comparison in Table 1.
The LTC2377-20 ADC has a typical supply current
of 4.2mA at its full sample rate of 500ksps. The
LTC2377‑20 automatically powers down after a conversion and does not power up until the next conversion
is started. This auto power-down feature reduces the
power dissipation of the ADC as the sample rate is
reduced to as little as 1µA for very low sample rate
applications.
For low sample rate applications where supply current
is important, the 5.2mA maximum supply current of
the LT1468A may be too high. The LT1012A picoamp
input current, microvolt offset, low noise op amp
with a maximum supply current of 500µA at ±15V
can replace the LT1468A for these applications. With
sample rates up to 125ksps the LT1012A achieved a
linearity of +0.9ppm, –0.5ppm, as shown in the op
amp performance comparison in Table 1. At sample
rates above 125ksps the INL performance begins to
degrade, as the op amp cannot settle fast enough to
accurately drive the ADC.
5
fS = 500ksps
fIN = 99.182Hz
SNR = 102.7dBFS
THD = –123.5dB
–20
–40
4
3
2
–60
INL (ppm)
AMPLITUDE (dB)
VOS(MAX) = 292µV = 29.2ppm
–80
–100
–120
1
0
–1
–2
–140
–3
–160
–4
–180
–5
–10
0
50
150
100
FREQUENCY (kHz)
200
250
DN4GH2 F02
Figure 2. Combined Circuit FFT
–5
0
AIN (V)
5
10
DN4GH2 F03
Figure 3. Linearity vs Input Voltage
Conclusion
The ADC driver circuit shown here converts a singleended ±10V signal into a ±5V fully differential signal
for the LTC2377-20 500ksps SAR ADC. Combined
circuit performance achieves 50µV offset, 2ppm
INL, 102.7dBFS SNR and –123.5dB THD. The driver
consists primarily of two LT1468A op amps and a
LT5400A matched resistor array. Alternative versions
of this circuit use the LT1122A op amp to provide 75pA
max input current or the LT1012A op amp at reduced
sampling rates to reduce supply current. DC2135, a
demo board version of this circuit, is available from
Linear Technology.
Table 1. Op Amp Performance Comparison
MAX
MAX IB TYP ISY MAX fS
VOS (µV) (pA)
(mA) (ksps)
TYP INL
(ppm)
LT1468A
75
40,000
5.2
500
+2, –1.3
LT1122A
600
75
10
500
+6, –1.1
LT1012A
90
150
0.6
125
+0.9, –0.5
Data Sheet Download
www.linear.com/LTC2377-20
Linear Technology Corporation
For applications help,
call (408) 432-1900
dn1032fa LT 0116 REV A • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
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 LINEAR TECHNOLOGY CORPORATION 2013
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