LTC6268/LTC6269 500MHz Ultra-Low Bias Current FET Input Op Amp FEATURES DESCRIPTION Gain Bandwidth Product: 500MHz n –3dB Bandwidth (A = 1): 350MHz n Low Input Bias Current: ±3fA Typ. Room Temperature 4pA Max at 125°C n Current Noise (100kHz): 5.5fA/√Hz n Voltage Noise (1MHz): 4.3nV/√Hz n Extremely Low C 450fF IN n Rail-to-Rail Output n Slew Rate: 400V/µs n Supply Range: 3.1V to 5.25V n Quiescent Current: 16.5mA n Harmonic Distortion (2V P-P): –100dB at 1MHz –80dB at 10MHz n Operating Temp Range: –40°C to 125°C n Single in 8-Lead SO-8, 6-Lead TSOT-23 Packages n Dual in 8-Lead MS8, 3mm × 3mm 10-Lead DFN 10 Packages The LTC®6268/LTC6269 is a single/dual 500MHz FET-input operational amplifier with extremely low input bias current and low input capacitance. It also features low inputreferred current noise and voltage noise making it an ideal choice for high speed transimpedance amplifiers, CCD output buffers, and high-impedance sensor amplifiers. Its low distortion makes the LTC6268/LTC6269 an ideal amplifier for driving SAR ADCs. n APPLICATIONS n n n n n It operates on 3.1V to 5.25V supply and consumes 16.5mA per amplifier. A shutdown feature can be used to lower power consumption when the amplifier is not in use. The LTC6268 single op amp is available in 8-lead SOIC and 6-lead SOT-23 packages. The SOIC package includes two unconnected pins which can be used to create an input pin guard ring to protect against board leakage currents. The LTC6269 dual op amp is available in 8-lead MSOP with exposed pad and 3mm × 3mm 10-lead DFN packages. They are fully specified over the –40°C to 85°C and the –40°C to 125°C temperature ranges. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Trans-Impedance Amplifiers ADC Drivers CCD Output Buffer Photomultiplier Tube Post-Amplifier Low IBIAS Circuits 20kΩ TIA Frequency Response TYPICAL APPLICATION 100 20kΩ Gain 65MHz Trans-Impedance Amplifier 90 PARASITIC FEEDBACK C 80 GAIN (dBΩ) 20kΩ* 2.5V 2.5V PD – IPD LTC6268 + –2.5V VOUT = –IPD • 20k BW = 65MHz 70 60 50 40 0.01 6268 TA01 PD = OSI OPTOELECTRONICS, FCI-125G-006 *TWO 40.2kΩ 0603 PACKAGE RESISTORS IN PARALLEL 0.1 1 10 FREQUENCY (MHz) 100 1000 6268 TA02 62689f For more information www.linear.com/LTC6268 1 LTC6268/LTC6269 ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage V+ to V–............................................5.5V Input Voltage ................................V– – 0.2V to V+ + 0.2V Input Current (+IN, –IN)(Note 2)............................. ±1mA Input Current (SHDN)............................................. ±1mA Output Current (IOUT ) (Note 8, 9)..........................135mA Output Short-Circuit Duration (Note 3).... Thermally Limited Operating Temperature Range LTC6268I/LTC6269I..............................–40°C to 85°C LTC6268H/LTC6269H......................... –40°C to 125°C Specified Temperature Range (Note 4) LTC6268I/LTC6269I..............................–40°C to 85°C LTC6268H/LTC6269H......................... –40°C to 125°C Maximum Junction Temperature........................... 150°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec).................... 300°C PIN CONFIGURATION TOP VIEW TOP VIEW NC 1 8 SHDN –IN 2 7 V+ +IN 3 6 OUT NC 4 5 V– 6 V+ OUT 1 V– 2 5 SHDN +IN 3 4 –IN S6 PACKAGE 6-LEAD PLASTIC TSOT-23 S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 192°C/W (NOTE 5) TJMAX = 150°C, θJA = 120°C/W (NOTE 5) TOP VIEW TOP VIEW OUTA –INA +INA V– 1 2 3 4 9 V– 8 7 6 5 V+ OUTB –INB +INB MS8E PACKAGE 8-LEAD PLASTIC MSOP OUTA 1 –INA 2 +INA 3 V– 4 SDA 5 10 V+ 11 V– 9 OUTB 8 –INB 7 +INB 6 SDB DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 40°C/W (NOTE 5) EXPOSED PAD (PIN 9) IS V–, IT IS RECOMMENDED TO SOLDER TO PCB TJMAX = 150°C, θJA = 43°C/W (NOTE 5) EXPOSED PAD (PIN 11) IS V–, IT IS RECOMMENDED TO SOLDER TO PCB 62689f 2 For more information www.linear.com/LTC6268 LTC6268/LTC6269 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6268IS6#TRMPBF LTC6268IS6#TRPBF LTGFS 6-Lead Plastic TSOT-23 –40°C to 85°C LTC6268HS6#TRMPBF LTC6268HS6#TRPBF LTGFS 6-Lead Plastic TSOT-23 –40°C to 125°C LTC6268IS8#PBF LTC6268IS8#TRPBF 6268 8-Lead Plastic SOIC –40°C to 85°C LTC6268HS8#PBF LTC6268HS8#TRPBF 6268 8-Lead Plastic SOIC –40°C to 125°C LTC6269IMS8E#PBF LTC6269IMS8E#TRPBF LTGFP 8-Lead Plastic MSOP –40°C to 85°C LTC6269HMS8E#PBF LTC6269HMS8E#TRPBF LTGFP 8-Lead Plastic MSOP –40°C to 125°C LTC6269IDD#PBF LTC6269IDD#TRPBF LGFN 10-Lead Plastic DD –40°C to 85°C LTC6269HDD#PBF LTC6269HDD#TRPBF LGFN 10-Lead Plastic DD –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 5.0V ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VSUPPLY = 5.0V (V+ = 5V, V– = 0V, VCM = mid-supply), RL = 1kΩ, CL = 10pF, VSHDN is unconnected. SYMBOL PARAMETER VOS Input Offset Voltage CONDITIONS MIN TYP MAX VCM = 2.75V 0.2 l –0.7 –2.5 0.7 2.5 mV mV –1.0 –4.5 0.2 l 1.0 4.5 mV mV VCM = 4.0V TC VOS Input Offset Voltage Drift VCM = 2.75V IB Input Bias Current (Notes 6, 8) VCM = 2.75V LTC6268I/LTC6269I LTC6268H/LTC6269H –20 –900 –4 ±3 l l 20 900 4 fA fA pA VCM = 4.0V LTC6268I/LTC6269I LTC6268H/LTC6269H –20 –900 –4 ±3 l l 20 900 4 fA fA pA VCM = 2.75V LTC6268I/LTC6269I LTC6268H/LTC6269H –40 –450 –2 ±6 l l 40 450 2 fA fA pA IOS en Input Offset Current (Notes 6, 8) 4 UNITS μV/°C Input Voltage Noise Density, VCM = 2.75V f = 1MHz 4.3 nV/√Hz Input Voltage Noise Density, VCM = 4.0V f = 1MHz 4.9 nV/√Hz Input Referred Noise Voltage f = 0.1Hz to 10Hz 13 μVP-P Input Current Noise Density, VCM = 2.75V f = 100kHz 5.5 fA/√Hz Input Current Noise Density, VCM = 4.0V f = 100kHz 5.3 fA/√Hz RIN Input Resistance Differential >1000 GΩ Common Mode >1000 GΩ CIN Input Capacitance Differential (DC to 200MHz) CMRR Common Mode Rejection Ratio VCM = 0.5V to 3.2V (PNP Side) in 100 Common Mode (DC to 100MHz) 450 fF 90 l 72 70 dB dB 64 52 82 l dB dB l 0 VCM = 0V to 4.5V IVR Input Voltage Range Guaranteed by CMRR fF 4.5 V 62689f For more information www.linear.com/LTC6268 3 LTC6268/LTC6269 5.0V ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VSUPPLY = 5.0V (V+ = 5V, V– = 0V, VCM = mid-supply), RL = 1kΩ, CL = 10pF, VSHDN is unconnected. SYMBOL PARAMETER CONDITIONS PSRR VCM = 1.0V, VSUPPLY Ranges from 3.1V to 5.25V Power Supply Rejection Ratio Supply Voltage Range AV Open Loop Voltage Gain VOUT = 0.5V to 4.5V MIN TYP 95 l 78 75 l 3.1 125 40 250 l V/mV V/mV 10 2 21 l V/mV V/mV RLOAD = 10k RLOAD = 100 VOL Output Swing Low (Input Overdrive 30mV) Measured from V– ISINK = 10mA Output Swing High (Input Overdrive 30mV) Measured from V+ ISOURCE = 10mA 140 200 mV mV 130 200 260 mV mV 70 140 200 mV mV 160 270 370 mV mV l ISOURCE = 25mA l ISC IS Output Short Circuit Current (Note 9) 60 40 90 l 15 9 16.5 l 18 23 mA mA 0.39 0.85 1.2 mA mA 2 2 12 12 µA µA 0.75 V Supply Current Per Amplifier Supply Current in Shutdown (Per Amplifier) dB dB 80 l VOH UNITS 5.25 l ISINK = 25mA MAX l ISHDN Shutdown Pin Current VSHDN = 0.75V VSHDN =1.50V l l VIL SHDN Input Low Voltage Disable l l –12 –12 mA mA VIH SHDN Input High Voltage Enable. If SHDN is Unconnected, Amp is Enabled tON Turn On Time, Delay from SHDN Toggle to Output Reaching 90% of Target SHDN Toggle from 0V to 2V, AV = 1 580 ns tOFF Turn Off Time, Delay from SHDN Toggle to Output High Z SHDN Toggle from 2V to 0V, AV = 1 480 ns BW –3dB Closed Loop Bandwidth AV = 1 350 MHz GBW Gain-Bandwidth Product f = 10MHz 500 MHz tS Settling Time, 1V to 4V, Unity Gain 0.1% 17 ns SR+ Slew Rate+ AV = 6 (RF = 499, RG = 100) VOUT = 0.5V to 4.5V, Measured 20% to 80%, CLOAD = 10pF 300 200 400 l V/µs V/µs AV = 6 (RF = 499, RG = 100) VOUT = 4.5V to 0.5V, Measured 80% to 20%, CLOAD = 10pF 180 130 260 l V/µs V/µs 21 MHz SR– Slew Rate– 1.5 400 V FPBW Full Power Bandwidth (Note 7) 4VP-P HD Harmonic Distortion(HD2/HD3) A = 1, 10MHz. 2VP-P, VCM = 1.75V, RL = 1k –81/–90 dB THD+N Total Harmonic Distortion and Noise A = 1, 10MHz. 2VP-P, VCM = 1.75V, RL = 1k 0.01 –79.6 % dB ILEAK Output Leakage Current in Shutdown VSHDN = 0V, VOUT = 0V VSHDN = 0V, VOUT = 5V 400 400 nA nA 62689f 4 For more information www.linear.com/LTC6268 LTC6268/LTC6269 3.3V ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VSUPPLY = 3.3V (V+ = 3.3V, V– = 0V, VCM = mid-supply), RL = 1kΩ, CL = 10pF, VSHDN is unconnected. SYMBOL PARAMETER VOS Input Offset Voltage CONDITIONS MIN TYP MAX VCM = 1.0V 0.2 l –0.7 –2.5 0.7 2.5 mV mV –1.0 –4.5 0.2 l 1.0 4.5 mV mV ±3 l l –20 –900 –4 20 900 4 fA fA pA VCM = 2.3V –20 ±3 l LTC6268I/LTC6269I –900 l –4 LTC6268H/LTC6269H 20 900 4 fA fA pA VCM = 1.0V –40 ±6 l LTC6268I/LTC6269I –450 l –2 LTC6268H/LTC6269H 40 450 2 fA fA pA VCM = 2.3V TC VOS Input Offset Voltage Drift VCM = 1.0V IB Input Bias Current (Notes 6, 8) VCM = 1.0V LTC6268I/LTC6269I LTC6268H/LTC6269H 4 UNITS µV/C IOS Input Offset Current (Notes 6, 8) en Input Voltage Noise Density, VCM =1.0V f = 1MHz 4.3 nV/√Hz Input Voltage Noise Density, VCM = 2.3V f = 1MHz 4.9 nV/√Hz Input Referred Noise Voltage 13 μVP-P Input Current Noise Density, VCM = 1.0V f = 100kHz 5.6 fA/√Hz Input Current Noise Density, VCM = 2.3V f = 100kHz 5.3 fA/√Hz in f = 0.1Hz to 10Hz RIN Input Resistance Differential Common Mode >1000 >1000 CIN Input Capacitance Differential (DC to 200MHz) Common Mode (DC to 100MHz) CMRR Common Mode Rejection Ratio VCM = 0.5V to 1.2V (PNP Side) Input Voltage Range Guaranteed by CMRR AV Open Loop Voltage Gain VOUT = 0.5V to 2.8V Output Swing Low (Input Overdrive 30mV). Measured from V– fF fF 63 60 100 dB dB 60 50 77 l dB dB l 0 200 l 80 40 V/mV V/mV 10 2 18 l V/mV V/mV RLOAD = 10k RLOAD = 100 VOL 100 450 l VCM = 0V to 2.8V (Full Range) IVR ISINK = 10mA 2.8 ISINK = 25mA Output Swing High (Input Overdrive 30mV). Measured from V+ ISOURCE = 10mA 140 200 mV mV 140 200 260 mV mV 80 140 200 mV mV 170 270 370 mV mV l ISOURCE = 25mA l ISC IS Output Short Circuit Current (Note 9) 50 35 80 l 14.5 9 16 l Supply Current per Amplifier V 80 l l VOH GΩ GΩ mA mA 17.5 23 mA mA 62689f For more information www.linear.com/LTC6268 5 LTC6268/LTC6269 3.3V ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VSUPPLY = 3.3V (V+ = 3.3V, V– = 0V, VCM = mid-supply) RL = 1kΩ, CL = 10pF, VSHDN is unconnected. SYMBOL PARAMETER CONDITIONS MIN Supply Current in Shutdown (Per Amplifier) TYP MAX 0.23 0.6 0.8 mA mA 2 2 12 12 µA µA 0.75 V l ISHDN Shutdown Pin Current VSHDN = 0.75V VSHDN = 1.5V l l VIL SHDN Input Low Voltage Disable l Enable. If SHDN is Unconnected, Amp Is Enabled l –12 –12 UNITS VIH SHDN Input High Voltage tON Turn On Time, Delay from SHDN Toggle SHDN Toggle from 0V to 2V to Output Reaching 90% of Target 710 ns tOFF Turn Off Time, Delay from SHDN Toggle SHDN Toggle from 2V to 0V to Output High Z 620 ns BW –3dB Closed Loop Bandwidth AV = 1 GBW Gain-Bandwidth Product f = 10MHz SR+ Slew Rate+ AV = 6 (RF = 499, RG = 100), VOUT = 0.5V to 2.8V, Measured 20% to 80%, CLOAD = 10pF AV = 6 (RF = 499, RG = 100), VOUT = 2.8V to 0.5V, Measured 80% to 20%, CLOAD = 10pF SR– Slew Rate– 1.5 V 350 MHz 370 420 MHz 300 200 400 l V/µs V/µs 180 130 260 l V/µs V/µs 40 MHz FPBW Full Power Bandwidth (Note 7) 2VP-P HD Harmonic Distortion(HD2/HD3) A = 1, 10MHz. 1VP-P, VCM = 1.65V, RL = 1k –81/–90 dB THD+N Total Harmonic Distortion and Noise A = 1, 10MHz. 1VP-P, VCM = 1.65V, RL = 1k 0.01 –78 % dB Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The inputs are protected by two series connected ESD protection diodes to each power supply. The input current should be limited to less than 1mA. The input voltage should not exceed 200mV beyond the power supply. Note 3: A heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely. Note 4: The LTC6268I/LTC6269I is guaranteed to meet specified performance from –40°C to 85°C. The LTC6268H/LTC6269H is guaranteed to meet specified performance from –40°C to 125°C. Note 5: Thermal resistance varies with the amount of PC board metal connected to the package. The specified values are for short traces connected to the leads. Note 6: The input bias current is the average of the currents into the positive and negative input pins. Typical measurement is for S8 package. Note 7: Full Power Bandwidth is calculated from slew rate using the following equation: FPBW = SR/(2π • VPEAK) Note 8: This parameter is specified by design and/or characterization and is not tested in production. Note 9: The LTC6268/LTC6269 is capable of producing peak output currents in excess of 135mA. Current density limitations within the IC require the continuous current supplied by the output (sourcing or sinking) over the operating lifetime of the part be limited to under 135mA (Absolute Maximum). 62689f 6 For more information www.linear.com/LTC6268 LTC6268/LTC6269 TYPICAL PERFORMANCE CHARACTERISTICS Input Offset Voltage Distribution 300 250 TA = 25°C, unless otherwise noted. Input Offset Voltage vs Temperature Input Offset Voltage Distribution 250 VS = ±2.5V VCM = 0.25V 2 VS = ±2.5V VCM = 1.5V 200 VOS (mV) 150 150 100 50 50 0 –0.4 –0.3 –0.2 –01 0 0.1 0.2 0.3 0.4 0.5 0.6 VOS (mV) 6268 G03 6268 G02 Input Offset Voltage vs Common Mode Voltage 1 0.8 8 VOS (mV) 7 6 5 4 Input Offset Voltage vs Supply Voltage 1 VS– = 0V, VS+ = 3.1V to 5.25V 0.8 VCM = 1V VS = ±2.5V 0.6 0.6 0.4 0.4 0.2 0.2 VOS (mV) VS = ±2.5V VCM = 0.25V 9 –1 –50 –30 –10 10 30 50 70 90 110 130 150 TEMPERATURE (°C) 0 –0.4 –0.3 –0.2 –01 0 0.1 0.2 0.3 0.4 0.5 0.6 VOS (mV) Input Offset Drift Distribution H-GRADE I-GRADE 0 –0.2 0 –0.2 3 –0.4 –0.4 2 –0.6 –0.6 1 –0.8 –0.8 0 –8 –6 –4 –2 0 2 4 6 DISTRIBUTION (µV/°C) 8 VCM = 0.25V –0.5 6268 G01 NUMBER OF UNITS 0.5 0 100 10 VCM = 1.0V 1 200 11 VS = ±2.5V 1.5 –1 –2.5 10 –1.25 0 1.25 –1 2.5 3.5 3 VCM (V) 6268 G04 4 4.5 VS (V) 5 6268 G06 6268 G05 Input Offset Voltage vs Output Current 1.40 PSRR vs Frequency 100 VS = ±2.5V 0.80 60 VCM = 1.5V 0.60 0.40 0.20 0.00 100 VS = ±2.5V VCM = 0.25V –PSRR PSRR (dB) VOS (mV) 1.00 VS = ±2.5V VCM = 0.25V 80 1.20 CMRR vs Frequency 120 VCM = 0.25V –0.20 –100 –80 –60 40 –20 0 20 40 60 80 100 OUTPUT CURRENT (mA) 6268 G07 80 CMRR (dB) 1.60 5.5 +PSRR 40 60 20 40 0 20 –20 0.01 0.1 1 10 100 FREQUENCY (MHz) 1000 6268 G08 0 0.01 0.1 1 10 FREQUENCY (MHz) 100 1000 6268 G09 62689f For more information www.linear.com/LTC6268 7 LTC6268/LTC6269 TYPICAL PERFORMANCE CHARACTERISTICS Input Bias Current vs Common Mode Voltage Input Bias Current vs Supply Voltage 8.0 –1 VS = ±2.5V 1400 VCM = 0.25V 6.0 –2 1200 4.0 100 +IN 2.0 0 0.0 –2.0 –IN –100 –4.0 –6.0 –200 INPUT BIAS CURRENT (fA) INPUT BIAS CURRENT (fA) 200 0 1.0 2.0 3.0 4.0 COMMON MODE VOLTAGE (V) –4 +IN –5 –6 –7 –10.0 5.0 6268 G10 80 TA = 125°C TA = 25°C TA = –55°C 5.0 10.0 15.0 20.0 LOAD CURRENT (mA) –40 –160 100 SINKING 50 TA = 125°C TA = 25°C TA = –55°C 0 –50 –200 –240 –150 VS = ±2.5V VCM = 0.25V 5.0 10.0 15.0 20.0 LOAD CURRENT (mA) 25.0 –200 3.0 4 3 2 3.5 4.0 4.5 VS (V) 5.0 0.1Hz to 10Hz Output Voltage Noise 20 VS = ±2.5V VCM = 0.25V 5 5.5 6268 G15 VS = ±2.5V VCM = 0.25V 16 12 VOLTAGE NOISE (µV) 5 SOURCING –100 6 VOLTAGE NOISE (nV/√Hz) VOLTAGE NOISE (nV/√Hz) 6 4 3 2 8 4 0 –4 –8 –12 1 1 0 10k VS = ±2.5V 150 VCM = 0.25V 6268 G14 VS = ±2.5V VCM = 0.25V 125 200 Wide Band Input Referred Voltage Noise 7 65 85 105 TEMPERATURE (°C) Output Short Circuit Current vs Supply Voltage –120 –280 0.0 25.0 8 45 6268 G12 –80 Input Referred Voltage Noise 9 400 –200 25 5.5 TA = 125°C TA = 25°C TA = –55°C 6268 G13 10 600 0 ISC (mA) 120 OUTPUT SATURATION VOLTAGE (mV) OUTPUT SATURATION VOLTAGE (mV) 0 160 0 0.0 800 Output Saturation Voltage vs Load Current (Output High) VS = ±2.5V VCM = 0.25V 40 1000 6268 G11 Output Saturation Voltage vs Load Current (Output Low) 200 +IN –IN 200 –IN –8 –9 VS = 3.1V TO 5.25V VCM = 1.0V –10 3.5 4.0 4.5 5.0 3.0 SUPPLY VOLTAGE (V) –8.0 –300 0.0 –3 CURRENT (fA) VS = 5V Input Bias Current vs Temperature 1600 10.0 INPUT BIAS CURRENT (fA) 300 TA = 25°C, unless otherwise noted. –16 100k FREQUENCY (Hz) 1M 0 0 20 40 60 FREQUENCY (MHz) 80 6268 G16 100 6268 G17 –20 0 1 2 3 4 5 6 TIME (s) 7 8 9 10 6268 G18 62689f 8 For more information www.linear.com/LTC6268 LTC6268/LTC6269 TYPICAL PERFORMANCE CHARACTERISTICS 0.1Hz to 10Hz Output Voltage Noise 20 Input Referred Current Noise 100 VS = ±2.5V VCM = 1.5V 16 0 –4 –8 –12 50 10 1 2 3 4 5 6 TIME (s) 7 8 9 0.1 10 1 10 FREQUENCY (MHz) 100 Output Impedance vs Frequency 1000 1 0.1 AV = 100 AV = 10 AV = 1 0.01 0.001 0.001 0.01 0.1 1 10 FREQUENCY (MHz) 100 VS = ±2.5V VOUT = 2VP-P –40 RL = 1k AV = 1 VCM = –0.75V –60 –80 2ND –100 3RD –140 0.1 1 FREQUENCY (MHz) 6268 G22 Harmonic Distortion vs Amplitude 70 60 VOUT (mV) DISTORTION (dB) VS = ±2.5V VCM = –0.75V –40 RL = 1k AV = 1 fO = 10MHz –60 2ND HD 3RD HD 0.5 0.75 1 1.25 1.5 AMPLITUDE (VP-P) 1.75 2 6268 G25 –160 –180 1000 10 100 FREQUENCY (MHz) Harmonic Distortion vs Amplitude VS = ±2.5V VCM = –0.75V –40 RL = 1k AV = 1 fO = 1MHz –60 –80 2ND HD –100 3RD HD –120 10 –140 0.5 1 1.5 AMPLITUDE (VP-P) 2 6268 G24 50mV Step Response 80 VCM = 4.5V VCM = 2.5V VCM = 0.5V 70 60 50 50 40 40 30 20 10 0 –120 –140 0.25 –140 50mV Step Response 80 –100 –10 6268 G23 –20 –80 –120 –20 –120 1000 –100 0 Harmonic Distortion vs Frequency 10 –80 PHASE 10 6268 G21 –20 VS = ±2.5V VCM = 0.25V DISTORTION (dB) OUTPUT IMPEDANCE (Ω) 100 –60 6268 G20 6268 G19 DISTORTION (dB) 1 20 VS = ±2.5V –20 VCM = 0.25V A = 1000 –30 1 0.1 VOUT (mV) 0 –40 GAIN 30 –16 –20 0 RL = 1k, CL = 10pF RL = 1k, CL = 0pF –20 PHASE 4 VS = ±2.5V VCM = 0.25V GAIN (dB) 8 Gain and Phase vs Frequency 60 40 CURRENT NOISE (pA/√Hz) 12 VOLTAGE NOISE (µV) TA = 25°C, unless otherwise noted. –10 AV = 1 VS = 0, 5V –20 VCM = 0.5V, 2.5V, 4.5V RLOAD = 1k –30 0 5 10 15 20 25 30 35 40 45 50 TIME (nS) 6268 G26 VCM = 4.5V VCM = 2.5V VCM = 0.5V 30 20 10 0 –10 AV = 1 VS = 0, 5V –20 VCM = 0.5V, 2.5V, 4.5V RLOAD = 1k, CLOAD = 10pF –30 0 5 10 15 20 25 30 35 40 45 50 TIME (nS) 6268 G26a 62689f For more information www.linear.com/LTC6268 9 LTC6268/LTC6269 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. Large Signal Response 3.0 Supply Current vs Supply Voltage VS = ±2.5V, AV = 1, RLOAD = 1k 2.5 30 VS– = 0V 27 VCM = 1V AV = 1 24 2.0 1.5 SUPPLY CURRENT (mA) VOUT (V) 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 18 15 12 9 6 –2.5 –3.0 21 CLOAD = 0pF 20 0 40 60 TIME (nS) CLOAD = 10pF 80 3 100 0 3.0 6268 G27 TA = 125°C TA = 25°C TA = –55°C 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6268 G28 Supply Current vs Shutdown Voltage Supply Current vs Shutdown Voltage SUPPLY CURRENT (mA) 20 25 VS = 0V, 5V VCM = 2.75V AV = 1 20 SUPPLY CURRENT (mA) 25 15 10 5 0 0.0 TA = 125°C TA = 25°C TA = –55°C VS = 0V, 3.1V VCM = 1V AV = 1 15 10 5 0.5 1.0 1.5 SHUT DOWN VOLTAGE (V) 2.0 0 0.0 6268 G29 TA = 125°C TA = 25°C TA = –55°C 0.5 1.0 1.5 SHUT DOWN VOLTAGE (V) 2.0 6268 G30 62689f 10 For more information www.linear.com/LTC6268 LTC6268/LTC6269 PIN FUNCTIONS V–: Negative Power Supply. Normally tied to ground, it can also be tied to a voltage other than ground as long as the voltage difference between V+ and V– is between 3.1V and 5.25V. If it is not connected to ground, bypass it to ground with a capacitor of 0.1µF as close to the pin as possible. –IN: Inverting Input of the Amplifier. The voltage range of this pin is from V– to V+ –0.5V. +IN: Non-Inverting Input. The voltage range of this pin is from V– to V+ –0.5V. V+: Positive Power Supply. Total supply (V+ – V–) voltage is from 3.1V to 5.25V. Split supplies are possible as long as the total voltage between V+ and V– is between 3.1V and 5.25. A bypass capacitor of 0.1µF should be used between V+ to ground as close to the pin as possible. SHDN, SDA, SDB: Active Low op amp shutdown, threshold is 0.75V above the negative supply, V–. If left unconnected, the amplifier is enabled. OUT: Amplifier Output. NC: Not connected. May be used to create a guard ring around the input to guard against board leakage currents. See Applications Information section for more details. SIMPLIFIED SCHEMATIC V+ C0 I0 ESD_D2 COMPLEMENTARY INPUT STAGE Q1 INPUT REPLICA +IN Q9 D4 Q4 CASCODE STAGE Q3 ESD_D0 CMOS INPUT BUFFER –IN Q5 Q6 BUFFER OUT ESD_D1 Q7 D6 Q8 INPUT REPLICA Q2 D5 ESD_D3 SD REFERENCE GENERATION D7 V– 6268 BD LTC6268 Simplified Schematic Diagram 62689f For more information www.linear.com/LTC6268 11 LTC6268/LTC6269 OPERATION The LTC6268 input signal range is specified from the negative supply to 0.5V below the positive power supply, while the output can swing from rail-to-rail. The schematic above depicts a simplified schematic of the amplifier. The input pins drive a CMOS buffer stage. The CMOS buffer stage creates replicas of the input voltages to boot strap the protection diodes. In turn, the buffer stage drives a complementary input stage consisting of two differential amplifiers, active over different ranges of input common mode voltage. The main differential amplifier is active with input common mode voltages from the negative power supply to approximately 1.55V below the positive supply, with the second amplifier active over the remaining range to 0.5V below the positive supply rail. The buffer and output bias stage uses a special compensation technique ensuring stability of the op amp. The common emitter topology of output transistors Q1/Q2 enables the output to swing from rail-to-rail. APPLICATIONS INFORMATION Noise To minimize the LTC6268’s noise over a broad range of applications, careful consideration has been placed on input referred voltage noise (eN), input referred current noise (iN) and input capacitance CIN. CF RF IN – CIN OUT 6268 F01 + GND Figure 1. Simplified TIA Schematic For a trans-impedance amplifier (TIA) application such as shown in Figure 1, all three of these op amp parameters, plus the value of feedback resistance RF, contribute to noise behavior in different ways, and external components and traces will add to CIN. It is important to understand the impact of each parameter independently. Input referred voltage noise (eN) consists of flicker noise (or 1/f noise), which dominates at lower frequencies, and thermal noise which dominates at higher frequencies. For LTC6268, the 1/f corner, or transition between 1/f and thermal noise, is at 80kHz. The iN and RF contributions to input referred noise current at the minus input are relatively straight forward, while the eN contribution is amplified by the noise gain. Because there is no gain resistor, the noise gain is calculated using feedback resistor(RF) in conjunction with impedance of CIN as (1 + 2π RF • CIN • Freq), which increases with frequency. All of the contributions will be limited by the closed loop bandwidth. The equivalent input current noise is shown in Figures 2-5, where eN represents contribution from input referred voltage noise (eN), iN represents contribution from input referred current noise (iN), and RF represents contribution from feedback resistor (RF). TIA gain (RF) and capacitance at input (CIN) are also shown on each figure. Comparing Figures 2 & 3, and 4 & 5 for higher frequencies, eN dominates when CIN is high (5pF) due to the amplification mentioned above while iN dominates when CIN is low (1pF). At lower frequencies, the 62689f 12 For more information www.linear.com/LTC6268 LTC6268/LTC6269 APPLICATIONS INFORMATION 5 eN iN RF TOTAL 4 NOISE DENSITY (pA/√Hz) NOISE DENSITY (pA/√Hz) 5 RF = 10k CIN = 1pF CF = 0.28pF 3 2 1 0 0 20 40 60 FREQUENCY (MHz) 80 4 eN iN RF TOTAL 3 2 1 0 100 RF = 100k CIN = 1pF CF = 0.08pF 0 20 40 60 FREQUENCY (Hz) 80 6268 F02 6268 F04 Figure 2 Figure 4 eN iN RF TOTAL RF = 10k CIN = 5pF CF = 0.56pF 4 3 2 1 0 0 20 40 60 FREQUENCY (MHz) 80 5 NOISE DENSITY (pA/√Hz) NOISE DENSITY (pA/√Hz) 5 4 eN iN RF TOTAL 3 2 1 0 100 RF = 100k CIN = 5pF CF = 0.18pF 0 20 40 60 FREQUENCY (MHz) 6268 F03 100 Figure 5 RF contribution dominates for 10k and 100k. Since wide band eN is 4.3nV/√Hz (see typical performance characteritics), RF contribution will become a lesser factor at lower frequencies if RF is less than 1.16kΩ as indicated by the following equation: eN / RF ≥1 4kT / RF 80 6268 F05 Figure 3 100 Optimizing the Bandwidth for TIA Application The capacitance at the inverting input node can cause amplifier stability problems if left unchecked. When the feedback around the op amp is resistive (RF), a pole will be created with RF ||CIN. This pole can create excessive phase shift and possibly oscillation. Referring to Figure 1, the response at the output is: RF 2 1+ 2ζs + S ω ω2 62689f For more information www.linear.com/LTC6268 13 LTC6268/LTC6269 APPLICATIONS INFORMATION Where RF is the DC gain of the TIA, ω is the natural frequency of the closed loop, which can be expressed as: ω= 2πGBW RF (CIN +CF ) ζ is the damping factor of the loop, which can be expressed as 1⎛ 1 ζ= ⎜ 2 ⎝ 2πGBW •RF (CIN +CF ) ⎛ C +C ⎞ 2πGBW ⎞ + RF ⎜ CF + IN F ⎟ + ⎟ 1+ A O ⎠ RF (CIN +CF ) ⎠ ⎝ Where CIN is the total capacitance at the inverting input node of the op amp, and GBW is the gain bandwidth of the op amp. There are two regions that the system will be stable regardless of CF. The first region is when RF is less than 1/(4π∙CIN∙GBW). In this region, the pole produced by the feedback resistor and CIN is at a high frequency which does not cause stability problems. The second region is where: A O2 RF > πGBW •CIN Table 1. Min CF RF 10kΩ 100kΩ CIN = 1pF 0.25pF 0.08pF Achieving Higher Bandwidth with Higher Gain TIAs Good layout practices are essential to achieving best results from a TIA circuit. The following two examples show drastically different results from an LTC6268 in a 499kΩ TIA. (See Figure 6.) The first example is with an 0603 resistor in a basic circuit layout. In a simple layout, without expending a lot of effort to reduce feedback capacitance, the bandwidth achieved is about 2.5MHz. In this case, the bandwidth of the TIA is limited not by the GBW of the LTC6268, but rather by the fact that the feedback capacitance is reducing the actual feedback impedance (the TIA gain itself) of the TIA. Basically, it’s a resistor bandwidth limitation. The impedance of the 499kΩ is being reduced by its own parasitic capacitance at high frequency. From the 2.5MHz bandwidth and the 499kΩ low frequency gain, we can estimate the total feedback capacitance as C = 1/(2π • 2.5MHz • 499kΩ) = 0.13pF. That’s fairly low, but it can be reduced further. PARASITIC FEEDBACK C Where AO is the DC open loop gain of the op amp, and the pole formed by RF CIN is the dominant pole. For RF between these two regions, the small capacitor CF in parallel with RF can introduce enough damping to stabilize the loop. By assuming CIN >> CF, the following condition needs to be met for CF, CF > CIN = 5pF 0.56pF 0.18pF 499k IPD – K PD CASE A VOUT LTC6268 + –2.5 CIN π •GBW •RF +2.5 –2.5 6268 F06 PD: OSI FCI-125G-006 Figure 6. LTC6268 and Low Capacitance Photodiode in a 499kΩ TIA The above condition implies that higher GBW will require lower feedback capacitance CF, which will have higher loop bandwidth. Table 1 shows the optimal CF for RF of 10kΩ and 100kΩ and CIN of 1pF and 5pF. 62689f 14 For more information www.linear.com/LTC6268 LTC6268/LTC6269 APPLICATIONS INFORMATION Such a ground trace shields the output field from getting to the summing node end of the resistor and effectively shunts the field to ground instead. Keeping the trace close to the output end increases the output load capacitance very slightly. See Figure 8 for a pictorial representation. Figure 9 shows the dramatic increase in bandwidth simply by careful attention to low capacitance methods around the feedback resistance. Bandwidth was raised from 2.5MHz to 11.2MHz, a factor greater than 4. Methods implemented were two: Figure 7. Frequency Response of 499kΩ TIA without Extra Effort to Reduce Feedback Capacitance is 2.5MHz With some extra layout techniques to reduce feedback capacitance, the bandwidth can be increased. Note that we are increasing the effective “bandwidth” of the 499kΩ resistance. One of the main ways to reduce capacitance is to increase the distance between the plates, in this case the plates being the two endcaps of the component resistor. For that reason, it will serve our purposes to go to a longer resistor. An 0805 is longer than an 0603, but its endcaps are also larger in area, increasing capacitance again. However, increasing distance between the endcaps is not the only way to decrease capacitance, and the extra distance between the resistor endcaps also allows the easy application of another technique to reduce feedback capacitance. A very powerful method to reduce plate to plate capacitance is to shield the E field paths that give rise to the capacitance. In this particular case, the method is to place a short ground trace between the resistor pads, near the TIA output end. CERAMIC R SUBSTRATE E RESISTIVE ELEMENT ENDCAP IPD K G A –2.5 2)Shield the feedback capacitance using a ground trace under the feedback resistor near the output side. Figure 9. LTC6268 in a 499kΩ TIA with extra Layout Effort to Reduce Feedback Capacitance Achieves 11.2MHz BW CERAMIC R SUBSTRATE FR4 K LTC6268 VOUT E RESISTIVE ELEMENT ENDCAP IPD – + 1)Minimal pad sizing. Check with your board assembler for minimum acceptable pad sizing, or assemble this resistor using other means, and G A E FIELD ⇒ C – FR4 LTC6268 + –2.5 EXTRA GND TRACE UNDER RESISTOR VOUT TAKE E FIELD TO GND, MUCH LOWER C 6268 F08 Figure 8. A Normal Layout at Left and a Field-Shunting Layout at Right. Simply Adding a Ground Trace Under the Feedback Resistor Does Much to Shunt Field Away from the Feedback Side and Dumps It to Ground. Note That the Dielectric Constant of Fr4 and Ceramic Is Typically 4, so Most of the Capacitance Is in the Solids and Not Through the Air. (Reduced Pad Size On Right Is Not Shown.) 62689f For more information www.linear.com/LTC6268 15 LTC6268/LTC6269 APPLICATIONS INFORMATION High Impedance Buffer domain reflections of the ADC glitches. The 2.048V reference establishes a midpoint input “zero” reference voltage. The LT1395 high speed current feedback amplifier and its associated resistor network attenuate the buffered signal and render it differential by forcing the common mode to virtual ground (the VCM voltage provided by the ADC). The very high input impedance of the LTC6268 makes it ideal for buffering high impedance or capacitive sources. The circuit of Figure 10 shows the LTC6268 applied as a buffer, after a simple RC filter. The RLC network after the buffer acts as an absorptive filter to avoid excessive time R9 200Ω VIN R2 75Ω VIN = 2.048V ±1.7V FS R1 49.9Ω C1 22pF R3 10M +V + U1 – + CIN 0.1µF VIN VOUT_s GND L2 100nH R10 75Ω R16 49.9Ω R11 75Ω R17 49.9Ω R4 C2 10pF 49.9Ω R5 49.9Ω R7 VREF 100Ω VOUT_F SHDN L1 100nH – LTC6268 LTC6655-2.048 +V R6 100Ω C4 0.1µF C3 L4 10pF 100nH L3 100nH C4 100µF R12 825Ω R8 200Ω R14 R13 825Ω 402Ω +V – + U2 R18 49.9Ω +V = 5V –V = –5V C5 .01µF 1.8V VDD AIN+ + R15 402Ω – LT1395 –V 1.8V OVDD LTC2269 16-BIT ADC CORE S/H D15 • • OUTPUT DRIVERS • AIN– D0 CLOCK CONTROL 10MHz CLOCK VCM GND OGND LTC2269 16-BIT 20 Msps ADC 6268 F10 Figure 10. LTC6268 as a High-Z Buffer Driving an LT1395 as a Single-Ended to Differential Converter Into a 16-Bit ADC 62689f 16 For more information www.linear.com/LTC6268 LTC6268/LTC6269 ADC OUTPUTS (COUNTS) APPLICATIONS INFORMATION 64k fS = 10Msps 60k fIN = 10.101MHz 56k 52k 48k 44k 40k 36k 32k 28k 24k 20k 16k 12k 8k 4k 0 440 460 480 500 520 540 560 580 TIME (10ns/DIV) GUARD RING HIGH-Z SENSOR (RIN) RF§ VBIAS –IN LEAKAGE CURRENT Maintaining Ultralow Input Bias Current Leakage currents into high impedance signal nodes can easily degrade measurement accuracy of fA signals. High temperature applications are especially susceptible to these issues. For humid environments, surface coating may be necessary to provide a moisture barrier. There are several factors to consider in a low input bias current circuit. At the femtoamp level, leakage sources can come from unexpected sources including adjacent signals on the PCB, both on the same layer and from internal layers, any form of contamination on the board from the assembly process or the environment, other components on the signal path and even the plastic of the device package. Care taken in the design of the system can mitigate these sources and achieve excellent performance. V+ OUT +IN NC V– NO SOLDER MASK OVER GUARD RING LOW IMPEDANCE ‡ NO LEAKAGE CURRENT. V–IN = VGRD NODE ABSORBS § AVOID DISSIPATING SIGNIFICANT AMOUNTS OF POWER IN THIS RESISTOR. LEAKAGE CURRENT IT WILL GENERATE THERMAL GRADIENTS WITH RESPECT TO THE INPUT PINS AND LEAD TO THERMOCOUPLE-INDUCED ERROR. (a) GUARD RING VBIAS RF HIGH-Z SENSOR VIN –+ V+ RIN – LEAKAGE CURRENT Figure 11 shows the time domain response of a 10.101MHz 3VP-P input square wave, sampled at 10Msps, just 1ns slower than the waveform rate. At this rate, the waveform appears reconstructed at a rate of 1ns per sample, allowing for a more immediate view of the settling characteristics, even though each sample is really 100ns later. LTC6268 S8 ‡ V–IN 6268 F11 Figure 11. Sampled Time Domain Response of the Circuit of Figure 10 SD NC LTC6268 VOUT + V– LEAKAGE CURRENT IS ABSORBED BY GROUND INSTEAD OF CAUSING A MEASUREMENT ERROR. 6268 F12 (b) Figure 12. Example Layout of Inverting Amplifier (or Trans-Impedance) with Leakage Guard Ring The choice of device package should be considered because although each has the same die internally, the pin spacing and adjacent signals influence the input bias current. The LTC6268/LTC6269 is available in SOIC, MSOP, DFN and SOT-23 packages. Of these, the SOIC has been designed as the best choice for low input bias current. It has the largest lead spacing which increases the impedance of the package plastic and the pinout is such that the two input pins are isolated on the far side of the package from the other signals. The gull-wing leads on this package also allow for better cleaning of the PCB and reduced contamination-induced leakage. The other packages have advantages in size and pin count but do so by reducing the input isolation. Leadless packages such as the DFN offer the minimum size but have the smallest pin spacing and may trap contaminants under the package. 62689f For more information www.linear.com/LTC6268 17 LTC6268/LTC6269 APPLICATIONS INFORMATION The material used in the construction of the PCB can sometimes influence the leakage characteristics of the design. Exotic materials such as Teflon can be used to improve leakage performance in specific cases but they are generally not necessary if some basic rules are applied in the design of conventional FR4 PCBs. It is important to keep the high impedance signal path as short as possible on the board. A node with high impedance is susceptible to picking up any stray signals in the system so keeping it as short as possible reduces this effect. In some cases, it may be necessary to have a metallic shield over this portion of the circuit. However, metallic shielding increases capacitance. Another technique for avoiding leakage paths is to cut slots in the PCB. High impedance circuits are also susceptible to electrostatic as well as electromagnetic effects. The static charge carried by a person walking by the circuit can induce an interference on the order of 100’s of femtoamps. A metallic shield can reduce this effect as well. The layout of a high impedance input node is very important. Other signals should be routed well away from this signal path and there should be no internal power planes under it. The best defense from coupling signals is distance and this includes vertically as well as on the surface. In cases where the space is limited, slotting the board around the high impedance input nodes can provide additional isolation and reduce the effect of contamination. In electrically noisy environments the use of driven guard rings around these nodes can be effective (see Figure 12). Adding any additional components such as filters to the high impedance input node can increase leakage. The leakage current of a ceramic capacitor is orders of magnitude larger than the bias current of this device. Any filtering will need to be done after this first stage in the signal chain. Low Input Offset Voltage The LTC6268 has a maximum offset voltage of ±2.5mV (PNP region) over temperature. The low offset voltage is essential for precision applications. There are 2 different input stages that are used depending on the input common mode voltage. To increase the versatility of the LTC6268, the offset voltages are trimmed for both regions of operation. Rail-to-Rail Output The LTC6268 has a rail-to-rail output stage that has excellent output drive capability. It is capable of delivering over ±40mA of output drive current over temperature. Furthermore, the output can reach within 200mV of either rail while driving ±10mA. Attention must be paid to keep the junction temperature of the IC below 150°C. Input Protection To prevent breakdown of internal devices in the input stage, the two op amp inputs should NOT be separated by more than 2.0V. To help protect the input stage, internal circuitry will engage automatically if the inputs are separated by >2.0V and input currents will begin to flow. In all cases, care should be taken so that these currents remain less than 1mA. Additionally, if only one input is driven, internal circuitry will prevent any breakdown condition under transient conditions. The worst-case differential input voltage usually occurs when the +input is driven and the output is accidentally shorted to ground while in a unity gain configuration. 62689f 18 For more information www.linear.com/LTC6268 LTC6268/LTC6269 APPLICATIONS INFORMATION ESD ESD Protection devices can be seen in the simplified schematic. The +IN and –IN pins use a sophisticated method of ESD protection that incorporates a total of 4 reversebiased diodes connected as 2 series diodes to each rail. To maintain extremely low input bias currents, the center node of each of these series diode chains is driven by a buffered copy of the input voltage. This maintains the two diodes connected directly to the input pins at low reverse bias, minimizing leakage current of these ESD diodes to the input pins. The remaining pins have traditional ESD protection, using reverse-biased ESD diodes connected to each power supply rail. Care should be taken to make sure that the voltages on these pins do not exceed the supply voltages by more than 100mV or these diodes will begin to conduct large amounts of current. Shutdown The LTC6268S6, LTC6268S8, and LTC6269DD have SHDN pins that can shut down the amplifier to less than 1.2mA supply current per amplifier. The SHDN pin voltage needs to be within 0.75V of V– for the amplifier to shut down. During shutdown, the output will be in a high output resistance state, so the LTC6268 is suitable for multiplexer applications. The internal circuitry is kept in a low current active state for fast recovery. When left floating, the SHDN pin is internally pulled up to the positive supply and the amplifier is enabled. 62689f For more information www.linear.com/LTC6268 19 LTC6268/LTC6269 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 0.62 MAX 2.90 BSC (NOTE 4) 0.95 REF 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 – 0.45 6 PLCS (NOTE 3) 0.95 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 1.90 BSC S6 TSOT-23 0302 62689f 20 For more information www.linear.com/LTC6268 LTC6268/LTC6269 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610 Rev G) .189 – .197 (4.801 – 5.004) NOTE 3 .045 ±.005 .050 BSC 8 .245 MIN .160 ±.005 .010 – .020 × 45° (0.254 – 0.508) 2 .053 – .069 (1.346 – 1.752) 0°– 8° TYP .016 – .050 (0.406 – 1.270) 5 .150 – .157 (3.810 – 3.988) NOTE 3 1 RECOMMENDED SOLDER PAD LAYOUT .008 – .010 (0.203 – 0.254) 6 .228 – .244 (5.791 – 6.197) .030 ±.005 TYP NOTE: 1. DIMENSIONS IN 7 .014 – .019 (0.355 – 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE 3 4 .004 – .010 (0.101 – 0.254) .050 (1.270) BSC SO8 REV G 0212 62689f For more information www.linear.com/LTC6268 21 LTC6268/LTC6269 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS8E Package 8-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1662 Rev K) BOTTOM VIEW OF EXPOSED PAD OPTION 1.88 (.074) 1 1.88 ±0.102 (.074 ±.004) 0.29 REF 1.68 (.066) 0.889 ±0.127 (.035 ±.005) 0.05 REF 5.10 (.201) MIN DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 1.68 ±0.102 3.20 – 3.45 (.066 ±.004) (.126 – .136) 8 3.00 ±0.102 (.118 ±.004) (NOTE 3) 0.65 (.0256) BSC 0.42 ±0.038 (.0165 ±.0015) TYP 8 7 6 5 0.52 (.0205) REF RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) DETAIL “A” 0° – 6° TYP GAUGE PLANE 0.53 ±0.152 (.021 ±.006) DETAIL “A” 1 2 3 4 1.10 (.043) MAX 0.86 (.034) REF 0.18 (.007) SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP 0.65 (.0256) BSC 0.1016 ±0.0508 (.004 ±.002) MSOP (MS8E) 0213 REV K NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 62689f 22 For more information www.linear.com/LTC6268 LTC6268/LTC6269 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 ±0.05 3.55 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ±0.10 (4 SIDES) R = 0.125 TYP 6 0.40 ±0.10 10 1.65 ±0.10 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 5 0.75 ±0.05 0.00 – 0.05 1 (DD) DFN REV C 0310 0.25 ±0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 62689f For more information www.linear.com/LTC6268 23 LTC6268/LTC6269 TYPICAL APPLICATION LTC6268 as a High-Z Buffer Driving an LT1395 as a Single-Ended to Differential Converter Into a 16-Bit ADC R9 200Ω VIN R2 75Ω R1 49.9Ω VIN VOUT_s GND AIN+ R7 VREF 100Ω C4 0.1µF L3 100nH C4 100µF C3 L4 10pF 100nH 16-BIT ADC CORE D15 AIN– R11 75Ω R17 49.9Ω R12 825Ω R8 200Ω LTC2269 S/H R5 49.9Ω VOUT_F SHDN R16 49.9Ω R10 75Ω R14 R13 825Ω 402Ω +V – + U2 R18 49.9Ω +V = 5V –V = –5V C5 .01µF + OUTPUT DRIVERS • CIN 0.1µF L2 100nH R4 C2 10pF 49.9Ω – LTC6268 LTC6655-2.048 +V L1 100nH • VIN = 2.048V ±1.7V FS R6 100Ω 1.8V OVDD • C1 22pF R3 10M +V + U1 – + 1.8V VDD D0 CLOCK CONTROL 10MHz CLOCK R15 402Ω VCM GND OGND LTC2269 16-BIT 20 Msps ADC – LT1395 –V 6268 TA03 ADC OUTPUTS (COUNTS) Reconstructed Sampled Time Domain Response of Above Circuit 64k fS = 10Msps 60k fIN = 10.101MHz 56k 52k 48k 44k 40k 36k 32k 28k 24k 20k 16k 12k 8k 4k 0 440 460 480 500 520 540 560 580 TIME (10ns/DIV) 6268 F11 RELATED PARTS PART NUMBER Op Amps LTC6244 LTC6240/LTC6241/ LTC6242 LTC6252/LTC6253/ LTC6254 LTC6246/LTC6247/ LTC6248 LT1818 LT6230 LT6411 SAR ADC LTC2376-18/ LTC2377-18/ LTC2378-18/ LTC2379-18 DESCRIPTION COMMENTS Dual 50MHz, Low Noise, Rail-to-Rail, CMOS Op Amp 18MHz, Low Noise, Rail-to-Rail Output, CMOS Op Amp Unity Gain Stable, 1pA Input Bias Current, 100μV Max Offset. 18MHz GBW, 0.2pA Input Current, 125μV Max Offset. 720MHz, 3.5mA Power Efficient Rail-to-Rail I/O Op Amp 720MHz GBW, Unity Gain Stable, Low Noise 180MHz, 1mA Power Efficient Rail-to-Rail I/O Op Amps 180MHz GBW, Unity Gain Stable, Low Noise 400MHz, 2500V/µs, 9mA Single Operational Amplifier Unity Gain Stable, 6nV/√Hz Unity Gain Stable 215MHz, Rail-to-Rail Output, 1.1nV/√Hz, 3.5mA Op Amp Family 350μV Max Offset Voltage, 3V to 12.6V Supply 650MHz Differential ADC Driver/Dual Selectable Amplifier SR 3300V/µs, 6ns 0.1% Settling. 18-Bit, 250ksps to 1.6Msps, Low Power SAR ADC, 102dB SNR 18mW at 1.6Msps, 3.4μW at 250sps, –126dB THD. 62689f 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC6268 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC6268 LT 0914 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2014