LT3952 - 60V LED Driver with 4A Switch Current

LT3952
60V LED Driver with
4A Switch Current
FEATURES
DESCRIPTION
4000:1 True Color PWM™ Dimming
4A, 60V Internal DMOS Switch
nn Wide Input Voltage Range: 3V to 42V
nn 0V to 60V Output Current Regulation with Monitor
nn PMOS Switch Driver for PWM and Output Disconnect
nn LED Short-Circuit Protection and SHORTLED Flag
nn Internal Spread Spectrum Frequency Modulation
nn Constant-Current and Constant-Voltage Regulation
nn Input Current Limit and Monitor
nn Adjustable Frequency: 200kHz to 3MHz,
Synchronizable to an External Clock
nn 10:1 Analog Dimming
nn Programmable Open-LED Protection with
OPENLED Flag
nn Programmable V Undervoltage and
IN
Overvoltage Lockout
nn Available in a 28-Lead TSSOP Package
The LT®3952 is a current mode step-up DC/DC converter
with an internal, 60V, 80mΩ DMOS power switch. The
LT3952 is specifically designed to drive high power LEDs
in multiple configurations. It combines input and output
current regulation loops with output voltage regulation to
operate as a flexible current/voltage source.
nn
nn
Programmable switching frequency with optional spreadspectrum modulation provides EMI reduction, while still
allowing optimization of the external components for
efficiency or component size. The LED current is programmable with an external sense resistor, and can be adjusted
from zero to full scale with a voltage at the CTRL pin. The
external PWM input provides LED ON/OFF control and
4000:1 dimming ratio, and an internal PWM generator
delivers the efficiency of PWM dimming to standalone
or I/O limited applications. The LT3952 is available in the
thermally enhanced 28-lead TSSOP package.
APPLICATIONS
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
True Color PWM is a trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents including, 7199560,
7321203, 7746300. Patents pending
Display Backlighting
Automotive and Avionic Lighting
nn Accurate Current-Limited Voltage Regulators
nn
nn
TYPICAL APPLICATION
Short-Circuit Robust Boost LED Driver with Spread Spectrum Frequency Modulation
4A INPUT LIMIT
10µH
15mΩ
VIN
7V TO 42V
4.7µF
EN/UVLO
IVINN
VIN IVINP
Efficiency vs Input Voltage
2.2µF
100V
×2
SW
100
GND
1M
FB
21.5k
INTVCC
CTRL
VREF
PWM
ISMON
DIM
PWM
ISMON
100k
LT3952
750mΩ
OPENLED
SHORTLED
VC
3.6k
8.2nF
ISP
TG
INTVCC
IVINCOMP
1µF
90.9k
1MHz
100nF
80
SSFM OFF
SSFM ON
INTVCC
SYNC/SPRD
SS
RT
90
70
ISN
100k
OPENLED
SHORTLED
57V OPEN LED
REGULATION
EFFICIENCY (%)
OVLO
2.2µF
60
16 LED (50V)
333mA
3952 TA01a
For more information www.linear.com/LT3952
0
10
20
30
VIN (V)
40
50
3952 TA01b
3952fa
1
LT3952
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN, IVINP, IVINN, SHORTLED, OPENLED,
EN/UVLO ...................................................................42V
OVLO.........................................................................12V
SW, ISP, ISN, TG........................................................60V
IVINP-IVINN......................................................–1V to 3V
CTRL, FB, DIM, SYNC/SPRD, PWM.......... INTVCC + 0.3V
VC, SS, ISMON, IVINCOMP..........................................3V
RT, VREF ......................................................................2V
INTVCC (Note 4)........................................................3.6V
Operating Junction Temperature Range (Notes 2, 3)
LT3952E/LT3952I............................... –40°C to 125°C
LT3952H............................................. –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
PIN CONFIGURATION
TOP VIEW
GND
1
28 GND
SW
2
27 ISP
SW
3
26 ISN
SW
4
25 TG
IVINN
5
24 ISMON
IVINP
6
23 IVINCOMP
VIN
7
EN/UVLO
8
OVLO
9
INTVCC 10
29
GND
22 OPENLED
21 SHORTLED
20 PWM
19 SS
SYNC/SPRD 11
18 VREF
GND 12
17 CTRL
VC 13
16 FB
RT 14
15 DIM
FE PACKAGE
28-LEAD PLASTIC TSSOP
θJA = 30°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3952EFE#PBF
LT3952EFE#TRPBF
LT3952FE
28-Lead Plastic TSSOP
–40°C to 125°C
LT3952IFE#PBF
LT3952IFE#TRPBF
LT3952FE
28-Lead Plastic TSSOP
–40°C to 125°C
LT3952HFE#PBF
LT3952HFE#TRPBF
LT3952FE
28-Lead Plastic TSSOP
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix
2
3952fa
For more information www.linear.com/LT3952
LT3952
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VIN = IVINP = IVINN = 12V, ISP = ISN = 24V, EN/UVLO = PWM = 3V, CTRL = 2V, OVLO = 0V unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
MAX
1.5
0
35
2.2
1
60
3.00
3.10
Minimum Operating Voltage
Supply Current
3
FB = 1.3V, RT = 40.2k, CTRL = 0V
EN/UVLO = 0V, CTRL = 0V
EN/UVLO = 1.15V, CTRL = 0V
UNITS
V
mA
µA
µA
Internal Regulator
INTVCC Output Voltage
CTRL = 0V
INTVCC Dropout Voltage
VIN = 3V, CTRL = 0V
INTVCC Undervoltage Lockout
INTVCC Rising, CTRL = 0V
INTVCC UVLO Hysteresis
CTRL = 0V
2.90
150
2.62
2.68
V
mV
2.74
200
V
mV
Reference Voltage Output
VREF Voltage
IVREF = –100μA , CTRL = 0V
VREF Line Regulation
3V < VIN < 42V , CTRL = 0V
0.01
%/V
VREF Load Regulation
0µA < IVREF < –100µA , CTRL = 0V
0.6
%
l
1.955
2.000
2.045
V
Current Feedback
CTRL Range for Current Sense Threshold Adjustment
CTRL PWM Shutdown Threshold
0.2
CTRL Falling
100
1.2
V
125
mV
CTRL PWM Threshold Hysteresis
12.5
mV
CTRL Zero-Scale Offset
200
mV
CTRL Input Bias Current
CTRL = 0V, Current Out of Pin
Current Sense Common Mode Input Range
CTRL = 1.5V
Full-Scale Current Sense Accuracy (VISP-VISN)
ISP = 60V, CTRL = 1.5V
20
0
l
100
nA
60
V
mV
245
250
255
Midrange Current Sense Accuracy (VISP-VISN)
ISP = 60V, CTRL = 0.7V
115
125
135
mV
1/10th Scale Current Sense Accuracy (VISP-VISN)
ISP = 60V, CTRL = 0.3V
10
25
40
mV
Low Side Current Sense Accuracy (VISP-VISN)
ISP = 0V, CTRL = 1.5V
l
240
250
260
mV
l
350
375
390
mV
Overcurrent Sense Threshold
ISP to VC Transconductance
CTRL = 1.5V
275
ISP/ISN Input Bias Current
PWM = 5V (Active), ISP = 60V
PWM = 0V (Standby), ISP = 60V
250
0
Current Sense Monitor Ratio (VISMON)/(VISP-VISN)
CTRL = 0.4V, 0.8V
Current Sense Monitor Accuracy (VISMON)
CTRL = 1.5V , ISP = 60V
µS
0.1
4
0.950
µA
µA
V/V
1.000
1.050
V
35
60
µA
60
65
mV
Input Current Sense Amplifier
Amplifier Supply Current (From IVINP)
IVINP = IVINN = 42V
IVIN Regulation Threshold (VIVINP-IVINN)
l
IVINCOMP to VC Transconductance
55
1650
Input Common Mode Minimum Voltage
IVINP/IVINN to Monitor Voltage Gain
µS
3
VIVINP-IVINN = 30mV
20
V
V/V
3952fa
For more information www.linear.com/LT3952
3
LT3952
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VIN = IVINP = IVINN = 12V, ISP = ISN = 24V, EN/UVLO = PWM = 3V, CTRL = 2V, OVLO = 0V unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
MAX
1.15
1.2
1.25
UNITS
TG Gate Driver
PWM Input High Threshold
PWM Rising
l
PWM Hysteresis
20
V
mV
TG On Voltage
VISP-TG, VISP > 10V
7.5
9.5
0
0.3
V
TG Off Voltage
VISP-TG, PWM = 0V
TG Turn-On Time
CLOAD = 470pF, PWM Rising
100
ns
TG Turn-Off Time
CLOAD = 470pF, PWM Falling
150
ns
V
Output Voltage Feedback
FB Voltage Regulation Threshold (VFB)
CTRL = 1.5V
l
FB Open-LED Threshold
FB Rising
1.188
1.182
1.200
1.200
1.212
1.218
V
V
VFB –
65mV
VFB –
45mV
VFB –
25mV
V
FB Open-LED Threshold Hysteresis
FB Overvoltage Threshold
15
VFB +
15mV
FB Rising
FB Overvoltage Threshold Hysteresis
VFB +
40mV
15
FB Pin Bias Current
Feedback Line Regulation
VFB +
30mV
mV
20
l
3V < VIN < 42V
V
mV
100
0.0003
nA
%/V
FB to VC Transconductance
450
µS
VC Output Impedance
5000
kΩ
Soft-Start
Soft-Start Sourcing Current
Current Out of Pin, SS = 0.1V
18
25
37
µA
Soft-Start Sinking Current
SS = 1.8V
1.5
2.5
4.1
µA
Soft-Start Hiccup Retry Threshold
200
mV
Soft-Start Strong Pull-Down On-Resistance
120
Ω
Oscillator
RT Voltage
Switching Frequency
Maximum Duty Cycle
1.20
RT = 470k
RT = 90.9k
RT = 40.2k
RT = 25.5k
RT = 470k
SYNC = 300kHz Clock Signal, RT = 470k
RT = 90.9k
RT = 40.2k
RT = 25.5k
l
l
215
1.0
2.0
3.0
98
97
92
85
99
98
95
90
80
%
%
%
%
%
50
ns
Minimum Off-Time
Minimum On-Time
SYNC/SPRD Pin Resistance to GND
VSYNC = 2V
SYNC/SPRD Input High Threshold
V
180
0.95
1.90
2.75
250
1.05
2.10
3.25
kHz
MHz
MHz
MHz
75
ns
100
kΩ
1.5
V
SYNC/SPRD Input Low Threshold
0.4
V
Spread Spectrum Minimum Step as Percentage of fSW
1
%
Spread Spectrum Maximum Step as Percentage of
fSW
31
%
4
3952fa
For more information www.linear.com/LT3952
LT3952
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VIN = IVINP = IVINN = 12V, ISP = ISN = 24V, EN/UVLO = PWM = 3V, CTRL = 2V, OVLO = 0V unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
MAX
5
10
15
UNITS
PWM Generator
PWM Pin Pull-Up/Pull-Down Current
PWM = 1.2V, DIM = 0.7V
PWM Generator Lower Threshold Offset
0.2V < DIM < 1.2V
PWM Generator Upper Threshold Offset
0.2V < DIM < 1.2V
PWM Generator Frequency
DIM = 0.7V, CPWM = 22nF
DIM Pin Output Current
DIM = 0.7V
TG Duty Cycle Using PWM Generator
DIM = 0.345V
DIM = 0.535V
DIM = 0.725V
DIM = 1.105V
l
VDIM – 15 VDIM + 0 VDIM + 15
VDIM +
825
VDIM +
950
VDIM +
1075
230
l
µA
mV
mV
Hz
10
20
30
µA
1
21
42.5
86
10
30
50
90
21
39
57.5
94
%
%
%
%
Power Switch
Switch On-Resistance
ISW = 500mA
Switch Leakage Current
SW = 60V, CTRL = 0V
80
2
VC to Current Threshold Transconductance
Maximum Power Switch Current Limit
mΩ
7.5
VC = 2V
µA
S
4
4.5
5
A
1.191
1.230
1.269
V
Logic Inputs/Outputs
EN/UVLO Disable Threshold
EN/UVLO Falling
l
EN/UVLO Threshold Internal Hysteresis
75
EN/UVLO Hysteresis Current
EN/UVLO = 1.25V, Device in Shutdown
EN/UVLO = 1.5V, Device in Operation
OVLO Threshold
OVLO Rising
l
OVLO Threshold Hysteresis
1.191
mV
2
0
0.4
µA
µA
1.230
1.269
V
25
mV
OVLO Input Bias Current
OVLO = 1V
15
SHORTLED On-Resistance
ISHORTLED = 1mA
60
SHORTLED Output Low Voltage
ISHORTLED = 2mA
SHORTLED Off-State Leakage
SHORTLED = 42V
OPENLED On-Resistance
IOPENLED = 1mA
OPENLED Output Low Voltage
IOPENLED = 2mA
0.3
V
OPENLED Off-State Leakage
OPENLED = 42V
1
µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3952E is guaranteed to meet specified performance from
0°C to 125°C. Specifications over the –40°C to 125°C operating junction
temperature range are assured by design, characterization and correlation
with statistical process controls. The LT3952I is guaranteed to meet
performance specifications over the –40°C to 125°C operating junction
temperature range. The LT3952H is guaranteed to meet performance
specifications over the full –40°C to 150°C operating junction temperature
range. High junction temperatures degrade operating lifetimes. Operating
lifetime is derated at junction temperatures greater than 125°C.
100
nA
Ω
0.3
V
1
µA
60
Ω
Note 3: The LT3952 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when overtemperature is active. Continuous operating above the specified
maximum operating junction temperature may impair device reliability.
Note 4: INTVCC is an output and is not meant to be externally driven.
3952fa
For more information www.linear.com/LT3952
5
LT3952
TYPICAL PERFORMANCE CHARACTERISTICS
EN/UVLO Thresholds vs
Temperature
Shutdown Current vs Temperature
60
EN/UVLO Hysteresis Current
vs Temperature
2.25
1.40
VEN = 1.15V
50
1.35
40
1.30
30
20
1.25
CURRENT (µA)
THRESHOLD (V)
SUPPLY CURRENT (µA)
2.00
EN/UVLO FALLING
1.20
1.75
1.50
10
1.15
0
–50
0
50
100
TEMPERATURE (°C)
1.10
–50
150
0
50
100
TEMPERATURE (°C)
3952 G01
0
50
100
TEMPERATURE (°C)
3.05
2
0.80
INTVCC Voltage vs Temperature
1.75
0.40
0.20
0.00
–0.20
–0.40
–0.60
1.5
3.00
1.25
INTVCC (V)
QUIESCENT CURRENT (mA)
0.60
1
0.75
2.95
0.5
0.25
–0.80
2
12
22
32
EN/UVLO VOLTAGE (V)
0
42
0
20
10
2.90
–50
40
30
0
VIN (V)
3925 G04
100
50
TEMPERATURE (°C)
3952 G05
3.50
3.25
3.25
3.00
3.00
2.75
2.50
2.25
2.25
0
10
20
30
40
0.5
2.00
3952 G07
VIN = 2.9V
0.4
0.3
0.2
0.1
INTVCC (V)
VIN (V)
1.5
2
2.5
3
4
3.5
VIN (V)
VIN (V)
6
INTVCC Dropout vs Load and
Temperature
INTVCC vs Input Voltage, Dropout
2.75
2.50
150
3952 G06
INTVCC DROPOUT (V)
3.50
INTVCC (V)
INTVCC (V)
INTVCC vs Input Voltage
2.00
150
3952 G03
Quiescent Current
vs Input Voltage
1.00
–1.00
1.25
–50
150
3952 G02
EN/UVLO Bias Current above
Threshold
EN/UVLO CURRENT (µA)
VEN = 1.25V
EN/UVLO RISING
3952 G08
0
150°C
25°C
–50°C
0
3
9
6
LOAD (mA)
12
15
3952 G09
3952fa
For more information www.linear.com/LT3952
LT3952
TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC Current Limit
vs Temperature
2.050
2.08
IREF = 100µA
2.06
NORMAL: INTVCC = 2.5V
2.025
2.04
15
FOLDBACK: INTVCC = 0V
VREF (V)
20
VREF (V)
INTVCC CURRENT LIMIT (mA)
30
25
2.000
2.00
1.96
1.975
5
1.94
0
50
100
TEMPERATURE (°C)
150
1.950
–50
0
50
100
TEMPERATURE (°C)
3952 G10
10
OVFB RISING
1.22
1.20
SWITCHING FREQUENCY (MHz)
OVFB FALLING
VFB
1.18
OPENLED RISING
1.16
OPENLED FALLING
1.14
1.12
–50
0
50
100
TEMPERATURE (°C)
10
20
Switching Frequency
vs Temperature
1.050
1
0.1
10
150
100
RT (kΩ)
1000
RT = 90.9k
1.025
1.000
0.975
0.950
–50
0
50
100
TEMPERATURE (°C)
3952 G14
5.0
ISP/ISN Mid-Scale Threshold
(CTRL = 0.7V) vs Temperature
128
254
CTRL = 2V
253 VISP = 60V
4.8
150
3952 G15
ISP/ISN Full-Scale Threshold
vs Temperature
SW Current Limit vs Temperature
40
30
3952 G12
Switching Frequency vs RT
3952 G13
127
4.4
251
ISP-ISN (mV)
ISP-ISN (mV)
252
4.6
250
249
126
125
124
248
4.2
123
247
4.0
–50
0
VIN (V)
SWITCHING FREQUENCY (MHz)
1.24
1.92
150
3952 G11
FB Thresholds vs Temperature
FB THRESHOLDS (V)
2.02
1.98
10
0
–50
SW CURRENT LIMIT (A)
Reference Voltage
vs Input Voltage
VREF Voltage vs Temperature
0
50
100
TEMPERATURE (°C)
150
3952 G16
246
–55
0
50
150
100
TEMPERATURE (°C)
3952 G17
122
–50
0
50
100
TEMPERATURE (°C)
150
3952 G18
3952fa
For more information www.linear.com/LT3952
7
LT3952
TYPICAL PERFORMANCE CHARACTERISTICS
ISP/ISN 1/10th Scale Threshold
(CTRL = 0.3V) vs Temperature
ISP/ISN Overcurrent Threshold
vs Temperature
395
ISP/ISN OVERCURRENT THRESHOLD (mV)
28
26
25
24
23
22
–50
0
50
100
TEMPERATURE (°C)
1.2
1.0
385
0.8
ISMON (V)
27
ISP-ISN (mV)
ISMON Voltage
vs ISP-ISN Voltage
375
0.4
365
0.2
355
–50
150
0
50
100
TEMPERATURE (°C)
0
150
3952 G19
0
50
100
150
ISP-ISN (mV)
200
3952 G20
VISP-ISN Threshold vs CTRL
255.0
VCTRL = 2V
250
3952 G21
ISP-ISN Threshold
vs Output Voltage
VISP-ISN Threshold vs FB Voltage
300
0.6
300
250
250
150
100
ISP-ISN (mV)
200
ISP-ISN (mV)
ISP-ISN (mV)
252.5
250.0
200
150
100
247.5
50
50
0
1.1
1.15
1.2
FB (V)
1.25
1.3
245.0
0
10
20
30
40
VOUT (V)
50
60
0
0
0.5
1
CTRL (V)
1.5
3952 G23
3952 G22
3952 G24
TG Driver Turn-On
TG Rise/Fall Time vs Capacitance
2
TG Driver Turn-Off
900
800
tRISE/FALL (ns)
700
600
500
PWM
2V/DIV
TG
5V/DIV
TG
5V/DIV
tFALL (ns)
400
300
tRISE (ns)
200
200ns/DIV
0
2.5
5
7.5
PMOS: VISHAY SILICONIX Si7309
PMOS: VISHAY SILICONIX Si7309
100
0
PWM
2V/DIV
3952 G26
200ns/DIV
3952 G27
10
CLOAD (nF)
3952 G25
8
3952fa
For more information www.linear.com/LT3952
LT3952
TYPICAL PERFORMANCE CHARACTERISTICS
IVINP-IVINN Threshold
vs Temperature
IVINCOMP vs IVINN-IVINP
60
58
1.225
0.8
1.175
1.150
54
–50
0
50
100
TEMPERATURE (°C)
0
150
0
20
40
60
80
1.125
–50
PWM Generator Currents
vs Temperature
10000
25
20
60
40
100
10
5
0
–10
1
1.5
2
1
0
10
100
PWM CAPACITOR (nF)
DIM VOLTAGE (V)
PWM Generator Thresholds
vs Temperature
THRESHOLD (V)
1.4
1000
PWM PULLDOWN CURRENT
–15
–50
0
50
100
TEMPERATURE (°C)
150
3952 G33
3952 G32
3952 G31
1.6
PWM PULLUP CURRENT
–5
10
20
0.5
DIM PULLUP CURRENT
15
1000
CURRENT (µA)
PWM FREQUENCY (Hz)
100
80
150
3952 G30
PWM Generator Frequency
vs PWM Capacitor
120
50
100
TEMPERATURE (°C)
3952 G29
PWM Generator Duty Cycle
vs DIM Voltage
0
0
IVINP-IVINN (mV)
3954 G28
0
OVLO FALLING
1.200
0.4
56
OVLO RISING
OVLO THRESHOLDS (V)
1.2
IVINCOMP (V)
IVINP-IVINN (mV)
1.275
1.250
62
PWM GENERATOR DUTY CYCLE (%)
OVLO Thresholds vs Temperature
1.6
64
PWM Generator Operation
and Step
UPPER THRESHOLD
1.2
PWM
0.5V/DIV
1
DIM
0.5V/DIV
1.2V PWM
THRESHOLD
0.8
0.6
ILED
200mA/DIV
LOWER THRESHOLD
0.4
0.2
0
–50
10ms/DIV
DIM = 0.5V
0
50
100
TEMPERATURE (°C)
3952 G35
150
3952 G34
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9
LT3952
PIN FUNCTIONS
GND (1, 12, 28, Exposed Pad Pin 29): Ground Pins.
The exposed pad of the LT3952 acts as both GND and
heat sink. It must be connected to a large copper area for
proper operation.
SW (Pins 2, 3, 4): Switch Pins. Minimize copper area at
these pins to increase efficiency and reduce EMI.
IVINN (Pin 5): Input Current Sense Amplifier Negative Input.
The input current sense amplifier reduces the switching
current in the case of an overload. VC is reduced when the
IVINP-IVINN voltage exceeds the 60mV built-in potential.
Tie IVINP-IVINN across an external sense resistor to set
auxiliary current limit. If unused, tie to VIN.
IVINP (Pin 6): Auxiliary Current Sense Amplifier Positive Input. Also acts as the bias supply for the amplifier
to provide a function independent from the VIN pin. The
IVINP/IVINN amplifier can operate from voltages either
above or below VIN. Tie this pin to the positive terminal of
a sense resistor, and do not use resistance in series with
this pin. If unused, tie to VIN.
VIN (Pin 7): Input Supply Pin. Bypass this pin with a capacitor to GND as close to the IC as possible.
EN/UVLO (Pin 8): Master Enable and VIN Undervoltage
Lockout. When low, the IC is put into shutdown mode and
the Q current is reduced to <1μA. This pin utilizes a 1.23V
comparator with hysteresis, as well as a hysteresis current
source for programming additional hysteresis externally.
Drive with a digital signal greater than 1.5V for simple
on/off control. Tie to a resistor divider between VIN and
GND to set an external UVLO threshold.
OVLO (Pin 9): Overvoltage Lock Out Comparator. This pin
disables switching and TG in the case of an overvoltage.
This pin utilizes a 1.23V comparator with hysteresis. When
the voltage at OVLO exceeds the threshold, the switching
is disabled until the voltage at OVLO falls 25mV below the
threshold. Tie to GND if unused.
INTVCC (Pin 10): Internal Low Dropout Regulator Output.
INTVCC is regulated to 3V, and must be bypassed with an
external capacitor of at least 2.2µF. INTVCC is the power
supply for the internal DMOS gate driver and control
10
circuitry. Users may apply <5mA loads to INTVCC. Overloading INTVCC can cause unintentional device shutdown
from INTVCC falling below the 2.68V UVLO threshold.
SYNC/SPRD (Pin 11): Frequency Synchronization and
Spread Spectrum Enable Pin. Tie low for fixed internal
clock, tie to INTVCC for spread spectrum internal clock, or
drive with an external clock for frequency synchronization
with no spread spectrum. When using an external clock for
frequency synchronization, RT resistor should be chosen
to program a switching frequency 20% lower than the
SYNC pulse frequency. Synchronization (switch turn-on)
occurs 50ns after the rising edge of SYNC.
VC (Pin 13): gm Amplifier Output for External Loop
Compensation. Stabilize the loop with a C or series RC
network. This pin is set to a high impedance state during
PWM dimming off-time.
RT (Pin 14): Switching Frequency Adjustment Pin. Set
switching frequency using a resistor to GND (see Typical
Performance Characteristics for values). For SYNC function, set the frequency 20% slower than the SYNC pulse
frequency. Do not leave this pin open. PCB layout must
have this component close to the IC.
DIM (Pin 15): PWM Generator Control Voltage. This pin
outputs a fixed 20μA current, and controls a triangle wave
generator on the PWM pin to determine the PWM duty
cycle. 0.2V to 1.2V range on DIM adjusts PWM duty from
0% to 100%. Float this pin or tie to INTVCC if unused, tie a
resistor from DIM to GND to set a fixed voltage, or apply
an external voltage to DIM for adjustable PWM duty cycle.
FB (Pin 16): Output Voltage Loop Feedback Pin. Connect
to a resistor divider from VOUT. In constant-voltage applications, FB sets the output voltage. In constant-current
applications, the FB divider is set higher than the expected
output voltage to act as open-LED protection. As the voltage at FB rises to within 45mV of the regulation point,
the OPENLED flag is asserted if the output current also
falls below one-tenth the full-scale value. If the FB voltage
exceeds the regulation point by 30mV, the switching is
terminated and the TG pin pulls high in order to disconnect the LED load.
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LT3952
PIN FUNCTIONS
CTRL (Pin 17): Output Current Sense Adjust Pin. Sets
voltage regulation threshold across ISP/ISN current sense
resistor. 0.2V to 1.2V range on CTRL adjusts ISP/ISN
threshold from 0mV to 250mV. Tie to VREF or INTVCC for
fixed 250mV threshold. Below 100mV, the CTRL pin acts
as an auxiliary PWM input for combination PWM/analog
dimming on a single pin.
VREF (Pin 18): Reference Voltage Output. This pin outputs
a fixed 2V reference, and supplies up to 100μA for use
in generating a reference voltage for the CTRL pin. When
using a resistor divider, bypass this pin with 100nF to GND.
SS (Pin 19): Soft-Start and Hiccup Control Pin. This pin
modulates oscillator frequency and VC voltage clamp when
it is below 1.7V. A capacitor on the pin sets the soft-start
interval as well as hiccup retry timing in fault mode. The
SS pin has a 25μA pull-up current in normal mode, a 2.5μA
pull-down current in hiccup mode, and a 120Ω pull-down
resistance in start-up mode. Optional latchoff mode is set
with a 750k pull-up resistor from INTVCC to SS.
PWM (Pin 20): On/Off Control. Used for TG on/off control
and PWM dimming of the LED. Logic low idles regulator
to a lower Q current, makes the TG pin drive to ISP level,
and makes the VC pin high impedance. Logic high turns
on error amplifier, enables switching and TG. The PWM
threshold is 1.2V. Tie to VREF or INTVCC for continuous
operation. The PWM pin also supplies ±10µA switched
current sources to generate a triangle wave on external
capacitor for the PWM dimming generator. It is safe to
overdrive these currents with an external signal.
SHORTLED (Pin 21): Open-Drain Short-Circuit Indicator.
SHORTLED pulls low in the case of an LED overcurrent
fault, and releases during the start-up phase of the next
soft-start cycle. The state of SHORTLED is only updated
when the PWM pin is high. Tie this pin to desired logic
high voltage with an external resistor. The maximum
recommended sink current is 2mA to limit excess power
dissipation. Leave the pin open if unused.
OPENLED (Pin 22): Open-Drain Open-LED Indicator.
OPENLED pulls low when the voltage at the FB pin is
within 45mV of the regulation point and the LED current
has dropped to 10% of the full-scale output. OPENLED
releases when the FB voltage falls below the threshold.
The state of OPENLED is only updated when the PWM
pin is high. Tie this pin to desired logic high voltage with
an external resistor. The maximum recommended sink
current is 2mA to limit excess power dissipation. Leave
the pin open if unused.
IVINCOMP (Pin 23): Auxiliary Current Sense Amplifier
Monitor Output. The voltage at IVINCOMP is a 20× amplified and buffered version of the IVINP-IVINN differential
voltage, and the VC voltage will be reduced when IVINCOMP reaches its 1.2V threshold. A 1µF capacitor to GND
is suggested to filter inductor ripple and compensate the
input current loop. During PWM dimming, the IVINCOMP
pin stores the input current regulation loop value on the
capacitor during the PWM off time. Do not load this pin.
If the input current regulation loop is not used, this pin
may be connected to GND.
ISMON (Pin 24): Output Current Monitor Pin. The voltage at ISMON is a 4× amplified and buffered version of
the ISP, ISN differential voltage. During PWM dimming,
the ISMON voltage continues to reflect the instantaneous
output current, falling during the PWM low time.
TG (Pin 25): Top Gate Driver Output. An inverted and levelshifted version of the PWM input signal. Drives the gate of
an external PMOS transistor between VISP and VISP – 7.5V
to provide load-side on/off control, PWM dimming, and
fault mode disconnect. Leave TG unconnected if not used.
ISN (Pin 26): Output Current Sense Amplifier Negative
Input. Connect this pin to the load side of the output current sense resistor. If unused, tie to output voltage.
ISP (Pin 27): Output Current Sense Amplifier Positive
Input. Also serves as the positive rail for the TG driver.
Limit impedance in series with this pin.If unused, tie to
output voltage.
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11
LT3952
BLOCK DIAGRAM
6
VIN
16
IVINN
24
ISN
+
–
0.375V
+
x1
LEDOC
0.1V
1.2V
+
PWMON
CTRPWM
0.2V
TG
C/10
PWM
25
1.2V ISP – 7.5V
1.2V
+
–
CTRPWM
–
–++
–
+
–
2µA
OVLO
–
+
FBOV
0.3V
+
1.23V
+
2V
ISP
+
–
VMODE
140µA
+
–
–
–
SHDN
VREF
INTVCC
x4
1.23V
–
–
IVINCOMP
EN/UVLO
18
ISMON
+
1.155V
+
950mV
+
+–
INTVCC
10µA
Q
R
+
1.23V
OVSHDN
–
9
26
ISP
UV
LDO
x20
8
27
CTRL
+–
+
23
17
FB
–
10
INTVCC
5
IVINP
–
7
PWM
20
10µA
S
–
Q
+
INTVCC
20µA
DIM
VC
PWMON
22
OPENLED
SS
G
Q
C/10
VMODE
S
D
Q
–
TSD
(165°C)
FBOV
TSD
21
SHORTLED
UV
OCP
1.2V
SS
SHDN
SS
19
12
+
+
–
SYNC/SPRD
11
+
0.1V
–
+
–
OSC +
SSFM
2.5µA
SS/FLT
R Q
S
+
PWMON INTVCC
LEDOC
25µA
13
SW
2, 3, 4
PWM
LEDOC
OVP
OTP
TSD
R
15
+
SSFM OFF
SSFM ON
22mΩ
–
RT
14
GND
1, 12, 28, 29
3952 BD
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LT3952
OPERATION
The LT3952 is a fixed-frequency, current mode boost converter with a feature set ideal for driving high power LED
lamps. It provides input and output current regulation, as
well as output voltage regulation and fault handling. The
operation of the LT3952 is best understood by referring to
the Block Diagram. In normal operation, with the PWM pin
low, the switching is disabled, the TG pin is pulled high to
ISP to turn off the PMOS disconnect switch, the VC pin is
high impedance to store the previous switching state on
the external compensation capacitor, and the ISP/ISN pin
bias currents are reduced to leakage levels.
When the PWM pin transitions high, the TG pin transitions
low after a short delay. At the same time, the internal oscillator wakes up and generates a pulse to set the PWM
latch, turning on the internal NMOS power switch. The
switch current is sensed and added to a stabilizing slope
compensation ramp, and the resultant signal is compared
to the VC voltage. The inductor current increases linearly
during the switch on-time. When the current sense signal
exceeds the VC value, the latch is reset and the internal
NMOS power switch is turned off. During the switch
off-time, energy is transferred from the inductor and the
inductor current decreases. At the completion of each
oscillator cycle, internal signals such as slope compensation return to their starting points and a new cycle begins
with the set pulse from the oscillator.
Through this repetitive action, the IC establishes a switching duty cycle to regulate a current or voltage in the load.
The VC signal is integrated over many switching cycles,
and is an amplified version of the difference between the
LED current sense voltage, measured between ISP and
ISN, and the target difference voltage set by the CTRL pin.
In this manner, the error amplifier sets the correct peak
switch current level to keep the LED current in regulation.
If the error amplifier output increases, more current is
demanded in the switch; if it decreases, less current is
demanded. If the switch current exceeds the internal 4.5A
current limit, the latch is reset regardless of the state of
the PWM comparator. Likewise, in any fault condition; i.e.,
FB overvoltage (VFB > 1.23V), LED overcurrent (VISP-ISN
> 375mV), overvoltage lockout or INTVCC undervoltage
the switching is immediately disabled.
In addition to the VISP-ISN to CTRL feedback loop, the
LT3952 also provides additional loops to control input
current and output voltage. The loops are connected in a
wired-OR configuration, where the auxiliary loops are only
allowed to reduce the value of VC in the event that one or
more exceeds its threshold. This means that even if one
or more of the auxiliary loops is below its regulation point,
VC will not rise unless the output (LED) current sense is
also below its regulation point.
The first auxiliary loop is the output voltage feedback loop
using the FB pin. It is typically used to prevent the output
voltage from exceeding a safe value. The voltage at the FB
pin is compared to an internal reference voltage of 1.2V,
and the amplified difference pulls down the VC pin in the
case that FB exceeds 1.2V. As VC drops, the switching
current reduces and in this manner the output voltage is
regulated so that FB = 1.2V.
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13
LT3952
OPERATION
The second auxiliary loop is the input current limit using the IVINN, IVINP, and IVINCOMP pins. Similar to the
output (LED) current loop, the input current is sensed
as the differential voltage across a sense resistor. As the
average IVINP/IVINN differential voltage exceeds 60mV,
IVINCOMP reaches its 1.2V threshold, and VC is reduced
in order to limit the input current to the 60mV threshold.
In order to program an external UVLO, tie the EN/UVLO
pin to a resistor divider between VIN and GND. The divider
ratio determines the baseline turn-off/turn-on thresholds
and the value of the upper resistor determines the additional hysteresis.
VIN
LT3952
INTVCC Bypass Capacitor
INTVCC is the internal power supply for the IC, and supplies the gate drive to the internal power switch. A bypass
capacitor is required from INTVCC to GND for stability
and filtering of the switching noise. For best results, use
a ceramic capacitor of 2.2µF or greater, and place the
capacitor as close to the IC as possible.
VREF Bypass Capacitor
VREF is the 2V reference output and can be bypassed with
100nF to GND. For best results, place the bypass capacitor
close to the IC and away from the noisy switching nodes.
Programming the Turn-On/Turn-Off Thresholds
with the EN/UVLO Pin
The LT3952 provides an adjustable VIN undervoltage lockout (UVLO) function using the EN/UVLO pin. The EN/UVLO
function provides a precision 1.23V falling threshold with
75mV internal hysteresis as well as a 2μA pull-down current
in the off state to provide additional, user-programmable
hysteresis. This pin can also be driven with a logic level
greater than 1.5V or tied to VIN for always-on operation.
14
R1
EN/UVLO
R2
3952 F01
Figure 1
The most important (and precise) threshold is the turnoff threshold from VIN falling. The following equations
determine the resistor values:
 R1
VUV(FALLING) = 1.23 •  1+ 
 R2 
 R1
VUV(RISING) = 1.305 •  1+  + 2µA •R1
 R2 
For example, a 12V falling UVLO with roughly 10% total
hysteresis requires 185k for R1. The closest standard
value is 187k, therefore:
R1 = 187k
R2 = 21.5k
VUV(FALLING) = 11.93V
VUV(RISING) = 13.03V
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LT3952
OPERATION
Programming the Overvoltage Disable
with the OVLO Pin
It is also possible to program a disable threshold if the
input voltage rises too high. The OVLO pin has a 1.23V
comparator with 25mV internal hysteresis. If the voltage
at OVLO exceeds the 1.23V threshold, the switching is
disabled, TG pulls high, and the SS pin pulls low. The
device begins a new soft-start sequence when the voltage
at OVLO has fallen 25mV below the threshold.
Continuing the previous equation, the desired value of R3
is 8k for an OVLO threshold of 32V. Subtract this from the
previous value of R2 in order to find the value of R2A. In
our case, R3 = 8.06k and the closest 1% resistor for the
new R2A value is 13.3k. The thresholds are recalculated
if desired from the expanded divider ratios:
R1 

VUV(FALLING) = 1.23 •  1+
 R2A +R3
R1 

VUV(RISING) = 1.305 •  1+
+ 2µA •R1
 R2A +R3
Although it is possible to connect this pin with an independent resistor divider, the component count is minimized by
splitting the bottom resistance of the standard EN/UVLO
divider to generate an additional tap point.
 R1+R2A 
VOV(RISING) = 1.23 •  1+


R3 
VIN
 R1+R2A 
VOV(FALLING) = 1.205 •  1+


R3 
R1
EN/UVLO
LT3952
R2A
R3
In our example:
0VLO
3952 F02
R1 = 187k, R2A = 13.3k, R3 = 8.06k
Figure 2
VUV(FALLING) = 11.998V
Using the previous values of R1 and R2 from the UVLO
section, the new R3 value is computed using the desired
rising threshold by:
VUV(RISING) = 13.104V
VOV(RISING) = 31.796V
VOV(FALLING) = 31.151V
 R1+R2 
R3 = 1.23 • 

 VOV(RISING) 
The middle resistor will be designated R2A. To obtain the
value for R2A, subtract the calculated value of R3 from
the old R2 value.
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15
LT3952
OPERATION
300
The LED current is programmed through the combination
of an external sense resistor and a voltage on the CTRL
pin. The CTRL voltage adjusts the setpoint of the current
sense amplifier on the ISP and ISN pins from 0mV to
250mV, and the external sense resistor defines the output
current for a given setpoint. The current sense resistor is
typically placed at the top of the LED strand, although the
rail-to-rail ISP/ISN inputs allow placement at the bottom
of the strand as well.
250
ISP-ISN (mV)
LED Current Control and Monitor
200
150
100
50
0
0
0.5
1
CTRL (V)
1.5
2
3952 F04
ISP
RLED
LT3952
Figure 4
SENSED
CURRENT
ISN
The required CTRL voltage for a desired analog setpoint
is computed by:
3952 F03
Figure 3
VCTRL = 0.2 + 4 • VISP-ISN
The required sense resistor for a desired output current
is computed by:
RLED =
VISP-ISN
IOUT
In the case of the fixed 250mV setpoint:
RLED =
0.25
IOUT
LED Current Monitoring
For example, a 500mA output requires a 0.5Ω sense resistor when using the fixed 250mV setpoint.
In adjustable mode, the working range of CTRL is from 0.2V
to 1.2V and adjusts the setpoint of ISP and ISN from 0mV
to 250mV. In this manner, analog dimming is achieved.
16
As the CTRL voltage nears 1.2V, a crossover from adjustable
threshold to a precision internal 250mV setpoint takes place
and some nonlinearity occurs as shown in the ISP-ISN vs
CTRL graph in the Typical Performance Characteristics.
It is therefore desirable to drive the CTRL pin well above
1.2V when the 250mV setpoint is desired. Tying CTRL to
the 2V VREF output is an excellent method of doing so.
The ISMON pin provides a buffered output representing
the differential voltage on ISP-ISN for current monitoring
applications. The normal working range of ISMON is from
0V to 1V, and the gain from ISP-ISN to ISMON is 4. This
corresponds to a 1V output at ISMON when the ISP-ISN
differential voltage has reached the 250mV maximum.
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LT3952
OPERATION
External PWM Dimming
The PWM pin, in combination with an external PMOS
transistor driven from the TG pin, allows on/off control
and PWM dimming of the LED current.
The PWM pin has a fixed 1.2V threshold, and driving
PWM higher than 1.2V enables the device for switching
and causes the TG pin to drive to a level roughly 7.5V
lower than the voltage at ISP. During the low time of
PWM, the TG pin is driven to the voltage at ISP to turn
off the external PMOS, and the LT3952 is put into a low
power standby state. Switching and the error amplifiers
are disabled and the VC pin is three-stated to preserve
the value of VC voltage for accelerated start-up upon the
next rising edge of PWM.
The CTRL pin also offers a PWM function to allow analog
and digital dimming on a single pin. Below 0.1V on CTRL,
the device is also put into standby mode with SW, TG, and
the error amplifiers disabled. Keep in mind that between
0.2V and 0.1V on CTRL, the device is not disabled, although
the output current is commanded to 0. The value of VC
reduces towards the minimum, and TG keeps the output
PMOS enabled, which discharges the output through the
LED lamps. For effective PWM dimming using the CTRL
pin, please ensure that the low voltage on CTRL is below
0.1V. This is easily obtained using an external open-drain
device to pull down a resistor divider used to generate the
CTRL setpoint. Alternately, enabling and disabling a DAC
output driving CTRL also gives excellent results.
pull-up and pull-down current sources generate a triangle
waveform on the PWM pin whose peak and valley points
are defined by the voltage on the DIM pin and whose
frequency is defined by the external capacitor.
VPWM-VALLEY = VDIM
VPWM-PEAK = VDIM + 950mV
fPWM =
5200
CPWM (µF)
20µA
LT3952
DIM
VDIM + 950mV
PWM
VDIM
3952 F05
Figure 5
By raising and lowering the voltage on the DIM pin, the
triangle wave intersects the 1.2V PWM threshold at different points, changing the PWM duty cycle.
VPWM
1.2V
VDIM
3952 F06
Figure 6. Lower DIM Voltage
VPWM
1.2V
VDIM
Internal PWM Generator
The PWM pin can also provide a self-oscillating PWM
generator for standalone operation by simply tying a small
capacitor from PWM to GND. In this configuration, 10µA
3952 F07
Figure 7. Higher DIM Voltage
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17
LT3952
OPERATION
As the DIM pin exceeds 1.2V, the PWM duty cycle will be
100%. As the DIM pin exceeds 2.3V, the internal PWM
generator is disabled along with the switched 10µA pulldown on PWM. The PWM pin will continue to be pulled
to INTVCC with the 10µA pull-up current. For applications
utilizing external PWM dimming, it is recommended to
disable the internal PWM generator by floating the DIM
pin or tying it to INTVCC. This will provide the fastest PWM
response for high dimming ratios.
Programming the frequency of PWM dimming consists
only of selecting the proper capacitor for the PWM pin
according to:
C (nF ) =
5200
fPWM (Hz )
For adjustable duty cycle control, an external voltage can
be applied at the DIM pin using a DAC or external supply.
To slowly increase the light output upon start-up or restart,
a capacitor can also be used with the DIM circuit. To fade
from dark to full brightness, only a capacitor is required.
To fade from dark to a fixed duty cycle, place a capacitor
in parallel with the DIM resistor.
Upon start-up or fault retry, an internal pull-down with 2k
series resistance is applied to the DIM pin to discharge any
external capacitor before the start-up sequence begins. Be
aware that this will temporarily load an external voltage
applied to DIM.
A common selection is 39nF for roughly 133Hz.
LT3952
Programming the PWM duty cycle consists of setting a
voltage on the DIM pin according to:
VDIM(V) = 0.95 •Duty + 0.25
DIM
LT3952
DIM
3952 F08
As shown in Figure 5, a single resistor in combination with
the 20µA output current of DIM can be used to program
the duty cycle.
Figure 8. Fade on to Full Brightness, or to Preset Duty
RDIM(kΩ) = 47.5 •Duty +12.5
18
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LT3952
OPERATION
Input Current Limit
The LT3952 provides adjustable input current limiting
through the IVINP/IVINN/IVINCOMP amplifier. Connect
the IVINP and IVINN sensing terminals across a resistor
in series with the input. A 20x amplified version of the
IVINP–IVINN differential is generated at IVINCOMP. A
capacitor at IVINCOMP provides filtering and averaging
of the input ripple.
As the average IVINP–IVINN differential reaches 60mV,
the IVINCOMP voltage will reach its 1.2V regulation
threshold and the cycle-by-cycle switch current will be
reduced. In this manner, the input current is regulated
to 60mV differential between IVINP and IVINN.
RSENSE (mΩ ) =
60mV
IIN(LIM ) ( A )
For example, a 2.4A input current limit is programmed
with a 25mΩ sense resistor.
SENSED
CURRENT
RIVIN
IVINP
Input Current Monitor
An input current monitor is available as the voltage on
IVINCOMP, which reflects a voltage equal to 20× the
IVINP-IVINN differential voltage and has a working range
of 0V to 1.2V as the IVINP-IVINN voltage varies from
0mV to 60mV.
IVINCOMP is a high impedance output and should not be
loaded. Averaging of current sense ripple, and compensation of the feedback loop is achieved using a 1µF capacitor
from IVINCOMP to GND.
Output Voltage Regulation/Limiting
The LT3952 provides a voltage-feedback error amplifier
through the FB pin to provide output voltage regulation
and limiting for open-LED protection.
In the case of an open-LED strand, the current commanded
by CTRL is never achieved and the device continues to
drive the output voltage higher. If left unchecked, this could
result in overvoltage damage to the external components
and the power switch itself, and therefore an output voltage limit is required.
IVINN
LT3952
IVINCOMP
3952 F09
Figure 9
In some cases, such as deep discontinuous conduction,
a large input ripple current may cause the input current
limit to activate early, cutting into the typical regulation
profile. In this situation, it is possible to filter the ripple
down to a smoother level using an external RC network.
By connecting FB to a resistor divider between VOUT and
GND, the maximum output voltage regulates at the 1.2V
threshold of the FB pin. The maximum output voltage is
computed as follows:
RIVIN
CFLT
Be aware that input current on start-up and PWM dimming is larger than steady state due to the output current
required to fill the output capacitor. It is recommended to
set the input limit appropriately to prevent interruption of
the regulated output.
 R4 
VOUT ( V ) = 1.2 •  1+ 
 R5 
VOUT
RFLT
LT3952
IVINP
R4
FB
IVINN
R5
LT3952
3952 F11
IVINCOMP
Figure 11
3952 F10
Figure 10
3952fa
For more information www.linear.com/LT3952
19
LT3952
OPERATION
A simple method to determine the proper resistor values
is to choose a value of R5 that draws a tolerable amount
of current at the 1.2V regulation point, and to compute
R4 by using:
R4 = ( VOUT – 1.2) •
R5
1.2
The OPENLED pin pulls low when the following two conditions are met:
1.The voltage at FB rises to within 45mV of the 1.2V
regulation point.
2. The output current is detected to be less than one-tenth
of the value commanded by CTRL.
For example, R5 = 24k draws 50μA at the regulation point,
and for a 24V output limit, the desired value of R4 is 456k.
The closest standard value to this is 453k, providing 23.85V
output voltage limit.
It is necessary to set the regulation point slightly higher
than the worst-case voltage drop of the LEDs to avoid
cut-in of the voltage limit during normal regulation.
Open LED Flag and Overvoltage Protection
The LT3952 provides an indicator of the open-LED condition
on the OPENLED pin, as well as an internal overvoltage
detection to prevent output overshoot if the LED strand
goes open under load. Both of these features are based
on the voltage at the FB pin.
The OPENLED pin consists of an open-drain NMOS pull
down to be connected with an external pull-up resistor to
the user’s desired voltage. This pin tolerates up to 42V,
and has a pull-down strength of 60Ω. Please be aware
of power dissipation and keep the OPENLED current to a
few mA maximum.
The OPENLED pin releases when the voltage at FB falls
to 65mV below the 1.2V regulation point. This sequence
prevents false OPENLED flags from momentary overshoot.
An overvoltage condition is detected by the voltage at
FB rising to 30mV above the 1.2V regulation point. Upon
detection of an overvoltage condition, the switching is
disabled and TG is pulled high to disconnect and protect
the load. Switching is re-enabled when the FB voltage
falls by 15mV. An overvoltage condition does not affect
the state of the OPENLED pin.
Switching Frequency
The switching frequency is programmed with a resistor
from the RT pin to GND. The RT pin is regulated to 1.2V,
and the output current of RT adjusts the oscillator frequency.
LT3952
RT
RT
3952 F12
Figure 12
20
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LT3952
OPERATION
The overall switching period is defined by the sum of
two parts: a fixed 50ns off-time that defines DMAX, and a
variable time defined by the RT current. To determine the
proper RT value for a desired switching frequency, using
the following equation:
R T (kΩ ) =
88.9
fSW (MHz)1.13
For example, a 2MHz switching frequency results in a
desired RT resistance of 40.6k, which has 40.2k as the
closest standard value.
Table 1 provides some commonly used values.
Table 1. Switching Frequency vs RT Value
fSW (MHz)
RT (kΩ)
3.0
25.5
2.0
40.2
1.0
90.9
0.4
243
0.215
470
Frequency Synchronization and Spread Spectrum
The LT3952 SYNC pin acts as both an external clock input
for frequency synchronization and the enable signal for
internal spread spectrum feature. Tie the SYNC/SPRD pin
low for fixed-frequency internal clock, tie to INTVCC for
spread-spectrum internal clock, or drive with an external
clock for frequency synchronization with no internal
spread spectrum.
When synchronizing to an external clock, the RT resistor should be chosen to program a switching frequency
20% lower than the external clock frequency. Even when
synchronizing, a soft-start cycle will first start the oscillator in frequency foldback to minimize inrush current. As
the soft-start cycle nears completion, the device will then
transition to the external frequency.
When the SYNC/SPRD pin is tied high for greater than
32 clock cycles, the device will enable spread-spectrum
clocking for EMI reduction. By continuously varying the
oscillator frequency, spread spectrum distributes the EMI
power generated during the switching cycle over a group
of frequencies rather than concentrating it at a single
frequency. Therefore, the measured EMI power at any
single frequency is reduced compared to that of fixedfrequency operation.
In spread-spectrum mode, the oscillator frequency is varied
in a pseudorandom manner from the nominal frequency
to 31% above nominal in 1% steps. This unidirectional
adjustment allows LT3952 to avoid a sensitive band in the
system simply by programming the nominal frequency
slightly above it. The proportional step size allows the user
to easily determine RT value for their specified EMI test
bin size, and the pseudorandom method provides tone
suppression from the frequency variation itself.
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21
LT3952
OPERATION
The pseudorandom value is updated proportionally to
the oscillator frequency, using a rate of fSW/32. This rate
allows multiple passes of the entire group of frequencies
during standard EMI test dwell times.
90
AMPLITUDE (dBµV)
80
Boost:
SSFM OFF
70
60
SSFM ON
50
40
30
20
0
LBOOST ≥
(
VIN(MIN) VLED(MAX) – VIN(MIN)
)
VLED(MAX) •1A • fSW
Buck:
10
(
3952 F14
START 700kHz
RES BW 9kHz VBW 90kHz
END 1.7MHz
DWELL TIME 10ms
(250 Hz)
Figure 13. Average Conducted EMI – 1MHz
Inductor selection consists of two parameters: saturation
current rating and inductance value. A higher switching
frequency allows the use of a smaller inductance value at
the expense of increased switching loss.
The saturation current rating of the inductor is selected
appropriately for the 4A current limit of the device.
An approximation for maximum inductor current (efficiency
= 100%) is based on the maximum LED current and the
input/output ratio:
 VLED(MAX) 
IL(MAX) ( A ) = 
•I
VIN(MIN)  LED

LBUCK ≥
VLED(MAX) VIN(MIN) – VLED(MAX)
)
VIN(MIN) •1A • fSW
Buck-Boost:
Inductor Selection
22
The maximum steady-state inductor current, IL(MAX),
should be less than 3A to allow for current ripple and
transient response. The desired inductance is determined
based on the steady-state current ripple. A typical rule of
thumb is to set the inductor current ripple to a maximum
of 25% of the switch current limit.
 VIN(MIN) • VLED(MAX) 

V
 LED(MAX) + VIN(MIN) 
LBB ≥
fSW •1A
Table 2 provides some recommended inductor vendors.
Table 2. Inductor Manufacturers
VENDOR
WEB
Wurth Elektronik
www.we-online.com
Coilcraft
www.coilcraft.com
Cooper
www.cooperet.com
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LT3952
OPERATION
Output Capacitor Selection
Schottky Rectifier Selection
In the case of driving LEDs, their exponential current/
voltage characteristic dictates that output voltage ripple
translates almost directly to LED current ripple. Although
the effect is not visible to the eye, large LED current ripple
may affect the output current accuracy and color spectrum
and it is therefore advisable to keep the output voltage
ripple below a few percent.
The power Schottky diode conducts the switching current
during the switch off-time. Select a diode rated for at least
1.5 • ILED to account for current variation from efficiency
and inductor ripple. The reverse-breakdown voltage should
be at least 20% greater than the maximum reverse voltage
expected in circuit.
For the boost and buck-boost topologies, output current is delivered in pulses and the filtering requirement
is higher than for the buck topology with its continuous
output current. Assuming a low ESR ceramic capacitor and
25% inductor current ripple, use the following equations
to compute the required output capacitance for a desired
output ripple voltage, ∆VLED.
Boost, Buck-Boost:
COUT =
ILED • ( VLED – VIN )
VLED • ∆VLED • fSW
Buck:
COUT =
0.3 •ILED
8 • ∆VLED • fSW
The input capacitor is also selected based on desired
voltage ripple. Complementary to output capacitor selection, the discontinuous input current of the buck topology
requires more filtering than the continuous input current
of the boost or buck-boost. Use the following equations
to determine the input capacitance required for a desired
input ripple voltage, ∆VIN.
A high side PMOS disconnect switch with a minimum VTH
of –2V is recommended in most LT3952 applications. This
switch is enabled and disabled during PWM dimming,
and disconnects the output in shutdown and during fault
conditions. Select a PMOS transistor with a VDS rating
greater than the open-LED regulation voltage set by FB,
and with a continuous current rating greater than ILED.
Soft-Start
0.3 •ILED •
The LT3952 incorporates flexible soft-start and the option
of hiccup or latchoff mode for customizing fault response.
The SS pin provides a 25μA pull-up current for charging,
a 2.5μA pull-down current for discharging, and a 120Ω
NMOS pull-down switch for clearing an external softstart capacitor. The state of each of these components is
determined by the soft-start/fault sequence, and will be
described herein.
VIN •ILED • ( VIN – VLED )
∆VIN • VIN2 • fSW
Shutdown Mode: During shutdown mode, all SS currents and the pull-down switch are disabled, effectively
Boost, Buck-Boost:
VLED
VIN
CIN =
8 • ∆VIN • fSW
Buck:
The LT3952 uses an internal transconductance error
amplifier whose VC output compensates the control loop.
The external inductor, output capacitor and the compensation resistor and capacitor determine the loop stability.
The inductor and output capacitor are chosen based on
performance, size and cost. The compensation resistor
and capacitor at VC are selected to optimize control loop
response and stability. For typical LED applications, a
6.8nF to 10nF compensation capacitor at VC is adequate,
and a series resistor increases the slew rate on the VC pin
to maintain tighter regulation of LED current during fast
transients on the input supply of the converter.
External PMOS Disconnect/PWM Switch
Input Capacitor Selection
CIN =
Loop Compensation
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23
LT3952
OPERATION
three-stating the SS pin. This is to avoid sinking quiescent
current in the case that an external resistor pull-up is
connected to SS.
When the device leaves shutdown mode, the NMOS pulldown switch is activated to clear the voltage at the soft-start
capacitor. The device waits in this state until the voltage
at SS drops below 0.2V, and until start-up is enabled
as defined by PWM > 1.2V and CTRL > 100mV. If both
enable signals are already valid upon leaving shutdown
mode, the NMOS pull-down is activated for 10µs longer
than is required to pull the SS voltage below 0.2V. In all
cases, this action provides a start-up profile where the
initial voltage at SS can be considered approximately 0V.
In the event that the device is shut down by EN/UVLO
or the INTVCC voltage dropping below 2.68V, the SS pin
initially goes high impedance and then restarts the clear,
charge sequence as described.
Start-Up Mode: Once start-up is enabled by PWM and
CTRL both valid, the NMOS pull-down switch is disabled
and the 25μA charging current is enabled. The voltage at
SS begins ramping in a linear manner until it reaches 0.2V,
at which point switching and the TG driver are enabled.
From 0.2V to 1.7V on SS, the frequency and the current
limit are increased linearly with SS voltage to provide
a smooth start-up profile with low inrush current. The
required soft-start capacitor for a desired start-up time
is computed from the 1.5V range of SS and the 25μA
charge current.
CSS (nF) = 16.67 • tSS (ms)
For example, a soft-start time of roughly 0.5ms is generated with an 8.2nF capacitor.
Depending on output and load conditions the device may
enter regulation before SS reaches 1.7V, however it is
the combination of the 1.7V threshold and the sensing of
at least one-tenth of the output current defined by CTRL
that signifies the successful completion of soft-start. This
becomes important when start-up is enabled by a low duty
cycle PWM signal. The explanation is as follows:
A low duty cycle PWM signal could cause excessive
start-up times if it were allowed to interrupt the softstart sequence. Therefore, once start-up is initiated by
24
PWM > 1.2V and CTRL > 150mV, it temporarily ignores
a logical disable by either of those signals. The device
continues to soft-start with switching and TG enabled
until either the voltage at SS reaches the 1.7V level, or the
output current reaches one-tenth of the full-scale value. At
this point the device begins following the dimming control
as designated by PWM or CTRL. If at any time an output
overcurrent is detected, SW and TG will be disabled even
as SS continues to charge. This will be discussed in further
detail in the Fault Handling section.
PWM
2V/DIV
LATCHED
STARTUP BEGINS
NORMAL
PWM CYCLE
SS
2V/DIV
SW
20V/DIV
ILED
200mA/DIV
OUTPUT READY:
LATCHED
STARTUP ENDS
10ms/DIV
3952 F15
Figure 14. PWM Latched Startup
One note is when PWM dimming using CTRL, the output
current is commanded to zero during the low time of CTRL
even as the soft-start voltage rises.
Fault Handling: Although the fault handling sequence may
change based on the soft-start conditions, the switching
is disabled and the TG driver immediately pulls high upon
detection of an output overcurrent fault. This provides
safe output disconnect even in the case of a dead short
on the output.
When an overcurrent is detected and TG and SW are
disabled, SS is still required to charge to the 1.7V upper
threshold before it begins discharging back down using
the 2.5μA current source. If SS is already at or above 1.7V,
it begins discharging immediately upon the disable of TG
and SW. If SS is still in the start-up phase when an output
overcurrent fault is detected, then SS continues charging
even as TG and SW are disabled. It charges to the 1.7V
level before reversing direction and discharging to the
0.2V level with the 2.5μA current source. This provides
additional delay to allow the system to recover from the
overcurrent condition.
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LT3952
OPERATION
Once SS has discharged to the 0.2V level, the sequence of
clearing SS with the 120Ω NMOS pull-down and restarting
the 25μA charge phase reoccurs as previously described.
Switching and TG are not re-enabled until SS again climbs
to the 0.2V threshold. If at this point an overcurrent is
still detected, then SW and TG are again disabled as SS
continues to climb to the 1.7V threshold before reversing
direction. In this manner, a hiccup retry cycle is obtained
with a maximum switching duty cycle of 10%, the ratio
of 25μA pull-up to 2.5μA pull-down currents. This low
hiccup duty cycle reduces input power during sustained
overload conditions.
1.7V
SS
0.2V
Figure
15. SS in Sustained Hiccup Mode
SHORTLED
3952 F13
If a latched-off response is desired, a user simply sets a
pull-up resistor from INTVCC to SS with a value low enough
to prevent SS from discharging to the 0.2V level. For the
low pull-down current of 2.5μA, even a relatively large
value of 750k to INTVCC prevents SS from reaching the
automatic retry threshold and effectively provides a fault
latchoff. At this point, a manual retry is obtained by entering
and exiting shutdown mode, upon which the 120Ω NMOS
pull-down clears the SS voltage in preparation for retry.
SHORTLED Flag: The LT3952 provides an open-drain
SHORTLED pin to flag the overcurrent detection. This pin
is connected with a pull-up resistor to the user’s voltage
(up to 42V), and has a pull-down strength of 60Ω. Please
be aware of power dissipation and keep the pull-up current
to a few mA maximum.
The SHORTLED pull-down activates immediately upon
detection of a fault and stays on throughout the charge/
discharge phase of the hiccup cycle. The pull-down releases
as the SS capacitor is cleared to 0V during the restart
phase and stays released as SS re-charges to the 0.2V
retry threshold. If at this point a fault is again detected,
the pin is again pulled down as the hiccup retry cycle
continues. For the user detecting fault with an IRQ, this
falling edge is used to count a desired number of faults
before full system shutdown, or the rising edge is used
to prepare the system for a new start-up cycle.
Board Layout
The high speed operation of the LT3952 demands careful
attention to board layout and component placement. The
exposed pad of the package is the GND terminal of the
IC and is also important for thermal management of the
IC. It is crucial to achieve a good electrical and thermal
contact between the exposed pad and the ground place
of the board. To reduce electromagnetic interference
(EMI), it is important to minimize the area of the high dV/
dt switching node between the inductor, SW pins, and
anode of the Schottky rectifier.
Use a ground plane under the switching node to eliminate
interplane coupling to sensitive signals. The length of the
high dI/dt trace from the SW pin through the Schottky rectifier and filter capacitor to GND should be minimized, and the
IC GND pins should be connected to the large copper area
beneath the IC. The GND terminal of the INTVCC capacitor
should be placed near the GND of the switching path. The
ground for the VREF capacitor, the IVINCOMP capacitor,
the compensation network, and other DC control signals
should be star connected to the underside of the IC. Do
not route high impedance signals such as FB, DIM, IVINN,
RT and VC near the switching nodes, and minimize the
length of their routes to avoid picking up switching noise.
Since there is a small, but variable, DC bias current on
the ISP/ISN/IVINP/IVINN inputs, minimize resistance in
series with these pins to avoid creating an offset. Kelvin
connecting these lines to the terminals of their respective
sense resistors provides best performance.
3952fa
For more information www.linear.com/LT3952
25
LT3952
TYPICAL APPLICATIONS
Short-Circuit Robust Boost LED Driver with Spread Spectrum Frequency Modulation
4A INPUT LIMIT L1
10µH
15mΩ
VIN
7V TO 42V
D1
4.7µF
EN/UVLO
IVINN
VIN IVINP
2.2µF
100V
×2
SW
GND
OVLO
1M
FB
21.5k
INTVCC
CTRL
VREF
PWM
ISMON
DIM
PWM
ISMON
100k
LT3952
ISN
OPENLED
SHORTLED
VC
TG
INTVCC
IVINCOMP
8.2nF
Short LED Protection without RSS: Hiccup Mode
INTVCC
SYNC/SPRD
SS
RT
1µF
90.9k
1MHz
M1
16 LED (50V)
333mA
RSS
750k OPT
3.6k
D1: VISHAY VS-10BQ060
L1: WURTH WE-LHMI74437349100
M1: VISHAY Si7415DN
ISP
750mΩ
100k
OPENLED
SHORTLED
57V OPEN LED
REGULATION
2.2µF
100nF
3952 TA02a
Short LED Protection with RSS: Latchoff Mode
VLED
20V/DIV
VLED
20V/DIV
SS
2V/DIV
SS
2V/DIV
SHORTLED
2V/DIV
SHORTLED
2V/DIV
ILED
1A/DIV
100ms/DIV
3952 TA02b
ILED
1A/DIV
LED Current vs Input Voltage
100ms/DIV
37961 TA02c
Average Conducted EMI Comparison
350
80
SSFM OFF
SSFM ON
70
345
AMPLITUDE (dBµV)
LED CURRENT (mA)
60
340
335
330
50
40
30
20
325
320
26
10
0
10
20
30
VIN (V)
40
50
0
0
3952 TA02d
2
4
6
FREQUENCY (MHz)
8
10
3952 TA02e
3952fa
For more information www.linear.com/LT3952
LT3952
TYPICAL APPLICATIONS
SEPIC LED Driver with Input Current Limit
VIN
5V TO 35V
42V TRANSIENT
4V OVLO FALLING
36.5V UVLO RISING
•
100k
EN/UVLO
IVINN
VIN IVINP
OVLO
100k
LT3952
VC
D1: VISHAY VS-10BQ060
L1: WURTH WE-DD744874100
M1: VISHAY Si7309DN
ISP
ISN
OPENLED
SHORTLED
10nF
1M
620mΩ
100k
1k
SW
GND
4.7µF
35V
49.9k
CTRL
VREF
PWM
ISMON
DIM
OPENLED
SHORTLED
L1B
FB
4.75k
PWM
ISMON
D1
•
4.7µF
39.2k
INTVCC
2.2µF
100V
L1A
3A INPUT LIMIT
10µH
20mΩ
TG
INTVCC
IVINCOMP
1µF
INTVCC
SYNC/SPRD
SS
RT
90.9k
1MHz
6 LED (17V)
400mA
2.2µF
100nF
3952 TA03a
LED Current vs Input Voltage
SEPIC Efficiency vs Input Voltage
410
100
408
90
404
EFFICIENCY (%)
LED CURRENT (mA)
406
402
400
398
396
80
70
394
392
390
0
10
20
VIN (V)
30
40
60
0
3952 TA03b
10
20
VIN (V)
30
40
3952 TA03c
3952fa
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27
LT3952
TYPICAL APPLICATIONS
2MHz Boost LED Driver with 4000:1 PWM Dimming and Overvoltage Protection
3A INPUT LIMIT L1
3.3µH
20mΩ
VIN
7V TO 16V
40V TRANSIENT
6.1V UVLO FALLING
18.3V OVLO RISING
D1
4.7µF
143k
EN/UVLO
VIN IVINP
IVINN
OVLO
100k
12.1k
CTRL
VREF
PWM
ISMON
DIM
1.65Ω
ISN
OPENLED
SHORTLED
2.2k
D1: PMEG4010
L1: WURTH WE-LHMI 74437346033
M1: VISHAY Si7309DN
M1
TG
INTVCC
VC
IVINCOMP
10nF
26V OPEN LED
REGULATION
ISP
LT3952
100k
OPENLED
SHORTLED
249k
FB
12.1k
INTVCC
SW
GND
24.3k
PWM
ISMON
4.7µF
50V
1µF
RT
INTVCC
SYNC/SPRD
SS
37.4k
2.15MHz
8 LED (22V)
150mA
2.2µF
8.2nF
3952 TA04a
LED Current vs Input Voltage
Efficiency Over Working Range
100
154
153
EFFICIENCY (%)
LED CURRENT (mA)
90
152
151
150
80
70
149
148
6
8
10
12
VIN (V)
14
16
18
60
6
1.67µs 2.22µs
4000:1
10
12
VIN (V)
14
16
3952 TA04b
High PWM Dimming Ratio
PWM
1V/DIV
8
3000:1
18
3952 TA04c
LED Dead Short Response
3.33µs
2000:1
VLED
10V/DIV
SS
1V/DIV
ILED
50mA/DIV
SHORTLED
2V/DIV
400ns/DIV
28
3952 TA04d
20ms/DIV
3952 TA04e
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LT3952
TYPICAL APPLICATIONS
3MHz Buck-Boost LED Driver with Internal PWM Dimming and Fade Start
L1
2.5µH
15mΩ
VIN
5V TO 35V
42V TRANSIENT
39V OVLO RISING
4.7µF
50V
D1
4.7µF
1M
EN/UVLO
VIN IVINP
IVINN
OVLO
1µF
100V
SW
GND
31.6k
2.2µF
0.25s FADE
75k
39nF
130Hz
1M
FB
CTRL
VREF
DIM
21.5k
ISP
LT3952
PWM
57V LIMIT
8 LED
333mA
0.75Ω
ISN
INTVCC
100k
100k
OPENLED
SHORTLED
OPENLED
SHORTLED
2.4k
D1: VISHAY VS-10BQ060
L1: WURTH WE-LHMI74437346025
M1: VISHAY Si7309DN
10nF
TG
INTVCC
VC
IVINCOMP
1µF
Efficiency vs Input Voltage
INTVCC
SYNC/SPRD
SS
RT
25.5k
3MHz
3952 TA05a
2.2µF
100nF
PWM Duty Cycle and Efficiency vs DIM Voltage
100
PWM DUTY CYCLE
100
EFFICIENCY
80
PERCENT (%)
EFFICIENCY (%)
90
80
70
60
60
40
20
0
0
5
10
15
20
VIN (V)
25
30
35
VIN = 12V
0
0.5
1
1.5
DIM (V)
2
2.5
3952 TA05c
3952 TA05b
Power On – Fade Start
VIN
10V/DIV
VLED
10V/DIV
PWM
1V/DIV
ILED
200mA/DIV
40ms/DIV
3952 TA05d
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3952fa
29
LT3952
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3952#packaging for the most recent package drawings.
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev K)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 27 26 2524 23 22 21 20 1918 17 16 15
6.60 ±0.10
4.50 ±0.10
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
6.40
2.74
(.252)
(.108)
BSC
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
30
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP REV K 0913
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
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For more information www.linear.com/LT3952
LT3952
REVISION HISTORY
REV
DATE
DESCRIPTION
A
01/16
Replaced reference to Note 5 to Note 4 in Absolute Maximum Table
Removed Note 4 from INTVCC Dropout Voltage specification
Replaced Note 5 with Note 4
Clarified SS (Pin 19) description – replaced “shutdown mode” with “start-up mode”
Clarified the Block Diagram pin designators
Clarified Figure 11
Clarified Open LED Flag and Overvoltage section 60mV becomes 65mV
Clarifed LED Dead Short Response graph
Clarifed Power On – Fade Start graph
Clarifed Related Parts table
PAGE NUMBER
2
3
5
11
12
19
20
28
29
32
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LT3952
31
LT3952
TYPICAL APPLICATION
3A Buck Mode LED Driver
VIN
12V TO 40V
9.6V FALLING UVLO
82mΩ
1µF
50V
78.7k
VIN
EN/UVLO
ISP
ISN
12.4k
TG
IVINP
IVINN
OVLO
CTRL
VREF
PWM
DIM
PWM
M1
IVINCOMP
LT3952
D1
INTVCC
INTVCC
2.2µF
100k
OPENLED
SHORTLED
ISMON
VC
SS
220Ω
SHORTLED
6.8nF
D1: DIODES, INC SBR3A40SA
L1: WURTH WE-LHMI74437346047
M1: VISHAY Si7309DN
100nF
3 TO 9 LED
(3V TO 30V)
3A
L1
4.7µH
4.7µF
50V
SW
2× 4.7µF
50V
FB
GND
RT
SYNC/SPRD
90.9k
1MHz
3952 TA06a
LED Current vs Input Voltage
Efficiency vs VIN
3.25
100
90
3 LED
3.15
EFFICIENCY (%)
LED CURRENT (A)
3.20
3.10
3.05
80
70
3 LED (30W)
5 LED (50W)
7 LED (70W)
9 LED (90W)
3.00
2.95
10
20
30
VIN (V)
60
40
10
20
30
VIN (V)
3952 TA06b
40
3952 TA06c
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT3795
110V High Side LED Controller with Spread Spectrum
and Boost Short-Circuit Protection
VIN: 4.5V to 110V, VOUT(MAX) = 110V, PWM Dimming = 3000:1,
ISD < 10mA, TSSOP-28 Package
LT3518
2.3A, 2.5MHz High Current LED Driver with 3000:1
Dimming with PMOS Disconnect FET Driver
VIN: 3V to 30V, VOUT(MAX) = 45V, 3000:1 PWM Dimming, ISD < 1μA,
4mm × 4mm QFN-16 and TSSOP-16E Packages
LT3755/LT3755-1/ High Side 40V, 1MHz LED Controllers with True Color
LT3755-2
3000:1 PWM Dimming
VIN: 4.5V to 40V, VOUT(MAX) = 75V, 3000:1 PWM Dimming, ISD < 1μA,
3mm × 3mm QFN-16 and MSOP-16E Packages
LT3956
High Side 80V, 3.3A, 1MHz LED Driver with True Color
3000:1 PWM Dimming
VIN: 6V to 80V, VOUT(MAX) = 80V, PWM Dimming = 3000:1, ISD < 1μA,
5mm × 6mm QFN-36 Package
LT3761
High Side 80V, 1MHz LED Controller with 3000:1 PWM
Dimming and Internal PWM Generator
VIN: 4.5V to 60V, VOUT(MAX) = 80V, 3000:1 True Color PWM Dimming,
Analog, ISD < 1μA, MSOP-16E Package
LT3478/LT3478-1 4.5A, 2MHz High Current LED Drivers with 3000:1
Dimming
VIN: 2.8V to 36V, VOUT(MAX) = 40V, 3000:1 PWM Dimming, ISD < 1μA,
TSSOP-16E Package
LT3954
VIN: 4.5V to 40V, VOUT(MAX) = 40V, True Color PWM Dimming = 3000:1,
Analog, ISD < 1μA, 5mm × 6mm QFN-36 Package
32
High Side 40V, 5A 1MHz LED Driver with 3000:1 PWM
Dimming and Internal PWM Generator
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LT3952
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LT3952
LT 0116 REV A • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2015