PANASONIC AN8027

Voltage Regulators
AN8027, AN8037
AC-DC switching power supply control IC with standby mode
■ Overview
Unit: mm
2.4±0.25
3.3±0.25
7
6
0.5±0.1
8
5
30°
1.4±0.3
2
1
1.5±0.25
4
3
■ Features
2.54
9
1.5±0.25
6.0±0.3
23.3±0.3
The AN8027 and AN8037 are ICs developed for selfexcited switching regulator of RCC local resonance control type.
These ICs are designed to achieve stability and high
efficiency over a wide input voltage range and loads range
(light loads to heavy loads), for supporting input levels
used worldwide and improved conformance with energy
conservation laws.
• Support improved conformance with energy conservation laws by providing two operating modes.
0.3 +0.1
–0.05
• Standby mode (light loads):
3.0±0.3
Achieves better efficiency due to reduced frequency .
• Normal mode:
SIP009-P-0000C
Achieves high efficiency in RCC local resonance operation with zero-cross detection.
• Incorporating an input voltage compensation function available to a wide input range for worldwide use.
• This function compensates the maximum on-period in inverse proportion to the input voltage.
• Incorporating a timer latch function.
• The time period can be adjusted according to the overload in normal mode or standby mode.
• This function makes it possible to protect the IC from damage that may be caused by the short-circuiting of the IC's
external capacitor for the timer.
• Incorporating an overvoltage protection function. (detects at VCC pin)
• Incorporating a pulse-by-pulse overcurrent protection function, which makes latch protection possible at the time of
the short-circuiting of the transformer's primary winding.
• Adopting a 9-pin single inline package (E-9S: available to manufacturing in overseas).
• AN8027: Transformer resetting is detected from the high- or low-level signal on the TR pin.
• AN8037: Transformer resetting is detected from the falling edge of the high-level signal on the TR pin.
Refer to the "[1] operation descriptions 7. local resonance operation" section in the application notes.
■ Applications
• Televisions, VCRs, facsimiles, and printers
1
AN8027, AN8037
Voltage Regulators
7 V
CC
■ Block Diagram
3.8 V
OVP
S
R
(SD latch)
Q
SD 8
INIT
Start
Stop
VREF
7.1 V
Timer
0.5 V
Current
reviser (IFB)
Q
Q
Q Q
Q
High-side
clamp
OCP 2
In
In
Out
Drive
6 Out
5 GND
Q
VFB
I/V
conv.
FB 9
CF
latch
TON
TOFF
(0.7 V)
TR 1
High-side
clamp
Low-side
clamp
Current
reviser (ITR)
One
shot
0.35 V
4
R
1.0 V
CLM
− 0.2 V
Start
pulse
To timer
CF 3
(− 0.15 V)
Q
S
R
■ Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply voltage
VCC
24
V
Constant output current
IOUT
±150
mA
Peak output current
IOP
±1 000
mA
TR pin allowable application current
ITR
±5
mA
OCP pin allowable application voltage
VOCP
− 0.3 to +7.0
V
CLM pin allowable application voltage
VCLM
− 0.3 to +7.0
V
SD pin allowable application voltage
VSD
− 0.3 to +7.0
V
FB pin allowable application current
IFB
0 to −2.0
mA
Power dissipation (Ta ≤ 25°C)
PD
874
mW
454
mW
Topr
−30 to +85
°C
Tstg
−55 to +150
°C
Power dissipation (Ta = 85°C)
Operating ambient temperature
Storage
*
temperature *
Note) 1. *: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C.
2. Do not apply external currents or voltages to any pins not specifically mentioned.
For circuit current, '+' denotes current flowing into the IC, and '−' denotes current flowing out of the IC.
■ Recommended Operating Range
Parameter
Supply voltage
2
Symbol
Range
Unit
VCC
From the stop voltage to the OVP supply voltage
V
Voltage Regulators
AN8027, AN8037
■ Electrical Characteristics at VCC = 18 V, Ta = 25°C
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Low voltage protection (U.V.L.O.) VCC-START
initial startup supply voltage
13.4
14.9
16.4
V
Low voltage protection (U.V.L.O.) VCC-STOP
operation stop supply voltage
7.7
8.6
9.5
V
Overvoltage protection (OVP)
operating supply voltage
VCC-OVP
19.4
20.5
21.6
V
Overvoltage protection (SD)
operating threshold voltage
VTH1-SD
3.5
3.9
4.3
V
Overvoltage protection (SD)
reset threshold voltage
VTH2-SD
0.4
0.8
1.2
V
Remote (RM) operating
threshold voltage
VTH1-RM
0.05
0.15
0.3
V
Shutdown (SD) standby voltage
VSTB-SD
1.0
1.5
2.0
V
7.3
8.1
8.9
V
SD pin = Open
Overvoltage protection (OVP)
reset supply voltage
VCC-OVPC
Remote (RM) operating time
circuit current
ICC-RM
VCC = 18 V, VSD = 0 V
3.0
4.0
5.0
mA
Overvoltage protection (SD)
operating time circuit current 1
ICC1-SD
VCC = 10 V, VSD = 4.3 V → Open
1.2
1.5
1.8
mA
Overvoltage protection (SD)
operating time circuit current 2
ICC2-SD
VCC = 18 V, VSD = 4.3 V → Open
3.6
4.5
5.4
mA
Timer latch (SD) charge current 1
ISD1-TIM
FB pin = Open, ITR = −270 µA
68
102
136
µA
Timer latch (SD) charge current 2
ISD2-TIM
FB pin = Open, ITR = −1.64 mA
179
267
355
µA
Timer latch (SD) start feedback
current
IFB-TIM
ITR = −1 mA, ROCP = 30 kΩ
Transformer reset detection (TR)
threshold voltage
VTH-TR
Transformer reset detection (TR)
upper limit clamp voltage
VCLH-TR
Transformer reset detection (TR)
lower limit clamp voltage
VCLL-TR
Overcurrent protection (CLM)
threshold voltage
VTH-CLM
− 0.95 − 0.75 − 0.55
mA
0.15
0.25
0.35
V
ITR = 3 mA
0.55
0.7
0.85
V
ITR = −3 mA
− 0.3 − 0.15
0
V
−220
−200
−180
mV
Oscillator (CF) upper limit voltage
VH-CF
FB pin = Open, CF = 2 200 pF
3.8
4.2
4.6
V
Oscillator (CF) lower limit voltage 1
VL1-CF
FB pin = Open, CF = 2 200 pF
0.8
1.0
1.2
V
Oscillator (CF) lower limit voltage 2
VL2-CF
IFB = − 0.5 mA, CF = 2 200 pF
0
0.1
0.3
V
Oscillator (CF) maximum
on-period current gain
GION-CF
FB pin = Open, ITR = −750 µA
0.8
1.0
1.2

Oscillator (CF) maximum
on-period current
ION-CF
ITR = 0 mA
200
250
300
µA
Oscillator (CF) minmum
off-period current 1
IOFF1-CF
IFB = − 0.4 mA
−880
−660
−440
µA
3
AN8027, AN8037
Voltage Regulators
■ Electrical Characteristics at VCC = 18 V, Ta = 25°C (continued)
Parameter
Symbol
Conditions
IFB = − 0.8 mA
Min
Typ
Max
Unit
−210
−160
−110
µA
Oscillator (CF) minmum
off-period current 2
IOFF2-CF
Minimun off-period threshold
feedback current
IFB-TOFF
− 0.78 − 0.6 − 0.42
mA
Overcurrent protection (OCP) pin
source current
IOCP-OCP
−130
−100
−70
µA
CF = 2 200 pF, ITR = 475 µA,
IFB = − 0.5 mA
50
65
80
kHz
Pre-startup low-level output voltage VOL-STB
VCC = 13.5 V, IOUT = 1 mA

1.0
1.25
V
Low-level output voltage
VOL
IOUT = 0.1 A

0.9
2.0
V
High-lebel output voltage
VOH
IOUT = − 0.1 A
15.5
16.3

V
Pre-startup circuit current 1
ICC-STB1
VCC = 13.5 V
75
100
125
µA
Circuit current 1
ICC1-OPR1 VCC = 10 V
8.5
11.5
14.5
mA
Circuit current 2
ICC2-OPR2 VCC = 18 V
9.0
12.0
15.0
mA

200
380
µA
Output oscillator frequency
Circuit current durring startup 1
FOSC
ISTART1
• Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Low voltage protection (U.V.L.O.)
start/stop supply voltage difference
Conditions
Min
Typ
Max
Unit
∆VCC

6.3

V
Remote (RM) reset threshold voltage
VTH2-RM

0.1

V
Timer latch (SD) overcurrent
protection time
TCLM-SD

0.1

s
Transformer reset detection (TR)
threshold hysteresis width
∆VTH-TR

0.05

V
Maximum on-period
TON(max)
ITR = 0 mA, IFB = − 0.2 mA

26.5

µs
Minimum off-period
TOFF(min)
ITR = 0 mA, IFB = − 0.2 mA

5

µs
Overcurrent protection (OCP)
power-on charge period
TSD(ON)-OCP IFB = − 0.5 mA, ROCP = 22 kΩ

1.8

µs
Overcurrent protection (OCP)
power-off charge period
TSD(OFF)-OCP IFB = − 0.5 mA, ROCP = 30 kΩ

8.8

µs
Output rise time
tr
10% to 90%, IOUT = 0 mA

60

ns
Output fall time
tf
10% to 90%, IOUT = 0 mA

20

ns
TTR

800

ns
CLM output response time
TCLM

100

ns
Pre-startup circuit current 2
ICC-STB2
50
100
150
µA

100

µs
TR output response time
VCC = 13.5 V,
Ta = −30°C to +85°C
Only for AN8037
Timer period during startup
4
TSTART
Voltage Regulators
AN8027, AN8037
■ Pin Descriptions
Pin No. Pin name
1
2
3
TR
OCP
CF
I/O
Explanation
I
Transformer reset detection input. When the
IC detects transformer resetting and the falling edge of a high-level signal is input to
this pin of the AN8037 or a low-level signal
is input to the same pin of the AN8027, the
level of the Out pin becomes high. However,
the transformer reset signal is ignored if the
signal is shorter than the minimum off-period determined by the CF pin. Also note
that the maximum on-period is corrected according to the source currents.


Connection for the resistor that determines
the overload level of the IC to activate the
timer latch protection circuit.
By judging the operating mode (i.e., the normal or standby mode) of the IC from the
secondary side, the timer period is adjusted
with the selection of external resistance according to the operating mode.
Connection for the capacitor that determines
the on- and off-periods of the IC output (Out).
The on- and off-periods are corrected by ION
which is proportional to the flowing out current at the TR pin, and IOFF which corresponds to the current at FB pin.
Equivalent Circuit
VREF
1
High-side Low-side
clamp clamp
VREF
Comp.
CF
2
VREF
IOFF
Comp.
VFB
ION
3
4
5
CLM
GND
I

Input to the pulse-by-pulse overcurrent protection circuit.
Normally, we recommend adding an external
filter for this input. If overcurrent continues
for several cycles, the IC determines that the
operation is erroneous, thus triggering the
latch protection function.
VREF
Comp.
CLM(−) 4
IC ground.
5
5
AN8027, AN8037
Voltage Regulators
■ Pin Descriptions (continued)
Pin No. Pin name
6
7
8
9
Out
VCC
SD
FB
I/O
Explanation
O
Output used to directly drive a power MOSFET.
A totem pole structure is adopted in this
output circuit.
The absolute maximum ratings for the output
current are:
Peak: ±1 A
DC: ±150 mA

I
I
Equivalent Circuit
VCC
6
Power supply.
This pin monitors supply voltage and has the
threshold for the start, stop, OVP, and OVP
reset levels.
This pin is used in RM (remote), OVP (overvoltage protection), and timer latch.
RM:
The IC is in remote operation if this pin is
short-circuited to the ground and the output
of the IC is turned off.
OVP:
When overvoltage signal of the power supply is detected and high is inputted to the terminal, it turns off the internal circuit. At the
same time, it holds that condition (latch).
Timer latch:
It detects the output voltage fall due to the
overcurrent condition of the power supply
output through the current level inputted to
FB. When the IFB decreases under the current
of certain value, the charge current flows in
the capacitor which is connected to this terminal. Then, when the capacitor is charged
up to the threshold voltage of the OVP, the
OVP works so that the IC could keep the operation stop condition.
Connection for the photocoupler used for the
power supply output error-voltage feedback.
This input can decrease the photocoupler dark
current by about 200 µA.
7
VCC
OVP
3.9 V
Comp.
RM
ITIM
8
0.1 V
Comp.
25 µA
VREF
VFB
IFB 9
6
Voltage Regulators
AN8027, AN8037
■ Application Notes
[1] Operation descriptions
1. Start/stop circuit block
• Startup mechanism
After the AC voltage is applied and the
supply voltage due to the current in the startup
resistor reaches the startup voltage and the IC
begins to operate, drive of the power MOSFET
begins. This causes a bias in the transformer, and
the supply voltage is provided to the IC from
the bias winding. (This is point a in figure 1.)
During the period between the point when the
startup voltage is reached, and the point when
the bias winding can generate a voltage enough
to supply the IC, the IC supply voltage is provided by the capacitor (C8) connected to VCC.
Since the supply voltage falls during this period
(area b in figure 1), if the supply voltage falls
below the IC stop-voltage before an adequate
supply voltage can be provided by the bias winding, it will not be possible to start the power supply. (This is the state at point c in figure 1.)
Rectified AC
Startup resistor
R1
VCC
C8
VOUT
GND
Standby
Startup
voltage
Stop
voltage
Startup
Voltage supplied
from bias winding
a
Startup state
b
c Startup failure
Figure 1
• Functions
This IC includes a function that monitors the VCC voltage. It starts IC operation when VCC reaches the startup
voltage (14.9 V typical), and stops operation when the voltage falls below the stop voltage (8.6 V typical). Since
a large voltage difference (6.3 V typical) is taken between the start and stop voltages, it is easy to select values for
the start resistor and the capacitor connected to VCC .
Note) To start up the IC operation, the startup current which is a pre-start current plus a circuit drive current is necessary.
Set the resistance value so as to supply a startup current of 400 µA.
2. Oscillation circuit
The oscillation circuit makes use of the charge and discharge of current to and from the capacitor CCF connected
to the CF pin (pin 3) to determine the switching timing of the power MOSFET.
The IC is in constant voltage control by changing the on-period of the power MOSFET without making offperiod change while the IC is in normal (RCC continuous) operation mode. At that time, the on-period is controlled by directly changing the output pulse width of the oscillation circuit, and the maximum on-period can be
adjusted with input voltage compensation by detecting the input voltage with the flow of current from the TR pin
(TR source current). Refer to figure 2. When the IC is in standby mode (for light loads), the stable, efficient
control of the IC is ensured by detecting the flow of current from the FB pin (IFB) and changing the off-period for
a decrease in frequency. Refer to figure 3.
The following provides information on how to set on- and off-period.
• Setting the on-period
The output on-period is the discharge period when the CF pin is between the peak value oft VH-CF = 4 V
(typical) and VFB .
An approximate on-period of the power MOSFET is obtained from the following formula. Refer to figure 2.
TON = CCF × (VH-CF − VFB)/ION
whereas, VH-CF = 4 V typ.
ION = ITR + 250 µA typ.
ITR = (EIN × NB/NP − VZ)/RTR
VFB = 0.7 V typ. (IFB ≤ 200 µA)
VFB = 4 kΩ × IFB typ. (IFB > 200 µA)
7
AN8027, AN8037
Voltage Regulators
■ Application Notes (continued)
[1] Operation descriptions (continued)
2. Oscillation circuit (continued)
• Setting the on-period (continued)
TON : On-period
CCF : Value of a capacitor connected to CF pin
VFB : Voltage internally converted from feedback signal IFB
VH-CF : CF upper limit voltage
ION : On-period discharge current
ITR : Flowing current at TR pin
EIN : Voltage on primary winding
NB : Number of turns in the bias winding
NP : Number of turns in the primary winding
VZ : Voltage on Zener diode connected to bias winding
RTR : Value of a resistor connected to the TR pin
The power MOSFET is turned off if the voltage at the CLM pin reaches the pulse-by-pulse overcurrent
protection threshold voltage (i.e., −200 mV typical) when the overcurrent protection function of the IC is
operating.
TON is shortened
NP
EIN+
because large EIN
increases ITR.
ITR
RTR
Current mirror
IFB
ITR=ION
Current mirror
1:5
FB
ION
VFB
250 µA
typ.
20 kΩ
The minimum current is guaranteed
to prevent a limitless increase in TON .
Out
GND
CF
PC
NB
VCC
AN8027, AN8037
TR
VZ
EIN−
CCF
EIN; large
ITR(ION); large
VH-CF = 4 V
CF pin voltage
VFB
0V
VCC − 1.5 V
Out pin voltage
Off
On
0V
Figure 2. On-period block diagram and control waveform
The maximum on-period can be used for overcurrent protection.
When the input voltage is low, the maximum on-period overcurrent protection is possible.
When the input voltage is high, the CLM pulse-by-pulse overcurrent protection is possible.
8
Voltage Regulators
AN8027, AN8037
■ Application Notes (continued)
[1] Operation descriptions (continued)
2. Oscillation circuit (continued)
• Setting the off-period
The minimum off-period is the charge period from VL-CF = 0.2 V (typical) to VTH(OFF) or VFB .
An approximate minimum off-period of the power MOSFET is obtained from the following formula.
Refer to figure 3.
TOFF(min) = CCF × VTH(OFF) /IOFF1 (IFB ≤ 0.6 mA)
= {CCF × VTH(OFF) / IOFF1} + {CCF × (VFB − VTH(OFF)) / IOFF2} (IFB > 0.6 mA)
VTH(OFF) = 2.4 V typ.
IOFF1 = 660 µA typ.
IOFF2 = 160 µA typ.
TOFF(min) : Minimum off-period
CCF
: Value of a capacitor connected to the CF pin
VFB
: Voltage internally converted from feedback signal IFB
VTH(OFF) : Threshold voltage of VFB to extend off-period
IOFF1
: Charge current until CF pin voltage increases from 0.2 V to 2.4 V
IOFF2
: Charge current until CF pin voltage increases from 2.4 V to VFB
When the IC is in local resonance operation, the off-period is determined by the longer one of either the
time required for the input voltage on the TR pin to drop below the threshold voltage or the minimum offperiod (TOFF(min)) specified by the CCF.
Thus the power MOSFET is in continuous on/off operation.
EIN+
NB
VCC
AN8027, AN8037
NP
Current mirror
PC
FB
1:5
= 660 µA typ.
I
IOFF
VFB (IOFF < 0.6 mA)
FB
IOFF = 160 µA typ.
(IFB > 0.6 mA)
Out
GND
CF
20 kΩ
CCF
VH−CF = 4 V
IFB < 0.6 mA
VH−CF = 4V
CF pin voltage
CF pin voltage
VTH(OFF) = 2.4 V
VFB
VL2−CF = 0.2 V
0V
VCC − 1.5 V
VCC − 1.5 V
TOFF(min)
On
Out pin voltage
IFB; large
TOFF(min); large
TOFF(min)
On
TOFF
TOFF
0V
VFB
VTH(OFF) = 2.4 V
VL2−CF = 0.2 V
0V
Out pin voltage
IFB > 0.6 mA
0V
Figure 3. Off-period block diagram and control waveform
9
AN8027, AN8037
Voltage Regulators
■ Application Notes (continued)
[1] Operation descriptions (continued)
3. Control waveform timing chart
1) Normal (RCC contiuous) operation mode
0V
(A)Voltage on bias winding
Off
(B)TR pin voltage
On
Off
On
On
Off
Off
0V
Input voltage correction
EIN; large
TON; short
4V
VFB voltage
(C)CF pin voltage
2.4 V
IFB correction
VFB; large
TOFF(min); long
0V
VCC − 1.5 V
(D)Out pin voltage
Off
On
Off
On
Off
On
Off
0V
Current on
bias winding
(E)Current
on primary
winding
(F)Current
on secondary
winding
0A
Heavy
Light
Load
<Circuit diagram>
(E)
(B)
TR
VCC
AN8027, AN8037 Out
CLM
CF
(A)
(D)
(C)
(G)
10
(F)
Voltage Regulators
AN8027, AN8037
■ Application Notes (continued)
[1] Operation descriptions (continued)
3. Control waveform timing chart (continued)
2) Standby (Intermittent) mode (for light loads)
On
0V
(A)Voltage on bias winding
(B)TR pin voltage
Off
Off
0V
Off
TON is acceptable
only after CF pin
voltage reaches 4 V.
4V
VFB voltage
2.4 V
TON is unacceptable
during TOFF(min) period.
TOFF(min)
(C)CF pin voltage
T(OFF)
0V
On
On
(D)Out pin voltage
Off
Off
Off
0V
(E)Current
on primary
winding
Current on
bias winding
(F)Current
on secondary
winding
0A
<Circuit diagram>
(E)
(B)
TR
VCC
AN8027, AN8037 Out
CLM
CF
(F)
(A)
(D)
(C)
(G)
11
AN8027, AN8037
Voltage Regulators
■ Application Notes (continued)
[1] Operation descriptions (continued)
3. Control waveform timing chart (continued)
3) Pulse-by-pulse overcurrent protection (CLM) operation
0V
(A)Voltage on bias winding
(B)TR pin voltage
Off
On
Off
On
Off
On
Off
On
On
Off
On
Off
On
Off
0V
(E) Current on primary
winding
0A
0V
(H)CLM pin voltage
− 0.2 V
CLM threshold voltage
4V
(C)CF pin voltage
2.4 V
VFB voltage
0V
VCC − 1.5 V
(D)Out pin voltage
Off
On
Off
0A
<Circuit diagram>
(E)
(B)
TR
VCC
AN8027, AN8037 Out
CLM
CF
(A)
(D)
(C)
(G)
12
(F)
Off
Voltage Regulators
AN8027, AN8037
■ Application Notes (continued)
[1] Operation descriptions (continued)
4. Power supply output control system (IFB: feedback)
Constant-voltage control of the power supply output is performed by changing the on- and off-period of the
power MOSFET. The on- and off-period are controlled with the photocoupler connected to the FB pin (Pin 9). The
photocoupler adjusts the current at the FB pin according to the signal that is output from the output voltage detection
circuit on the secondary side and changes the VFB voltage. Refer to figure 4.
The higher the AC input voltage is and the lower the load current is, the higher the current flow from FB pin,
the higher the VFB voltage, and the shorter the on-period (or longer the off-period in standby mode) will be.
Note that a current cancellation capacity of about 200 µA is provided to compensate for the dark current of the
photocoupler. Refer to figure 5.
AN8027, AN8037
7.1 V
1:5
Power output on
secondary side
200 µA typ.
PC
A minimum of 1 mA
is required for biasing
the AN1431T/M.
VFB
20 kΩ
Soft start current
is discharged
when the IC is
not in operation.
9
FB
AN1431T/M
PC
Primary side
Secondary side
Figure 4. Power output control
VFB
(V)
5
4
3
2
Dark current
1
0
0
− 0.2
− 0.4
− 0.6
− 0.8
−1.0
IFB (mA)
Figure 5. Feedback current vs. VFB characteristics
5. Soft start
When a power supply is started, it starts up in an overload state due to the capacitor connected to the power
supply output. At that moment, the output voltage is low. Therefore, the IC in usual voltage regulation tries to start
up the power output circuit at a maximum duty cycle. Although the IC tries to limit the current by the pulse-bypulse overcurrent protection at the CLM pin, the pulses cannot be suppressed to zero due to delays caused by the
filter. As a result, high current flows to the main switch (i.e., power MOSFET) and to the diode on the secondary
side. Therefore, in the worst case, these components are totally broken. To prevent this, soft start is used to
suppress inrush currents at power supply startup.
13
AN8027, AN8037
Voltage Regulators
■ Application Notes (continued)
[1] Operation descriptions (continued)
5. Soft start (continued)
As shown in figure 6, connect R3 and C4 between the
FB pin (Pin 9) and GND pin (Pin 5) so that the switching
regulator will be in soft start operation. When the voltage
supplied to the IC reaches the start voltage and the operation of the startup circuit begins, an open bias voltage of
approximately 6.4 V is output to the FB pin. As a result,
the charge current IFB flows into C4 from the FB pin. Then
the switching regulator starts up at high VFB, thus performing output control while the TON period is short. The
voltage difference between both edges of C4 rises according to the time constant determined by R3 and C4, thus
decreasing IFB with the lapse of time and increasing the
TON period gradually.
The above operation increases the flow of current to
the power MOSFET gradually after the switching regulator is turned on, thus suppressing the inrush current. However, this reduces the transient response of the feedback
loop, so care is required in designing this circuit.
Rectified AC
Startup resistor
R1
AN8027, AN8037
VCC
C8
FB
PC1
R3
C4
Out
CLM
GND
R8 C6
R7
To AC −
Figure 6
• Notes on selecting R3
The oscillation circuit of this IC is designed under the condition that the TON period is definite. If excessively
low resistance value for R3 is selected, the slope of the triangular wave on the CF pin immediately after the
startup may become extremely steep, leading to malfunction of the oscillation circuit. Accordingly, we recommend that you adjust R3 so that the drive pulse width t1 immediately after the startup is 0.5 ms or greater.
(Refer to figure 7.)
Note that the drive pulse width t1 depends on the capacitance value of the CCF that is connected to the CF
pin (Pin 3). Figure 8 indicates recommended values of R3 corresponding to the capacitance value CCF.
(In actual mounting conditions, the correlation shown in figure 8 may deviate slightly.)
t1
3 000
CF capacitance (pF)
VOUT
(Pin 6)
VCC = 16 V
C4 = 0.033 µF
2 000
1 000
CF
(Pin 3)
0
10
12
14
16
R3 (kΩ)
Start
14
Figure 7
Figure 8
18
20
22
Voltage Regulators
AN8027, AN8037
■ Application Notes (continued)
[1] Operation descriptions (continued)
5. Soft start (continued)
• Effective period for the soft start
The effective period for the soft start with the connection of R3 and C4 to the FB pin is approximately
calculated by the following formula.
[Approximate formula]
tSS = R3 × C4 (s)
It is thought that the effectiveness of the above formula is weakened because of the following reason:
The voltage difference between both ends of C4 rises up to 63% of the voltage at the FB pin within the time
constant τ (= R3 × C4), resulting in decrease of the charge current IFB, although it depends on the value of R3.
Note that if you increase the capacitance value of C4 unnecessarily, it would decrease the sensitivity of the
feedback by the photocoupler.
• Soft start at the re-startup
This IC includes a discharge circuit to instantly discharge charged electrons in the capacitor connected to
the FB pin in order to ensure the soft start at the re-startup.
Conditions for the operation of the discharge circuit are as follows:
1) VCC has become the stop voltage or below. (at the normal operation)
2) VCC has become the OVP reset threshold voltage or below. (at the OVP operation)
6. Notes on the feedback control
If the IC output pin (pin 6) falls to a negative voltage lower than that of the GND pin,
the startup operation may fail or the output oscillation may become unstable.
ICs in general, not just this IC, do not respond well when
negative voltages lower than the ground level are applied to
their pins. (Except for special applications.) This is because
parasitic device operations may be induced when negative voltages are applied due to the structure of ICs themselves.
In the case mentioned above, when the IC output (VOUT)
is turned off, the power MOSFET drain-to-source voltage,
VDS, jumps from a low voltage to a high voltage. The voltage
chattering that occurs at this time is superposed on VOUT
through the parasitic capacitance Cgd between the power
MOSFET gate and drain, and generates a negative voltage
with respect to the pin. No problems occur if the peak voltage, Vex, of this negative voltage does not exceed the parasitic device conduction voltage (about − 0.7 V).
However, the amplitude of the chattering is larger for
higher input voltages and for larger leakage inductance in the
transformer used. Also, the influence of this phenomenon becomes more noticeable for the larger Cgd of the power
MOSFET used, and the Vex peak value also increases. If the
parasitic device conduction voltage is exceeded, then, in this
IC, the parts of the circuit around the feedback circuit (FB)
(in particular, the FB discharge circuit) are influenced. This
can cause momentary drops in the FB pin voltage (the control
voltage), and as a result increase the FB current IFB and thus
does not allow the drive pulse on-period TON to be increased.
It may also prevent stabilization of the circuit. These are symptoms of the case described here. (Refer to figures 9 and 10.)
Rectified AC
FB
Cgd
VDS
Out
GND
Figure 9
VDS
VOUT
GND
Vex
FB
Control
voltage
Figure 10
15
AN8027, AN8037
Voltage Regulators
■ Application Notes (continued)
[1] Operation descriptions (continued)
6. Notes on the feedback control (continued)
[Countermeasures]
If an application exhibits the symptoms of the case described above, or similar symptoms, first insert a Schottky
barrier diode between VOUT and GND. It is not possible to completely remove the mechanism described above from
a power supply system. It is also not possible to prevent levels from being pulled down to negative voltages in the
control IC itself. Therefore, the most important point in designing countermeasures is to prevent such negative
voltages from reaching the parasitic device conductance voltage.
Note) If a Schottky barrier diode is added to the circuit and the condition improves initially but the symptoms reappear when
the input voltage or other parameter is increased, try replacing the Schottky barrier diode with one that has a larger
forward current (both peak and average values). The current capacity of the Schottky barrier diode is sometime
insufficient.
(Reference)
The following our Schottky diodes are available.
Part No.
Reverse voltage
Forward current (average)
Forward current (peak)
MA2C700A (MA700A*)
30 V
30 mA
150 mA
MA2C723 (MA723*)
30 V
200 mA
300 mA
MA2C719 (MA719*)
40 V
500 mA
1A
Note) *: Former part number
7. Local resonance operation (power MOSFET turn-on delay circuit)
Local resonance operation by using the AN8027 or AN8037 is possible with circuits as shown in figure 13.
C7 is the resonance capacitor, and R9 and C9 form a delay circuit for adjusting the power MOSFET turn on time.
When the power MOSFET is off, the voltage that occurs in the drive winding is input to the TR pin (pin 1)
through R9 and C9. The power MOSFET will be held in the off state while a high level (a level higher than the
threshold voltage, which is 0.25 V typical) is input to the TR pin.
The TR pin also has a clamping capability for upper and lower limit voltages. The upper limit voltage is clamped
at 0.7 V (typical) (sink current: −3 mA), and the lower limit voltage is clamped at about − 0.15 V typical (source
current: 3 mA). (Refer to figure 11.)
The power MOSFET off-period is determined by the longer period of the following two periods: the period
until the TR pin input voltage becomes lower than the threshold voltage as the bias winding voltage falls after the
transformer discharges its energy, and the minimum off-period (TOFF(min)) stipulated by the internal oscillator.
(Refer to the "Setting the off-period" section in the "Operating descriptions, 2. Oscillation circuit.") As a result,
ringing in the bias winding does not be regarded as a turn on signal during the minimum off-period.
16
Voltage Regulators
AN8027, AN8037
■ Application Notes (continued)
[1] Operation descriptions (continued)
7. Local resonance operation (power MOSFET turn-on delay circuit) (continued)
AN8027, AN8037
Not acceptable during
TON and TOFF(min) periods.
Transformer resetting
comparator
VCC
DB
TR
RTR
NB
Lower limit clamp
− 0.15 V typ.
One shot
(AN8037 only)
0.25 V typ.
Adjust so that the
current will be ±3 mA.
Upper limit clamp
0.7 V typ.
Lower limit
clamp current
GND
Upper limit clamp current
• Bottom-on function (AN8037 only)
A one-shot pulse is generated at the moment the signal level on the TR pin switched
to low level from high level reaches 0.25 V (typical) after the turn-on signal is received.
Refer to the next section for details.
Figure 11
8. Bottom-on function (AN8037 only)
Unlike the AN8027 or our conventional AN8026, AN8028, or AN8029 IC, which detects transformer resetting
with the high or low level in comparison to the threshold voltage on the TR pin, the AN8037 detects transformer
resetting on the falling edge across the threshold voltage.
This ensures the reliable local resonance operation of the IC regardless of input voltage fluctuations in a wide
input range for worldwide use, thus eliminating difficulty in turning on the power MOSFET when VDS is close to
the minimum value. Refer to figure 12.
tpd
Transformer resetting
tpd
detected on falling edge.
VP
VDS
VDS
VP
VIN
VIN
0V
VTR
0V
VTR
VTR 0.7 V typ.
0.25 V
0.25 V
0V
0V
ID
VTR 0.7 V typ.
ID
0V
0V
Input voltage; Low
Input voltage; High
Figure 12
17
AN8027, AN8037
Voltage Regulators
■ Application Notes (continued)
[1] Operation descriptions (continued)
8. Bottom-on function (AN8037 only) (continued)
Select the constants of R9 and C9 to determine the turn-on delay time so that the power MOSFET will be turned
on at a frequency of half the resonant frequency. Practically, refer to figure 12 and determine the turn-on delay
time so that the power MOSFET will be turned on at VDS = 0 V. The approximate resonant frequency can be obtained
from the following formula.
1
C: resonant capacitance
fSYNC =
[Hz]
2π √L · C
L: inductance of primary winding of transformer
The turn-on delay time tpd(ON) to turn on the power MOSFET at a frequency of half the resonant frequency is,
therefore, as follows.
tpd(ON) = π √L · C [s]
Note that since insertion of the resonance capacitor results in increased losses, using the parasitic capacitance
of the power MOSFET itself should also be considered. However, in this case the sample-to-sample variations
and temperature variations should be considered.
9. Notes on R9 and C9 value selection
If an excessively low value is used for R9, the current flowing into the TR pin after power supply startup will
exceed the maximum rating for the IC, and incorrect operation (in the worst case, destruction of the device) may
occur. We recommend using a value of R9 in the range that satisfies the following conditions.
VB(−) − The TR lower limit clamp voltage (− 0.15 V typical) ≥ −3 mA
R9
VB(−): negative peak voltage
VB(+) − The TR upper limit clamp voltage (1.5 V typical) ≤ 3 mA
R9
VB(+): positive peak voltage
Adjust tPD(ON) with C9 by taking the inductance and resonant capacitance of the transformer into consideration.
tpd
VIN
Rectified AC
VP
VDS
R1
VP
7 VCC
VIN
0V
C8
R9 VB
VTR
1 TR
SBD
VTR 0.7 V typ.
0.25 V
C9
0V
ID
6 Out
C7
SBD
ID
R7
To AC −
0V
Figure 13
18
Figure 14
Voltage Regulators
AN8027, AN8037
■ Application Notes (continued)
[1] Operation descriptions (continued)
10. Output block
This IC adopts a totem pole (push-pull) structure output circuit in which NPN transistors as shown in figure
15 sinks and sources current to rapidly drive the power MOSFET which is a capacitive load.
This circuit provides maximum sink and source currents of ±0.1 A (DC), and peak currents of ±1.0 A.
Furthermore, this circuit has a sink capability of 1 mA (typical) even when the supply voltage has fallen under the
stop voltage, and thus can turn off the power MOSFET reliably.
The main requirement on the control IC in this type of power supply is the ability to provide a large peak current.
That is to say, a high average current is not required in steady state operation. This is because the power MOSFET
is a capacitive load, and while a large peak current is required to drive such a load rapidly, once the load has been
charged or discharged a much smaller current suffices to retain that state.
This IC has a guaranteed peak current capability of ±1 A, values which were determined by considering the
capacitance of the power MOSFETs that will be used.
The parasitic inductance and capacitance of the power
MOSFET can cause ringing, and pull down the output
pin below the ground level. If the output pin goes to a
negative voltage that is larger than the voltage drop of the
diode, this state can turn on the parasitic diode formed by
Schottky barrier diode
the collector of the output NPN transistor and the substrate. Insert a Schottky barrier diode between the output
and ground if this is a problem. (Refer to figure 15.)
Figure 15
11. Timer latch
The pulse-by-pulse overcurrent protection function by itself cannot fully protect the transformer, the first recovery
diode or Schottky diode on the secondary side, or the power MOSFET, if the power output is overloaded or shortcircuited for a certain period. If the overcurrent state continues for a certain period or longer time, the timer latch
function makes it possible to interrupt the IC in a certain period by charging the capacitor connected to the SD pin.
The overload of the power output or short-circuiting of the power output is monitored as a voltage drop in power
output, at which time the pulse-by-pulse overcurrent protection is in operation. The voltage drop in power output is
detected as a decrease in current through the FB current feedback pin (pin 9). If this current is less than a certain value,
the on-chip comparator of the IC is in inverted operation to provide constant current to the SD pin. Refer to figure 16.
Then external capacitor connected to the SD pin is charged and the voltage on the SD pin rises to the SD
operating threshold voltage (i.e., 3.9 V typical), overvoltage protection (OVP) is triggered, and the operation of
the IC is suspended. Refer to figure 17.
Input voltage correction: Voltage input is detected
from the flow of current from the TR pin.
ISD = 1 × ITR + 70 µA, n ≈ 8.4
n
AN8027, AN8037
VCC
DB
ISD
Latch
OVP
Shutdown
VOVP
3.9 V typ.
Timer capacitor
discharging conditions
VCC < U.V.L.O. stop voltage
VCC < OVP reset voltage
On
SD
Overcurrent
detection
VOCP > VFB
FB
NB
The pin voltage rises by
charging the timer to trigger OVP.
Discharging
IFB
PC
Charging
ITIM
CTIM
Timer capacitor
discharging transistor
On
GND
The timer period is set according to the capacitance.
Figure 16
19
AN8027, AN8037
Voltage Regulators
■ Application Notes (continued)
[1] Operation descriptions (continued)
11. Timer latch (continued)
VO
Power supply
stop
Power supply
output voltage
0
Time
Power supply
stop
IDS
Power MOSFET
current
0
Time
VSD
VTH1−SD
Power supply
stop
SD
= 3.8 V typ.
SD pin voltage
Time
0
Figure 17. Basic timer latch operation
12. Setting the timer period
The period between the detection of the erroneous power output and the moment OVP is triggered (hereinafter
called timer period) needs to be longer than the rise time of the power supply. Since at operation start the IC is in
the same condition as the overload or output short-circuit condition, if the timer period is shorter, the power
supply works latch and can not start.
Therefore, the IC has a design making it possible to adjust the timer period with the external capacitor connected
to the SD pin. Make sure, however, that the capacitor is not too high, otherwise the power supply may be damaged.
Charge current is provided from the SD pin within
a period when the voltage on the CF pin satisfies the
following condition during the on-period.
CF pin voltage
VOCP ≥ VCF ≥ VFB
OCP pin voltage
VOCP = 2.2 V typ. V
FB
(ROCP = 22 kΩ)
Out pin voltage
Off
On
Timer period input voltage correction
Cycle T
SD pin charge current
ISD
EIN; large
ISD; large
Input voltage is detected from the flow of current from the TR pin.
ISD = 1 × ITR + 70 µA, n ≈ 8.4
n
Figure 18
20
Voltage Regulators
AN8027, AN8037
■ Application Notes (continued)
[1] Operation descriptions (continued)
12. Setting the timer period (continued)
Timer period (TTIM) is obtained from the following formula.
TTIM(S) = {CSD × (VTH1-SD − VSTB-SD)}/ISD(AVE)
VTH1-SD = 3.9 V typ.
CSD
: Capacitor connected to SD pin
VSTB-SD = 1.6 V typ.
VTH1-SD : Shutdown operating threshold voltage 3.9 V typ.
ISD(AVE) = ISD × TSD /T
VSTB-SD : Shutdown standby voltage 1.5 V typ.
TSD = CCF × (VOCP − VFB)/ION
ISD
: Timer latch charge current
TSD = CCF × (VOCP − VFB)/ION
TSD
: Timer latch charge period
T
: Cycle
CCF
: Capacitor connected to CF pin
VOCP : OCP pin voltage = ROCP × 100 µA typ.
VFB
: Voltage internally converted from feedback signal IFB
I
= FB × 20 kΩ + VBE
5
I
ION
: On-period charge current = 250 µA typ. × TR
4
By detecting the overload level on the secondary side from IFB and changing TSD , the timer period can be
adjusted according to the overload level. Furthermore, in the application circuit, the timer period can be adjusted
in both standby and normal modes. To enable this, let the microcomputer on the secondary side detect the operating mode (i.e., either the standby or normal mode) of the IC to vary the value of the resistor connected to the OCP
pin with the photocoupler. Refer to figures 19 and 20.
AN8027, AN8037 I
TR
TR
VCC
Current mirror
ISD = ITR + 70 µA
FB
ISD
IOCP
100 µA
Current mirror
IFB
1:5
DB
SD
OCP
On
PC
NB
CTIM
VFB
PC2
20 kΩ
GND
The timer period is adjusted
by detecting the overload level
on the secondary side from IFB .
Timer capacitor charging condition
The following condition must be
satisfied during on-period.
VOCP > VFB
The operating mode (i.e., either the standby
or normal mode) is detected by
the microcomputer on the secondary side
and the timer period is adjusted.
Figure 19
Timer period
(s)
7
Standby mode
Normal operation mode
2
40
Figure 20
70
Load on secondary side (W)
(Values are for an example circuit.)
21
AN8027, AN8037
Voltage Regulators
■ Application Notes (continued)
[1] Operation descriptions (continued)
13. Overvoltage protection (OVP) circuit
OVP stands for overvoltage protection. The overvoltage protection circuit is a self-diagnostic function that
shuts down the power supply to protect the load if a voltage that is significantly and abnormally higher than the
normal output voltage occurs in the power supply output, due to, for example, a malfunction in the control system
or an abnormal voltage applied externally. (Refer to figure 22.)
Basically, the overvoltage protection circuit should be designed so that the VCC pin voltage of the IC can be
monitored. Since the VCC pin voltage is normally supplied from the transformer bias winding, this voltage is
proportional to the secondary side output voltage. Thus the overvoltage protection circuit operates when an
overvoltage occurs in the secondary side output.
1) If, as a result of an abnormality in the power supply output, the voltage input to the VCC pin exceeds the
threshold value (20.5 V typical), the IC internal reference voltage is shut down, and all control operation is
stopped. The IC then holds this state. If latching at a voltage lower than the threshold value is required,
connect a Zener diode between the VCC and SD pins as shown in figure 22 and take method 2) below to set the
voltage.
2) If the SD pin input voltage exceeds a threshold value of 3.9 V typical, the IC internal reference voltage is shut
down, and all control operation is stopped. The IC then holds this state.
3) OVP is reset in two methods. One is to decrease the output voltage on the secondary side so that the VCC pin
voltage is less than the OVP reset voltage, i.e., 8.1 V typical. The other is to decrease the SD pin input voltage
(VSD) to a value less than the SD reset voltage, i.e., 0.7 V typical, by external resetting. If VSD is less than 0.1
V typical, however, the IC will be in remote operation to shut off the output.
The IC incorporates a circuit that discharges a constant current of approximately 25 mA from the capacitor
connected to the SD pin for the re-start operation. The operation of this circuit is stopped when the SD pin
voltage drops to 1.5 V or below. Refer to figure 21.
OVP reset conditions
VCC < OVP reset voltage
VSD < SD reset voltage
AN8027, AN8037
NB
VCC
OVP
ZOVP
DB
Latch
SD
Shutdown
VOVP-SD
3.9 V typ.
Timer capacitor
discharging conditions
VCC < U.V.L.O. stop voltage
VCC < OVP reset voltage
VOVP-VCC
20.5 V typ.
CTIM
Timer capacitor
discharging
transistor
On
GND
Figure 21
The following is a formula to allow the IC to be in OVP operation with the SD pin in the above method 2).
V(OUT) Secondary side output voltage under normal operation
Vth(OUT) =
× V7
VCC pin voltage under normal operation
V7 = VTH-SD1 + VZ
Vth(OUT) : Secondary side output overvoltage threshold value
VTH-SD1 : SD operating threshold value
VZ
: Zener voltage (externally connected to OVP pin)
22
Voltage Regulators
AN8027, AN8037
■ Application Notes (continued)
[1] Operation descriptions (continued)
13. Overvoltage protection (OVP) circuit (continued)
• Operating supply current characteristics
When the OVP circuit operates and the power supply current drops, this can induce a rise of the supply
voltage VCC . In the worst case, it may exceed the IC's guaranteed breakdown voltage (24 V).
Therefore, the circuit is provided with characteristics that cause the supply current to rise in constant
resistance mode when the OVP circuit operates, and thus prevent increases in the supply voltage.
Due to these characteristics, if the supply voltage VCC when the OVP circuit operates is stabilized at a value
(note that this value depends on the value of the startup resistor) that is larger than the OVP release voltage,
the OVP circuit will not be reset as long as the AC input is not cut. (Refer to figure 23.) Note that this does not
apply to an external reset.
Rectified AC
Startup resistor
R1
Power output
VCC
Abnormal voltage applied
from outside.
Load
SD
Should there be abnormal voltage (i.e., voltage that is higher than
the power output voltage and may damage the load) applied to
the power output from outside, the IC detects the abnormal voltage
through the bias winding on the primary side and triggers OVP.
Out
GND
Figure 22
Current is continuously supplied to the VCC pin through
the startup resistor as long as voltage is applied to the
startup resistor from commercial AC power.
Rectified AC
Startup resistor
R1
No current is supplied to the VCC pin from this bias winding
if OVP is triggered and the output of the IC is stopped.
VCC
* Select the startup resistor so that the VCC satisfies
the following condition according to the current
supplied through the startup resistor.
VCC > VCC−OVP
Out
GND
ICC
There is a surge of operating current at VCC−OVP (i.e., a
voltage that resets overvoltage protection). This prevents
VCC from exceeding the absolute maximum rating of the IC
caused by a decrease in current supply from the startup resistor.
VCC− OVP
VCC
Figure 23
23
AN8027, AN8037
Voltage Regulators
■ Application Notes (continued)
[1] Operation descriptions (continued)
14. Remote on/off function
The SD pin of the AN8027 or AN8037 has a remote on/off function besides the following functions.
• Timer latch function
• Overvoltage protection function
The remote on/off function turns the power supply output on and off remotely with external signals.
Furthermore, this function turns the power supply off by setting the SD pin voltage extremely close to the ground
voltage (i.e., 0 V) if the capacitor connected to the SD pin for timer latch use is damaged in the short-circuit mode.
Refer to figure 24.
AN8027, AN8037
The power supply is turned off if the capacitor
is damaged in the short-circuit mode.
8 SD
Figure 24
On the other hand, a hysteresis width of 50 mV (typical) is provided for threshold SD voltage to prevent the
output of the IC in remote operation from chattering. Refer to figure 25.
VSD 0.15 V
0.1 V
0V
VOUT
Start
Stop
Figure 25
24
Voltage Regulators
AN8027, AN8037
■ Application Notes (continued)
[1] Operation descriptions (continued)
15. Overcurrent protection circuit (pulse-by-pulse overcurrent protection)
This circuit uses the fact that overcurrents in the power supply output are proportional to the current flowing
in the primary side main switch (power MOSFET). This circuit limits overcurrents in the power supply output by
constraining the upper limit of the pulse current flowing in the main switch, and thus protects components sensitive to excessive current.
The current flowing in the main switch is detected by connecting a resistor between the power MOSFET source
and ground and monitoring the voltage that appears across that resistor. When the power MOSFET is turned on
and the CLM (current limit) threshold voltage is detected, the output is turned off. This controls the circuit so that
a current in excess of that limit cannot flow by turning off the power MOSFET. The CLM threshold voltage is
about − 0.2 V typical with respect to ground at Ta = 25°C. While this control operation is repeated every cycle, once
an overcurrent is detected, the off state is held for the remainder of that cycle, and the circuit is not turned on until
the next period. This type of overcurrent detection
Use a capacitor with
is called "pulse-by-pulse overcurrent detection."
excellent frequency
R6 and C6 in figure 26 form a filter circuit that
characteristics.
R6 R8
rejects noise generated due to the incidental
CLM
equivalent parasitic capacitance when the power
C6
MOSFET is on.
For the grounding point, we recommend that
GND
R7
the power MOSFET source pin and the IC GND
Use resistor with
pin be connected over as short a distance as pos- To AC −
no inductance.
sible.
Figure 26
• Notes on the detection level precision
This overcurrent detection level is reflected on the operating current level of the power supply overcurrent
protection function. Therefore, if this detection level varies with sample-to-sample variations or with temperature,
the operating current level of the overcurrent protection function of the power supply itself will vary. Since
variations in this level imply a need for increased ruggedness in parts used, or even the destruction of circuit
components, we have increased the precision of this IC as much as possible.
16. Overcurrent protection circuit (input voltage correction function)
As an extended application, this section presents a circuit design that applies a correction so that the overcurrent
protection operating point is held fixed with respect to variations in the input voltage. This circuit uses the proportional relationship between the input voltage and the inverted voltage of the bias winding, and superposes inverted
voltage of the bias winding on the overcurrent protection operating voltage. (Refer to figures 27 and 28.)
EIN+
VCC
VB
AN8027
AN8037
TR
Drs
IDS
Out
CLM
FB voltage applied; Shutdown
FF voltage applied; Correction operation
GND
Rrs
Zrs
VCLM
Determines the input voltage
at which correction starts.
Input voltage
correction
Determines
the amount of correction
EIN−
Figure 27
25
AN8027, AN8037
Voltage Regulators
■ Application Notes (continued)
[1] Operation descriptions (continued)
16. Overcurrent protection circuit (input voltage correction function) (continued)
VDS
0V
VB
0V
FB voltage
FF voltage
IDS
Input voltage; larger
↓
Amount of correction;
larger
∝
Input voltage
EIN
0A
0V
Correction corresponding
to the input voltage
VCLM
Figure 28
17. Overcurrent protection circuit (Timer latch protection)
The CLM pin is used for timer latch in addition to pulse-by-pulse overcurrent protection.
This is because the pulse-by-pulse overcurrent protection alone cannot prevent the power MOSFET connected to the Out pin from damage in most cases if the primary winding is short-circuited and excessive current
flows to the power MOSFET.
If an excessive current flows to the power MOSFET for a certain period due to the short-circuiting of the
primary winding, this circuit charges the capacitor connected to the SD pin, shut down the power supply, and
holds this state. (Refer to figure 29.)
Power supply
stop
IDS
Winding short-circuiting
Power MOSFET
current
Time
0
Power supply
stop
VSD
VTH1−SD = 3.9 V typ.
SD pin voltage
0
VSTB−SD = 1.5 V
Time
Figure 29
[Setting the timer period]
The timer period (TCLM) is obtained from the following formula.
TCLM = {CSD × (VTH1-SD − VSTB-SD)}/ICLM(AVE)
CSD
: Capacitor connected to SD pin
ICLM(AVE) = ICLM × TOFF /T
VTH1-SD : Shutdown operating threshold voltage
(ICLM = 100 µA)
VSTB-SD : Shutdown standby voltage
ICLM : CLM timer charge current (100 µA)
Example: If TOFF / T is 50%, CSD is 10 µF.
TOFF : Off-period
TIM ≈ 500 ms
T
: Cycle
26
Voltage Regulators
AN8027, AN8037
■ Application Notes (continued)
[2] Package power dissipation
PD  Ta
1 000
900
874
Independent IC
without a heat sink
Rth j−a = 143°C/W
PD = 874 mW (25°C)
Power dissipation PD (mW)
800
700
600
500
400
300
200
100
0
0
25
50
75
100
125
150
Ambient temperature Ta (°C)
■ Application Circuit Examples
• Circuit Diagram
D1
100 V
C3 2 200 pF/250 V
C1
0.22 µF
/250 V
L1
C2
0.1 µF C4 2 200 pF
/250 V
D6 SBD
C5
C12
2 200 pF
L2
180 µF
/250 V
38 V
MA3F760
(MA760*)
C14
22 µF/50 V
R1
68 kΩ × 2
D7 SBD
13 V
MA3F750
(MA750*)
R19
68 kΩ × 2
C16
1 000 µF/25 V
D8 SBD
MA3D798
(MA10798*)
R8
C9
15 kΩ 3300 pF
D2
C17
1 000 µF
PC1
MA2C166
(MA166*)
PC1
9
AN8027, AN8037
8
100 µF/50 V
7
C10
C16
10 µF/50 V
6
S2
5 MA2C700 (MA700*)
SBD
4
3
Q3
R3
75 kΩ
D3 MA2C166
(MA166*) Q2
R5
47 Ω
FBI
C7
2 200 pF
R9 18 kΩ
R7
820 Ω
Q1
Note) *: Former part number
S1
MA2C700
(MA700*)
SBD
R15
51 Ω
R14
1.8 kΩ
AN1431M/T R13
1.5 kΩ
GND
D9 SBD
−30 V
MA3D760
(MA7D60*)
D10 SBD
2
1
R11
510 Ω
C15
1.5 µF
6V
R12
500 Ω
C18
22 µF/50 V
R4
47 Ω
C11 1 800 pF
R10
750 Ω
4.6 V
MA3D798
(MA10798*)
R6
0.22 Ω
C19
47 µF/16 V
0V
27
28
C3
L1
JP
C4
+
L2
D1
∼
R1
∼
R9
S1
C13
−
R19
Z3
R18
R3
JP
S2
R17
Q1 JP
D5
C11 C7 R15
Z2
R7
G
9
D3
D
C10
D2
R4
Q2
S
Z1
C16
R8
C9 R16
D4
R5
FB1
C6
R2
1
9
PC1
18
10
0.8 ∅
T1
K
JP
K
D7
K Q3 R
A
C15
R14
R13
R10
C19
R12
(Adj.)
C18
C16
A
A
C14
A K D9
D10
A
A
A
K
R15 R11
A
K
D6
C17
D8
A
A
N.C.
0V
4.6 V
30 V
GND
6V
13 V
38 V
TN2
• Evaluation board chart
L
C1
C5
R6
FB2
■ Application Circuit
Examples (continued)
AN8027/AN8037
Application Board
TN1
N
C12
C8
AN8027, AN8037
Voltage Regulators