DATASHEET

CA5160
CT
ODU O DUCT
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P
PR
TE
O L E TI TU T E
S
B
0
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SUB 0, CA313
LE Data
B
4
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1
Sheet
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3
CA
PO S
®
4MHz, BiMOS Microprocessor Operational
Amplifier with MOSFET Input/CMOS
Output
CA5160 is an integrated circuit operational amplifier that
combines the advantage of both CMOS and bipolar
transistors on a monolithic chip. The CA5160 is a frequency
compensated version of the popular CA5130 series. It is
designed and guaranteed to operate in microprocessor or
logic systems that use +5V supplies.
Gate-protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very high input impedance,
very low input current, and exceptional speed performance.
The use of PMOS field effect transistors in the input stage
results in common-mode input voltage capability down to 0.5V
below the negative supply terminal, an important attribute in
single supply applications.
A complementary symmetry MOS (CMOS) transistor pair,
capable of swinging the output voltage to within 10mV of
either supply voltage terminal (at very high values of load
impedance), is employed as the output circuit.
The CA5160 operates at supply voltages ranging from +5V to
+16V, or ±2.5V to ±8V when using split supplies, and have
terminals for adjustment of offset voltage for applications
requiring offset-null capability. Terminal provisions are also
made to permit strobing of the output stage. It has guaranteed
specifications for 5V operation over the full military
temperature range of -55oC to 125oC.
CA5160M96 (5160)
TEMP.
RANGE (oC)
-55 to 125
FN1924.7
Features
• MOSFET Input Stage
- Very High ZI; 1.5TΩ (1.5 x 1012Ω) (Typ)
- Very Low II; at 15V Operation. . . . . . . . . . . . 5pA (Typ)
at 5V Operation. . . . . . . . . . . . . 2pA (Typ)
• Common-Mode Input Voltage Range Includes Negative
Supply Rail; Input Terminals Can be Swung 0.5V Below
Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either (or
Both) Supply Rails
• CA5160 Has Full Military Temperature Range Guaranteed
Specifications for V+ = 5V
• CA5160 is Guaranteed to Operate Down to 4.5V for AOL
• CA5160 is Guaranteed Up to ±7.5V
Applications
• Ground Referenced Single Supply Amplifiers
• Fast Sample-Hold Amplifiers
• Long Duration Timers/Monostables
• Ideal Interface With Digital CMOS
• High Input Impedance Wideband Amplifiers
• Voltage Followers (e.g., Follower for Single Supply D/A
Converter)
• Wien-Bridge Oscillators
• Voltage Controlled Oscillators
Part Number Information
PART NUMBER
(BRAND)
May 2003
PACKAGE
8 Ld SOIC
Tape and Reel
PKG.
NO.
M8.15
• Photo Diode Sensor Amplifiers
• 5V Logic Systems
• Microprocessor Interface
Pinout
CA5160 (SOIC)
TOP VIEW
OFFSET NULL
1
8
STROBE
INV. INPUT
2
7
V+
NON INV. INPUT
3
6
OUTPUT
V-
4
5
OFFSET NULL
+
NOTE: CA5160 devices have an on-chip frequency compensation
network. Supplementary phase-compensation or frequency roll-off (if
desired) can be connected externally between terminals 1 and 8.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
CA5160
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note 2). . . . . . . . . . . . . . . . Indefinite
Thermal Resistance (Typical, Note 1) θJA (oC/W)θJC (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . .
165
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. Short circuit may be applied to ground or to either supply.
TA = 25oC, V+ = 5V, V- = 0V, Unless Otherwise Specified
Electrical Specifications
PARAMETER
TEST
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Input Offset Voltage
VIO
VO = 2.5V
-
2
10
mV
Input Offset Current
IIO
VO = 2.5V
-
0.1
10
pA
II
VO = 2.5V
-
2
15
pA
VCM = 0 to 1V
70
80
-
dB
VCM = 0 to 2.5V
60
69
-
dB
VlCR+
2.5
2.8
-
V
VlCR-
-
-0.5
0
V
∆V+ = 1V; ∆V- = 1V
55
67
-
dB
RL = ∞
95
117
-
dB
RL = 10kΩ
85
102
-
dB
ISOURCE
VO = 0V
1.0
3.4
4.0
mA
ISINK
VO = 5V
1.0
2.2
4.8
mA
VOUT
RL = ∞
4.99
5
-
V
-
0
0.01
V
4.4
4.7
-
V
-
0
0.01
V
2.5
3.3
-
V
-
0
0.01
V
Input Current
Common Mode Rejection Ratio
CMRR
Common Mode Input Voltage Range
Power Supply Rejection Ratio
Large Signal Voltage
Gain (Note 3)
PSRR
VO = 0.1 to 4.1V
VO = 0.1 to 3.6V
Source Current
Sink Current
Maximum Output Voltage
AOL
VOM+
VOMVOM+
RL = 10kΩ
VOMVOM+
RL = 2kΩ
VOMSupply Current
ISUPPLY
VO = 0V
-
50
100
µA
ISUPPLY
VO = 2.5V
-
320
400
µA
NOTE:
3. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at RL = 10kΩ.
2
CA5160
TA = -55oC to 125oC, V+ = 5V, V- = 0V, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Offset Voltage
VIO
VO = 2.5V
-
3
15
mV
Input Offset Current
IIO
VO = 2.5 V
-
0.1
10
nA
II
VO = 2.5V
-
2
15
nA
VCM = 0 to 1V
60
80
-
dB
VCM = 0 to 2.5V
50
75
-
dB
VlCR+
2.5
2.8
-
V
VlCR-
-
-0.5
0
V
∆V+ = 2V
40
60
-
dB
RL = ∞
90
110
-
dB
RL = 10kΩ
75
100
-
dB
ISOURCE
VO = 0V
0.6
-
5.0
mA
ISINK
VO = 5V
0.6
-
6.2
mA
VOUT
RL= ∞
4.99
5
-
V
-
0
0.01
V
4.0
4.3
-
V
-
0
0.01
V
2.0
2.5
-
V
-
0
0.01
V
Input Current
Common Mode Rejection Ratio
CMRR
Common Mode Input Voltage Range
Power Supply Rejection Ratio
PSRR
Large Signal Voltage Gain
(Note 4)
VO = 0.1 to 4.1V
AOL
VO = 0.1 to 3.6V
Source Current
Sink Current
Maximum Output Voltage
VOM+
VOMVOM+
RL = 10kΩ
VOMVOM+
RL = 2kΩ
VOMSupply Current
VO = 0V
ISUPPLY
-
170
220
µA
VO = 2.5V
ISUPPLY
-
410
500
µA
MIN
TYP
MAX
UNITS
NOTE:
4. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at RL = 10kΩ.
TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
Input Offset Voltage
VIO
VS = ±7.5V
-
6
15
mV
Input Offset Current
IIO
VS = ±7.5V
-
0.5
30
pA
II
VS = ±7.5V
-
5
50
pA
50
320
-
kV/V
94
110
-
dB
CMRR
70
90
-
dB
VlCR
10
-0.5 to 12
0
V
-
32
320
µV/V
12
13.3
-
V
-
0.002
0.01
V
14.99
15
-
V
-
0
0.1
V
VO = 0V
12
22
45
mA
VO = 15V
12
20
45
mA
Input Current
Large Signal Voltage Gain
AOL
Common Mode Rejection Ratio
Common Mode Input Voltage Range
Power Supply Rejection Ratio
Maximum Output
Voltage
VOM+
VO = 10VP-P
RL = 2kΩ
PSRR
∆V+ = 1V; ∆V- = 1V
VS = ±7.5V
VOUT
RL = 2kΩ
VOMRL = ∞
VOM+
VOMMaximum Output
Current
IOM+ (Source)
IOM- (Sink)
3
IO
CA5160
TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified (Continued)
Electrical Specifications
PARAMETER
SYMBOL
Supply Current
I+
Input Offset Voltage Temperature Drift
TEST CONDITIONS
MIN
TYP
MAX
UNITS
RL = ∞, VO = 7.5V
-
10
15
mA
RL = ∞, VO = 0V
-
2
3
mA
∆VIO/∆T
-
8
-
µV/oC
For Design Guidance, At TA = 25oC, VSUPPLY = ±7.5V, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
Input Offset Voltage Adjustment Range
10kΩ Across Terminals 4 and 5 or 4 and 1
TYP
UNITS
±22
mV
1.5
TΩ
Input Resistance
RI
Input Capacitance
CI
f = 1MHz
4.3
pF
Equivalent Input Noise Voltage
eN
BW = 0.2MHz, RS = 1MΩ
40
µV
BW = 0.2MHz, RS = 10MΩ
50
µV
RS = 100Ω, 1kHz
72
nV/√Hz
RS = 100Ω, 10kHz
30
nV/√Hz
Equivalent Input Noise Voltage
eN
Unity Gain Crossover Frequency
fT
4
MHz
Slew Rate
SR
10
V/µs
0.09
µs
10
%
1.8
µs
Transient Response
Rise Time
tR
Overshoot
OS
Settling Time (To <0.1%, VIN = 4VP-P)
CC = 25pF, RL = 2kΩ (Voltage Follower)
tS
CC = 25pF, RL = 2kΩ, (Voltage Follower)
Block Diagram
7
200µA
1.35mA
8mA
(NOTE 5)
0mA
(NOTE 6)
200µA
V+
NOTES:
5. Total supply voltage (for indicated voltage
gains) = 15V with input terminals biased so that
Terminal 6 potential is +7.5V above Terminal 4.
BIAS CKT.
6. Total supply voltage (for indicated voltage
gains) = 15V with output terminal driven to either
supply rail.
+
3
OUTPUT
AV ≈
6000X
AV ≈ 5X
INPUT
AV ≈ 30X
6
2
-
4
CC
5
1
OFFSET
NULL
8
COMPENSATION
(WHEN DESIRED)
4
STROBE
V-
CA5160
Schematic Diagram
CURRENT SOURCE
FOR Q6 AND Q7
BIAS CIRCUIT
Q1
D1
D2
Z1
8.3V
R1
40kΩ
7
“CURRENT SOURCE
LOAD” FOR Q11
Q2
Q3
Q4
Q5
V+
D3
D4
R2
5kΩ
INPUT STAGE
D5
NON-INV.
INPUT
3
D7
D6
SECOND
STAGE
OUTPUT
STAGE
+
Q6
Q7
R3
1kΩ
R5
1kΩ
6
30
pF
R4
1kΩ
Q9
OUTPUT
2kΩ
2
INV. INPUT
Q8
Q10
Q12
Q11
R6
1kΩ
5
1
OFFSET NULL
SUPPLEMENTARY
COMP IF DESIRED
8
4
STROBING
NOTE: Diodes D5 through D7 provide gate oxide protection for MOSFET Input Stage.
Application Information
Circuit Description
Refer to the block diagram of the CA5160 CMOS
Operational Amplifier. The input terminals may be operated
down to 0.5V below the negative supply rail, and the output
can be swung very close to either supply rail in many
applications. Consequently, the CA5160 circuit is ideal for
single supply operation. Three class A amplifier stages,
having the individual gain capability and current
consumption shown in the block diagram, provide the total
gain of the CA5160. A biasing circuit provides two potentials
for common use in the first and second stages. Terminals 8
and 1 can be used to supplement the internal phase
compensation network if additional phase compensation or
frequency roll-off is desired. Terminals 8 and 4 can also be
used to strobe the output stage into a low quiescent current
state. When Terminal 8 is tied to the negative supply rail
(Terminal 4) by mechanical or electrical means, the output
potential at Terminal 6 essentially rises to the positive supply
rail potential at Terminal 7. This condition of essentially zero
current drain in the output stage under the strobed “OFF”
5
condition can only be achieved when the ohmic load
resistance presented to the amplifier is very high (e.g., when
the amplifier output is used to drive CMOS digital circuits in
comparator applications).
Input Stages
The circuit of the CA5160 is shown in the schematic diagram.
It consists of a differential input stage using PMOS field effect
transistors (Q6, Q7) working into a mirror pair of bipolar
transistors (Q9, Q10) functioning as load resistors together
with resistors R3 through R6. The mirror pair transistors also
function as a differential-to-single-ended converter to provide
base drive to the second-stage bipolar transistor (Q11). Offset
nulling, when desired, can be effected by connecting a
100,000Ω potentiometer across Terminals 1 and 5 and the
potentiometer slider arm to Terminal 4.
Cascode-connected PMOS transistors Q2, Q4, are the
constant current source for the input stage. The biasing
circuit for the constant current source is subsequently
described. The small diodes D5 through D7 provide gateoxide protection against high voltage transients, including
static electricity during handling for Q6 and Q7.
CA5160
Second Stage
Offset Nulling
Most of the voltage gain in the CA5160 is provided by the
second amplifier stage, consisting of bipolar transistor Q11
and its cascode-connected load resistance provided by
PMOS transistors Q3 and Q5. The source of bias potentials
for these PMOS transistors is described later. Miller Effect
compensation (roll off) is accomplished by means of the 30pF
capacitor and 2kΩ resistor connected between the base and
collector of transistor Q11. These internal components provide
sufficient compensation for unity gain operation in most
applications. However, additional compensation, if desired,
may be used between Terminals 1 and 8.
Offset voltage nulling is usually accomplished with a 100,000Ω
potentiometer connected across Terminals 1 and 5 and with
the potentiometer slider arm connected to Terminal 4. A fine
offset null adjustment usually can be affected with the slider
arm positioned in the mid point of the potentiometer’s total
range.
At total supply voltages, somewhat above 8.3V, resistor R2
and zener diode Z1 serve to establish a voltage of 8.3V
across the series connected circuit, consisting of resistor R1,
diodes D1 through D4, and PMOS transistor Q1. A tap at the
junction of resistor R1 and diode D4 provides a gate bias
potential of about 4.5V for PMOS transistors Q4 and Q5 with
respect to Terminal 7. A potential of about 2.2V is developed
across diode connected PMOS transistor Q1 with respect to
Terminal 7 to provide gate bias for PMOS transistors Q2 and
Q3. It should be noted that Q1 is “mirror connected” to both Q2
and Q3. Since transistors Q1, Q2 and Q3 are designed to be
identical, the approximately 200µA current in Q1 establishes a
similar current in Q2 and Q3 as constant current sources for
both the first and second amplifier stages, respectively.
At total supply voltages somewhat less than 8.3V, zener diode
Z1 becomes non-conductive and the potential, developed
across series connected R1, D1-D4, and Q1 varies directly
with variations in supply voltage. Consequently, the gate bias
for Q4, Q5 and Q2, Q3 varies in accordance with supply
voltage variations. This variation results in deterioration of the
power supply rejection ration (PSRR) at total supply voltages
below 8.3V. Operation at total supply voltages below about
4.5V results in seriously degraded performance.
Output Stage
The output stage consists of a drain loaded inverting
amplifier using CMOS transistors operating in the Class A
mode. When operating into very high resistance loads, the
output can be swung within millivolts of either supply rail.
Because the output stage is a drain loaded amplifier, its gain
is dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 20. Typical op-amp
loads are readily driven by the output stage. Because large
signal excursions are nonlinear, requiring feedback for good
waveform reproduction, transient delays may be
encountered. As a voltage follower, the amplifier can
achieve 0.01% accuracy levels, including the negative
supply rail.
6
As shown in the Table of Electrical Specifications, the input
current for the CA5160 Series Op Amps is typically 5pA at
TA = 25oC when Terminals 2 and 3 are at a common-mode
potential of +7.5V with respect to negative supply Terminal
4. Figure 1 contains data showing the variation of input
current as a function of common-mode input voltage at
TA = 25oC. These data show that circuit designers can
advantageously exploit these characteristics to design
circuits which typically require an input current of less than
1pA, provided the common-mode input voltage does not
exceed 2V. As previously noted, the input current is
essentially the result of the leakage current through the gateprotection diodes in the input circuit and, therefore, a
function of the applied voltage. Although the finite resistance
of the glass terminal-to-case insulator of the metal can
package also contributes an increment of leakage current,
there are useful compensating factors. Because the gateprotection network functions as if it is connected to Terminal
4 potential, and the metal can case of the CA5160 is also
internally tied to Terminal 4, input terminal 3 is essentially
“guarded” from spurious leakage currents.
10
TA = 25oC
7.5
INPUT VOLTAGE (V)
Bias-Source Circuit
Input Current Variation with Common Mode Input
Voltage
5
V+ 15V
TO
5V
7
2
CA5160
PA
6
3
2.5
4
VIN
8
0V
TO
V- -10V
0
-1
0
1
2
3
4
5
6
7
INPUT CURRENT (pA)
FIGURE 1. CA5160 INPUT CURRENT vs COMMON MODE
VOLTAGE
Input Current Variation with Temperature
The input current of the CA5160 series circuits is typically
5pA at 25oC. The major portion of this input current is due to
leakage current through the gate protective diodes in the
input circuit. As with any semiconductor-junction device,
CA5160
In applications requiring the lowest practical input current
and incremental increases in current because of “warm-up”
effects, it is suggested that an appropriate heat sink be used
with the CA5160. In addition, when “sinking” or “sourcing”
significant output current the chip temperature increases,
causing an increase in the input current. In such cases, heatsinking can also very markedly reduce and stabilize input
current variations.
7
TA = 125oC FOR METAL CAN PACKAGES
OFFSET VOLTAGE SHIFT (mV)
including op amps with a junction-FET input stage, the
leakage current approximately doubles for every 10oC
increase in temperature. Figure 2 provides data on the
typical variation of input bias current as a function of
temperature in the CA5160.
6
DIFFERENTIAL DC VOLTAGE
5 (ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED
4
3
2
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 0V
OUTPUT VOLTAGE = V+/2
1
0
0
4000
VS = ±7.5V
1000 1500
2000 2500
3000 3500
4000
TIME (HOURS)
1000
INPUT CURRENT (pA)
500
FIGURE 3. TYPICAL INCREMENTAL OFFSET VOLTAGE
SHIFT vs OPERATING LIFE
Power Supply Considerations
100
Because the CA5160 is very useful in single-supply
applications, it is pertinent to review some considerations
relating to power-supply current consumption under both
single-and dual-supply service. Figures 4A and 4B show the
CA5160 connected for both dual and single-supply
operation.
10
1
-80 -60 -40 -20
0
20 40 60 80
TEMPERATURE (oC)
100 120 140
FIGURE 2. INPUT CURRENT vs TEMPERATURE
Input Offset Voltage (VIO) Variation with DC Bias
vs Device Operating Life
It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The
magnitude of the change is increased at high temperatures.
Users of the CA5160 should be alert to the possible impacts
of this effect if the application of the device involves extended
operation at high temperatures with a significant differential
DC bias voltage applied across Terminals 2 and 3. Figure 3
shows typical data pertinent to shifts in offset voltage
encountered with CA5160 devices in metal can packages
during life testing. At lower temperatures (metal can and
plastic) for example at 85oC, this change in voltage is
considerably less. In typical linear applications where the
differential voltage is small and symmetrical, these
incremental changes are of about the same magnitude as
those encountered in an operational amplifier employing a
bipolar transistor input stage. The 2VDC differential voltage
example represents conditions when the amplifier output state
is “toggled”, e.g., as in comparator applications.
7
Dual-Supply Operation - When the output voltage at
Terminal 6 is 0V, the currents supplied by the two power
supplies are equal. When the gate terminals of Q8 and Q12
are driven increasingly positive with respect to ground,
current flow through Q12 (from the negative supply) to the
load is increased and current flow through Q8 (from the
positive supply) decreases correspondingly. When the gate
terminals of Q8 and Q12 are driven increasingly negative
with respect to ground, current flow through Q8 is increased
and current flow through Q12 is decreased accordingly.
Single Supply Operation - Initially, let it be assumed that
the value of RL is very high (or disconnected), and that the
input- terminal bias (Terminals 2 and 3) is such that the output
terminal (Number 6) voltage is at V+/2, i.e., the voltage-drops
across Q8 and Q12 are of equal magnitude. Figure 21 shows
typical quiescent supply-current vs supply-voltage for the
CA5160 operated under these conditions. Since the output
stage is operating as a Class A amplifier, the supply-current
will remain constant under dynamic operating conditions as
long as the transistors are operated in the linear portion of
their voltage transfer characteristics (see Figure 20). If either
Q8 or Q12 are swung out of their linear regions toward cutoff
(a nonlinear region), there will be a corresponding reduction in
supply-current. In the extreme case, e.g., with Terminal 8
swung down to ground potential (or tied to ground), NMOS
transistor Q12 is completely cut off and the supply-current to
series-connected transistors Q8, Q12 goes essentially to zero.
The two preceding stages in the CA5160, however, continue
CA5160
to draw modest supply-current (see the lower curve in Figure
21) even through the output stage is strobed off. Figure 4A
shows a dual-supply arrangement for the output stage that
can also be strobed off, assuming RL = ∞, by pulling the
potential of Terminal 8 down to that of Terminal 4.
Let it now be assumed that a load-resistance of nominal
value (e.g., 2kΩ) is connected between Terminal 6 and
ground in the circuit of Figure 4B. Let it further be assumed
again that the input terminal bias (Terminals 2 and 3) is such
that the output terminal (Number 6) voltage is V+/2. Since
PMOS transistor Q8 must now supply quiescent current to
both RL and transistor Q12, it should be apparent that under
these conditions the supply current must increase as an
inverse function of the RL magnitude. Figure 27 shows the
voltage drop across PMOS transistor Q8 as a function of
load current at several supply voltages. Figure 20 shows the
voltage transfer characteristics of the output stage for
several values of load resistance.
40µV when the test-circuit amplifier of Figure 5 is operated at
a total supply voltage of 15V. This value of total inputreferred noise remains essentially constant, even though the
value of source resistance is raised by an order of
magnitude. This characteristic is due to the fact that
reactance of the input capacitance becomes a significant
factor in shunting the source resistance. It should be noted,
however, that for values of source resistance very much
greater than 1MΩ, the total noise voltage generated can be
dominated by the thermal noise contributions of both the
feedback and source resistors.
+7.5V
0.01µF
RS
3
7
+
1MΩ
2
-
4
30.1kΩ
V+
0.01
µF
-7.5V
7
3
2
+
Q8
OUTPUT
Q12
-
NOISE
VOLTAGE
OUTPUT
6
STAGE
BW (-3dB) = 200kHz
TOTAL NOISE VOLTAGE
(INPUT REFERRED) = 40µV (TYP)
6
RL
1kΩ
FIGURE 5. TEST-CIRCUIT AMPLIFIER (30dB GAIN) USED
FOR WIDEBAND NOISE MEASUREMENTS
4
8
Typical Applications
V-
FIGURE 4A. DUAL POWER-SUPPLY OPERATION
Operational amplifiers with very high input resistances, like
the CA5160, are particularly suited to service as voltage
followers. Figure 6 shows the circuit of a classical voltage
follower, together with pertinent waveforms using the
CA5160 in a split supply-configuration.
V+
7
3
+
Q8
OUTPUT
STAGE
2
6
RL
Q12
-
Voltage Followers
4
8
FIGURE 4B. SINGLE POWER-SUPPLY OPERATION
FIGURE 4. CA5160 OUTPUT STAGE IN DUAL AND SINGLE
POWER SUPPLY OPERATION
Wideband Noise
From the standpoint of low-noise performance
considerations, the use of the CA5160 is most
advantageous in applications where in the source resistance
of the input signal is on the order of 1MΩ or more. In this
case, the total input-referred noise voltage is typically only
8
A voltage follower, operated from a single-supply, is shown in
Figure 7 together with related waveforms. This follower circuit
is linear over a wide dynamic range, as illustrated by the
reproduction of the output waveform in Figure 7B with input
signal ramping. The waveforms in Figure 7C show that the
follower does not lose its input-to-output phase-sense, even
though the input is being swung 7.5V below ground potential.
This unique characteristic is an important attribute in both
operational amplifier and comparator applications. Figure 7C
also shows the manner in which the CMOS output stage
permits the output signal to swing down to the negative supply
rail potential (i.e., ground in the case shown). The digital-toanalog converter (DAC) circuit, described in the following
section, illustrates the practical use of the CA5160 in a singlesupply voltage follower application.
CA5160
9 Bit CMOS DAC
+7.5V
0.01µF
3
7
+
10kΩ
6
2
-
4
2kΩ
0.01
µF
-7.5V
2kΩ
BW (-3dB) = 4MHz
SR = 10V/µs
25pF
SIMULATED
LOAD
CAPACITANCE
0.1µF
FIGURE 6A. DUAL SUPPLY FOLLOWER
Top Trace: Output
Bottom Trace: Input
FIGURE 6B. SMALL SIGNAL RESPONSE
A typical circuit of a 9 bit Digital-to-Analog Converter (DAC)
(see Note) is shown in Figure 8. This system combines the
concepts of multiple-switch CMOS ICs, a low cost ladder
network of discrete metal-oxide-film resistors, a CA5160 op
amp connected as a follower, and an inexpensive monolithic
regulator in a simple single power supply arrangement. An
additional feature of the DAC is that it is readily interfaced
with CMOS input logic, e.g., 10V logic levels are used in the
circuit of Figure 8.
The circuit uses an R/2R voltage-ladder network, with the
output-potential obtained directly by terminating the ladder
arms at either the positive or the negative power-supply
terminal. Each CD4007A contains three “inverters”, each
“inverter” functioning as a single-pole double-throw switch to
terminate an arm of the R/2R network at either the positive or
negative power-supply terminal. The resistor ladder is an
assembly of 1% tolerance metal-oxide film resistors. The five
arms requiring the highest accuracy are assembled with series
and parallel combinations of 806,000Ω resistors from the same
manufacturing lot.
A single 15V supply provides a positive bus for the CA5160
follower amplifier and feeds the CA3085 voltage regulator. A
“scale-adjust” function is provided by the regulator output
control, set to a nominal 10V level in this system. The linevoltage regulation (approximately 0.2%) permits a 9 bit
accuracy to be maintained with variations of several volts in
the supply. The flexibility afforded by the CMOS building
blocks simplifies the design of DAC systems tailored to
particular needs.
Error Amplifier in Regulated Power Supplies
The CA5160 is an ideal choice for error-amplifier service in
regulated power supplies since it can function as an erroramplifier when the regulated output voltage is required to
approach 0V.
The circuit shown in Figure 9 uses a CA5160 as an error
amplifier in a continuously adjustable 1A power supply. One
of the key features of this circuit is its ability to regulate down
to the vicinity of zero with only one DC power supply input.
An RC network, connected between the base of the output
drive transistor and the input voltage, prevents “turn-on
overshoot”, a condition typical of many operational-amplifier
regulator circuits. As the amplifier becomes operational, this
RC network ceases to have influence on the regulator
performance.
Top Trace: Output Signal
Center Trace: Difference Signal 5mV/Div.
Bottom Trace: Input Signal
FIGURE 6C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING
SETTLING TIME
FIGURE 6. SPLIT SUPPLY VOLTAGE FOLLOWER WITH
ASSOCIATED WAVEFORMS
9
NOTE: “Digital-to-Analog Conversion Using the Intersil CD4007A
CMOS IC”, Application Note AN6080.
CA5160
Precision Voltage-Controlled Oscillator
+15V
3
+
2
-
10kΩ
The circuit diagram of a precision voltage-controlled
oscillator is shown in Figure 10. The oscillator operates with
a tracking error on the order of 0.02% and a temperature
coefficient of 0.01%/oC. A multivibrator (A1) generates
pulses of constant amplitude (V) and width (T2). Since the
output (Terminal 6) of A1 (a CA5130) can swing within about
10mV of either supply-rail, the output pulse amplitude (V) is
essentially equal to V+. The average output voltage
(EAVG = V T2/T1) is applied to the non-inverting input
terminal of comparator A2 (a CA5160) via an integrating
network R3, C2. Comparator A2 operates to establish circuit
conditions such that EAVG = V1. This circuit condition is
accomplished by feeding an output signal from Terminal 6 of
A2 through R4, D4 to the inverting terminal (Terminal 2) of
A1, thereby adjusting the multivibrator interval, T3.
0.01µF
7
6
4
5
100kΩ
1
OFFSET
ADJUST
2kΩ
0.1µF
FIGURE 7A. SINGLE SUPPLY FOLLOWER
Voltmeter With High Input Resistance
0
FIGURE 7B. OUTPUT SIGNAL WITH INPUT SIGNAL RAMPING
0
0
Top Trace: Output
Bottom Trace: Input
FIGURE 7C. OUTPUT-WAVEFORM WITH GROUNDREFERENCE SINE-WAVE INPUT
FIGURE 7. SINGLE SUPPLY VOLTAGE FOLLOWER WITH
ASSOCIATED WAVEFORMS (e.g., FOR USE IN
SINGLE-SUPPLY D/A CONVERTER; SEE FIGURE
9 IN AN6080)
10
The voltmeter circuit shown in Figure 11 illustrates an
application in which a number of the CA5160 characteristics
are exploited. Range-switch SW1 is ganged between input
and output circuitry to permit selection of the proper output
voltage for feedback to Terminal 2 via 10kΩ current-limiting
resistor. The circuit is powered by a single 8.4V mercury
battery. With zero input signal, the circuit consumes
somewhat less than 500µA plus the meter current required
to indicate a given voltage. Thus, at full-scale input, the total
supply current rises to slightly more than 1500µA.
CA5160
10V LOGIC INPUTS
+10.010V
14
LSB
9
8
7
6
3
10
MSB
11
6
5
4
3
2
1
6
3
10
6
3
10
2
CD4007A
“SWITCHES”
9
13
7
8
CD4007A
“SWITCHES”
1
12
13
5
806K
1%
4
8
402K
1%
200K
1%
2
1
+10.010V
8
22.1K
1%
6
-
REGULATED
VOLTAGE
ADJUST
3.83K
1%
4
2µF
25V
1
8
12
5
(2)
806K
1%
806K
1%
(4)
806K
1%
750K
1%
(8)
806K
1%
+15V
PARALLELED
RESISTORS
1K
0.001µF
BIT
REQUIRED RATIOMATCH
1
Standard
2
±0.1%
3
±0.2%
4
±0.4%
5
±0.8%
6-9
±1% ABS.
10K
7
3
+
OUTPUT
62
7
+
13
806K
1%
806K
1%
CA3085
3
12
5
100K
1%
806K
1%
VOLTAGE
+15V REGULATOR
1
CD4007A
“SWITCHES”
VOLTAGE
FOLLOWER
CA5160
6
-
4
2
5
LOAD
1
100K
OFFSET
NULL
2K
0.1µF
FIGURE 8. 9 BIT DAC USING CMOS DIGITAL SWITCHES AND CA5160
2N6385
POWER DARLINGTON
INPUT 40V
+
SHORT-CIRCUIT CURRENT
LIMIT ADJUSTMENT
1Ω
3
2
OUTPUT
0V
35V
AT 1A
10kΩ
0.2µF
TURN
ON
DELAY
2.4kΩ
1W
1kΩ
1.5kΩ
1W
100kΩ
2N2102
1kΩ
1
1N914
56pF
+
100µF
-
43kΩ
8
2.2kΩ
100µF
25V
+
7
+ 5µF
-
CA3086
10
11
1
5
8
9
7
3
5
6
4
10kΩ
12
62kΩ
3
-
2
1
8.2
kΩ
4
14
4.7kΩ
13
1kΩ
+
6
-
2
10kΩ
2kΩ
50kΩ
100kΩ
0.01µF
-
-
Hum and Noise Output <250µVRMS; Regulation (No Load to Full Load) <0.005%; Input Regulation <0.01%/V
FIGURE 9. CA5160 VOLTAGE REGULATOR CIRCUIT (0.1 TO 35V AT 1A)
11
CA5160
T2
T3
VCO CONTROL VOLTAGE (VI)
(0V - 10V)
V
+15V
fo
(SENSITIVITY = 1kHz/V)
T1
D1
1M
10K
0.01µF
R5
100K
+15V
+15V
D2
100K
0.1
µF
7
3
R6
100K
C1
500pF
2
2
+
A1 MULTIVIBRATOR
CA5130
-
EAVG = V T2/T1
6
R3
1M
3
4
R1
182K
D4
R2
10K
A2 COMPARATOR
CA5160
+
6
4
5
C2
0.01µF
D3
7
-
0.01µF
1
R7
100K
D5
D1 - D5 = 1N914
R4 3K
FIGURE 10. VOLTAGE CONTROLLED OSCILLATOR
300V
300V
100MΩ
100V
100V
30V
30V
10V
BATTERY
TEST
OFF
ON
1.02
MΩ
3 POSITION
SLIDE SWITCH
9.9
kΩ
10V
+
-
SW1A 3V
INPUT
3V
SW1B
1V
1V
300mV
300mV
100mV
100mV
30mV
30mV
10mV
10mV
BATTERY
+9V
BATTERY
3
22MΩ
0.001
µF
7
+
2.7kΩ
2
-
4
5
1
300V
100V
ZERO
ADJUST
10kΩ
1V CAL.
10V
3V
SW1C 3V
1V
300mV
9kΩ
300mV
100mV
900Ω
100mV
30mV
10mV
30mV
10mV
100Ω
FIGURE 11. CA5160A HIGH INPUT RESISTANCE DC VOLTMETER
12
30V
10V
1V
9.1kΩ
300V
100V
820Ω 200Ω
30V
100kΩ
M
0-1mA
3V CAL.
500Ω
6
CA5160
500
µF
SW1D
CA5160
8.2kΩ
BUFFER
VOLTAGE FOLLOWER
20pF
+7.5V
0.9 - 7pF
C1
VOLTAGE-CONTROLLED
CURRENT SOURCE
7
3
+
6
CA3080A
1kΩ
2
-
4
1kΩ
2MΩ
SYMMETRY
-7.5V
100kΩ
+7.5V
6.8MΩ
5
6.2kΩ
3
+
10kΩ
4 - 60pF CA5160
C3
2
-
6
4
-7.5V
10kΩ
6.2kΩ
500Ω
FREQ
ADJUST
500Ω
CA3080
+
6
4
-7.5V
EXTERNAL
SWEEPING INPUT
MIN. FREQ. SET
7.5V
7
2
3
0.1
µF
10kΩ
-7.5V
MAX FREQ
SET
+7.5V
30kΩ
0.1µF
7
-7.5V
4.7kΩ
+7.5V
430pF
10-80pF
C2
5
-7.5V
+7.5V
HIGH
FREQ.
SHAPE
THRESHOLD
DETECTOR
CENTERING
100kΩ
C4
4 - 60pF
2kΩ
HIGH FREQ
LEVEL
ADJUST
50kΩ
2-1N914
C5
15 - 115pF
FIGURE 12A. FUNCTION GENERATOR CIRCUIT
NOTE: A square wave signal modulates the external sweeping
input to produce 1Hz and 1MHz, showing the 1,000,000/1
frequency range of the function generator.
NOTE: The bottom trace is the sweeping signal and the top trace is
the actual generator output. The center trace displays the 1MHz signal
via delayed oscilloscope triggering of the upper swept output signal.
FIGURE 12B. TWO-TONE OUTPUT SIGNAL FROM THE
FUNCTION GENERATOR
FIGURE 12C. TRIPLE-TRACE OF THE FUNCTION GENERATOR
SWEEPING TO 1MHz
FIGURE 12. CA5160 1,000,000/1 SINGLE CONTROL FUNCTION GENERATOR - 1MHz TO 1Hz
13
CA5160
+15V
5.1kΩ
+15V
100
kΩ
100
kΩ
1MΩ
3
100
kΩ
STEP HEIGHT
ADJUST
4 - 60pF
8.2kΩ
7
+
CA5130
2
15 - 115pF
FREQ
ADJUST
-
1N914
470pF
STAIRCASE
OUTPUT
+15V
6
2
7
10kΩ
CA5160
1N914
8
6
CA5130
2kΩ
4
CHARGE
COMMUTATING
NETWORK
+
3
6
+15V
+
3
4
MULTIVIBRATOR
+15V
7
2
1.5
MΩ
-
8
4
INTEGRATOR
HYSTERESIS SWITCH
MULTIVIBRATOR RETRACE INHIBIT
+15mV TO +10V
51kΩ
100kΩ
FIGURE 13A. STAIRCASE GENERATOR CIRCUIT
Function Generator
A function generator having a wide tuning range is shown in
Figure 12. The adjustment range, in excess of 1,000,000/1,
is accomplished by a single potentiometer. Three
operational amplifiers are utilized: a CA5160 as a voltage
follower, a CA3080 as a high-speed comparator, and a
second CA3080A as a programmable current source. Three
variable capacitors C1, C2, and C3 shape the triangular
signal between 500kHz and 1MHz. Capacitors C4, C5, and
the trimmer potentiometer in series with C5 maintain
essentially constant (±10%) amplitude up to 1MHz.
STAIRCASE
OUTPUT
2V STEPS
COMPARATOR
OSCILLATOR
Top Trace: Staircase Output 2V Steps
Center Trace: Comparator
Bottom Trace: Oscillator
Staircase Generator
Figure 13 shows a staircase generator circuit utilizing three
CMOS operational amplifiers. Two CA5130s are used; one as a
multivibrator, the other as a hysteresis switch. The third
amplifier, a CA5160, is used as a linear staircase generator.
FIGURE 13B. STAIRCASE GENERATOR WAVEFORM
FIGURE 13. STAIRCASE GENERATOR CIRCUIT UTILIZING
THREE CMOS OPERATIONAL AMPLIFIERS
10GΩ
+15V
1MΩ
0.1µF
10pF
+15V
7
10MΩ
3
7
+
6
CA5160
2
2
10kΩ
-
4
5
CA3140
3
1
100kΩ
6
+
5.6kΩ
9.9kΩ
560kΩ
4
0.1µF
9.1kΩ
500Ω
100Ω
-15V
M
500-0-500µA
-15V
FIGURE 14. CURRENT-TO-VOLTAGE CONVERTER TO PROVIDE A PICOAMMETER WITH ±3pA FULL SCALE DEFLECTION
14
CA5160
100kΩ
+15V
+15V
2200pF
30pF
1MΩ
+15V
0.1
µF
0.1µF
7
39kΩ
3
+
6
CA5160
2
2
7
-
-
8
1N914
4
5
6
CA3080A
3
1
0.1µF
8.2kΩ
27kΩ
9.1kΩ
2
+
5
DROOP
ZERO
ADJUST
CA3140
1MΩ
100kΩ
4
100kΩ
OFFSET
VOLTAGE
ADJUST
8.2Ω
7
3
6
+
0.1
µF
4
39kΩ
500µA
2kΩ
STROBE INPUT
SAMPLE - 15V
HOLD - 0V
FIGURE 15A. SAMPLE AND HOLD CIRCUIT
SAMPLED
OUTPUT
SAMPLED
OUTPUT
0VINPUT
0V-
INPUT
SIGNAL
SAMPLING
PULSES
SAMPLING
PULSE
Top Trace: Sampled Output
Center Trace: Input Signal
Bottom Trace: Sampling Pulses
FIGURE 15B. SAMPLE AND HOLD WAVEFORM
Top Trace: Sampled Output
Center Trace: Input
Bottom Trace: Sampling Pulses
FIGURE 15C. SAMPLE AND HOLD WAVEFORM
FIGURE 15. SINGLE SUPPLY SAMPLE AND HOLD SYSTEM, INPUT 0V TO 10V
Picoammeter Circuit
Figure 14 is a current-to-voltage converter configuration
utilizing a CA5160 and CA3140 to provide a picoampere
meter for ±3pA full-scale meter deflection. By placing
Terminals 2 and 4 of the CA5160 at ground potential, the
CA5160 input is operated in the “guarded mode”. Under this
operating condition, even slight leakage resistance present
between Terminals 3 and 2 or between Terminals 3 and 4
would result in 0V across this leakage resistance, thus
substantially reducing the leakage current.
If the CA5160 is operated with the same voltage on input
Terminals 3 and 2 as on Terminal 4, a further reduction in
the input current to the less than 1pA level can be achieved
as shown in Figure 1.
15
To further enhance the stability of this circuit, the CA5160
can be operated with its output (Terminal 6) near ground,
thus markedly reducing the dissipation by reducing the
supply current to the device.
The CA3140 stage serves as a X100 gain stage to provide
the required plus and minus output swing for the meter and
feedback network. A 100-to-1 voltage divider network
consisting of a 9.9kΩ resistor in series with a 100Ω resistor
sets the voltage at the 10GΩ resistor (in series with Terminal
3) to ±30mV full-scale deflection. This 30mV signal results
from ±3V appearing at the top of the voltage divider network
which also drives the meter circuitry.
By utilizing a switching technique in the meter circuit and in
the 9.9kΩ and 100Ω network similar to that used in the
voltmeter circuit shown in Figure 11, a current range of 3pA
CA5160
to 1nA full scale can be handled with the single 10GΩ
resistor.
+15V
R1
100kΩ
Single Supply Sample-and-Hold System
Figure 15 shows a single-supply sample-and-hold system
using a CA5160 to provide a high input impedance and an
input-voltage range of 0V to 10V. The output from the input
buffer integrator network is coupled to a CA3080A. The
CA3080A functions as a strobeable current source for the
CA3140 output integrator and storage capacitor. The CA3140
was chosen because of its low output impedance and
constant gain-bandwidth product. Pulse “droop” during the
hold interval can be reduced to zero by adjusting the 100kΩ
bias-voltage potentiometer on the positive input of the
CA3140. This zero adjustment sets the CA3080A output
voltage at its zero current position. In this sample-and-hold
circuit it is essential that the amplifier bias current be reduced
to zero to minimize output signal current during the hold
mode. Even with 320mV at the amplifier bias circuit (Terminal
5) at least ±100pA of output current will be available.
Wien Bridge Oscillator
A simple, single-supply Wien Bridge oscillator using a CA5160
is shown in Figure 16. A pair of parallel-connected 1N914
diodes comprise the gain-setting network which standardizes
the output voltage at approximately 1.1V. The 500Ω
potentiometer is adjusted so that the oscillator will always start
and the oscillation will be maintained. Increasing the amplitude
of the voltage may lower the threshold level for starting and for
sustaining the oscillation, but will introduce more distortion.
+15V
R3
51kΩ
C2
51pF
7
3
OUTPUT
f = 100kHz
2% THD AT 1.1VP-P
+
6
CA5160
2
R2
100kΩ
0.1
µF
4
C1
10-80pF
2kΩ
2-1N914
0.01µF
680Ω
f=
1
2 π √(R1 || R2) C1 R3 C2
500Ω
FIGURE 16. SINGLE-SUPPLY WEIN-BRIDGE OSCILLATOR
The current sourcing and sinking capability of the CA5160
output stage is easily supplemented to provide power-boost
capability. In the circuit of Figure 17, three CMOS transistorpairs in a single CA3600 lC array are shown parallel-connected
with the output stage in the CA5160. In the Class A mode of
CA3600E shown, a typical device consumes 20mA of supply
current at 15V operation. This arrangement boosts the currenthandling capability of the CA5160 output stage by about 2.5X.
The amplifier circuit in Figure 17 employs feedback to
establish a closed-loop gain of 20dB. The typical largesignal-bandwidth (-3dB) is 190kHz.
Operation with Output-Stage Power-Booster
+15V
14
0.01µF
1µF
-
1MΩ
+
3
680kΩ
2
QP2
11
QP3
+
6
CA5160
INPUT
1µF
CA3600 (NOTE)
QP1
7
2
-
8
2kΩ
13
1
3
10
500µF
6
12
4
8
QN1
A = 20dB
LARGE SIGNAL
BW (-3dB) = 190kHz
7
NOTE: See File Number 619.
50Ω
100mW
AT 10%
THD
5
QN2
4
QN3
9
20kΩ
FIGURE 17. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA5160.
16
CA5160
VS = ±7.5V
TA = 25oC
100
0
50
100
φ OL
80
150
200
60
40
CL = 30pF
RL = 2kΩ
20
150
OPEN-LOOP VOLTAGE GAIN (dB)
OPEN-LOOP VOLTAGE GAIN (dB)
120
OPEN-LOOP PHASE (DEGREES)
Typical Performance Curves
102
103
104
105
106
FREQUENCY (Hz)
107
108
FIGURE 18. OPEN-LOOP VOLTAGE GAIN AND PHASE SHIFT
vs FREQUENCY
120
110
100
90
15
17.5
SUPPLY VOLTAGE: V+ = 15V, V- = 0V
TA = 25oC
15
LOAD RESISTANCE = 5kΩ
12.5
2kΩ
1kΩ
10
500Ω
7.5
5
2.5
0
0
2.5
5
7.5
10
12.5
15
17.5
20
-50
LOAD RESISTANCE = ∞
TA = 25oC
OUTPUT VOLTAGE BALANCED = V+/2
V- = 0
12.5
10
7.5
5
OUTPUT VOLTAGE HIGH = V+
OR LOW = V2.5
6
8
GATE VOLTAGE (TERMINALS 4 AND 8) (V)
18
600
OUTPUT VOLTAGE = V+/2
V- = 0
V+ = 5V, V- = 0V
TA = -55oC
10
25oC
8
125oC
6
4
2
525
SUPPLY CURRENT (µA)
QUIESCENT SUPPLY CURRENT (mA)
10
12
14
16
POSITIVE SUPPLY VOLTAGE (V)
FIGURE 21. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE
14
12
100
0
22.5
FIGURE 20. VOLTAGE TRANSFER CHARACTERISTICS OF
CMOS OUTPUT STAGE
0
50
TEMPERATURE (oC)
FIGURE 19. OPEN-LOOP GAIN vs TEMPERATURE
QUIESCENT SUPPLY CURRENT (mA)
OUTPUT VOLTAGE [TERMS 4 AND 6] (V)
130
80
-100
0
101
RL = 2kΩ
140
450
125oC
375
25oC
300
-55oC
225
150
75
0
0
2
4
6
8
10
12
14
16
POSITIVE SUPPLY VOLTAGE (V)
FIGURE 22. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE
17
0
0
0.5
1
1.5
2
2.5
3
3.5
OUTPUT VOLTAGE (V)
4
4.5
FIGURE 23. SUPPLY CURRENT vs OUTPUT VOLTAGE
5
CA5160
Typical Performance Curves
(Continued)
8
9
V+ = 5V, V- = 0V
8
7
OUTPUT VOLTAGE SWING (V)
OUTPUT VOLTAGE SWING (V)
V+ = 5V, V- = 0V
6
5
4
-55oC
3
25oC
125oC
2
7
6
5
4
3
2
1
1
0
1
2
3
4
5
6
7
8
LOAD RESISTANCE (kΩ)
9
10
0
0.1 0.2
11
FIGURE 24. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
V+ = 5V, V- = 0V
OUTPUT CURRENT (mA)
7
6
5
4
SINK
3
2
0
-60
50
V- = 0V
TA = 25oC
10
800
10V
15V
V+ = 5V
1
0.1
-40
-20
0
20
40
60
80
0.001
0.001
100 120 140
TEMPERATURE (oC)
0.01
0.1
1
1000
INPUT NOISE VOLTAGE (nV/ √Hz)
V+ = 15V
10V
5V
1
0.1
0.01
0.001
0.001
0.01
0.1
1
10
MAGNITUDE OF LOAD CURRENT (mA)
FIGURE 28. VOLTAGE ACROSS NMOS OUTPUT
TRANSISTOR (Q12) vs LOAD CURRENT
18
100
FIGURE 27. VOLTAGE ACROSS PMOS OUTPUT
TRANSISTOR (Q8) vs LOAD CURRENT
50
V- = 0V
TA = 25oC
10
MAGNITUDE OF LOAD CURRENT (mA)
FIGURE 26. OUTPUT CURRENT vs TEMPERATURE
VOLTAGE DROP ACROSS NMOS OUTPUT - STAGE
TRANSISTOR (Q12) (V)
200
0.01
SOURCE
1
10
2
4 6 8
20 40 80
LOAD RESISTANCE (kΩ)
FIGURE 25. OUTPUT SWING vs LOAD RESISTANCE
VOLTAGE DROP ACROSS PMOS OUTPUT
STAGE TRANSISTOR (Q8) (V)
8
0.6 1
100
TA = 25oC
VS = ±7.5V
100
10
1
1
101
102
103
FREQUENCY (Hz)
104
105
FIGURE 29. EQUIVALENT NOISE VOLTAGE vs FREQUENCY
CA5160
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010) M
H
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MILLIMETERS
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
α
NOTES:
MAX
A1
e
µα
MIN
8
0o
8
7
8o
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
19
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