Data Sheet

PBSS4220PANS
20 V, 2 A NPN/NPN low VCEsat BISS double transistor
14 December 2015
Product data sheet
1. General description
NPN/NPN low VCEsat Breakthrough In Small Signal (BISS) double transistor in a leadless
medium power DFN2020D-6 (SOT1118D) Surface-Mounted Device (SMD) plastic
package with visible and solderable side pads.
PNP/PNP complement: PBSS5220PAPS
2. Features and benefits
•
•
•
•
•
•
•
•
Very low collector-emitter saturation voltage VCEsat
High collector current capability IC and ICM
High collector current gain hFE at high IC
Reduced Printed-Circuit Board (PCB) requirements
Exposed heat sink for excellent thermal and electrical conductivity
High energy efficiency due to less heat generation
Suitable for Automatic Optical Inspection (AOI) of solder joints
AEC-Q101 qualified
3. Applications
•
•
•
•
•
•
Load switch
Battery-driven devices
Power management
Charging circuits
LED lighting
Power switches (e.g. motors, fans)
4. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCEO
collector-emitter
voltage
open base
-
-
20
V
IC
collector current
-
-
2
A
ICM
peak collector current
-
-
3
A
Per transistor
single pulse; tp ≤ 1 ms
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PBSS4220PANS
NXP Semiconductors
20 V, 2 A NPN/NPN low VCEsat BISS double transistor
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
collector-emitter
saturation resistance
IC = 1 A; IB = 50 mA; pulsed;
-
-
170
mΩ
Per transistor
RCEsat
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
5. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
1
E1
emitter TR1
2
B1
base TR1
3
C2
collector TR2
4
E2
emitter TR2
5
B2
base TR2
6
C1
collector TR1
7
C1
collector TR1
8
C2
collector TR2
Simplified outline
6
Graphic symbol
5
7
1
8
2
C1
4
B2
TR2
TR1
E1
3
Transparent top view
E2
B1
C2
sym140
DFN2020D-6 (SOT1118D)
6. Ordering information
Table 3.
Ordering information
Type number
PBSS4220PANS
Package
Name
Description
Version
DFN2020D-6
DFN2020D-6: plastic, thermally enhanced ultra thin and
small outline package; no leads; 6 terminals; body 2 x 2
x 0.65 mm
SOT1118D
7. Marking
Table 4.
Marking codes
Type number
Marking code
PBSS4220PANS
3M
PBSS4220PANS
Product data sheet
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20 V, 2 A NPN/NPN low VCEsat BISS double transistor
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VCBO
collector-base voltage
open emitter
-
20
V
VCEO
collector-emitter voltage
open base
-
20
V
VEBO
emitter-base voltage
open collector
-
7
V
IC
collector current
-
2
A
ICM
peak collector current
-
3
A
IB
base current
-
0.3
A
IBM
peak base current
single pulse; tp ≤ 1 ms
-
1
A
Ptot
total power dissipation
Tamb ≤ 25 °C
[1]
-
370
mW
[2]
-
570
mW
[3]
-
530
mW
[4]
-
700
mW
[1]
-
510
mW
[2]
-
780
mW
[3]
-
730
mW
[4]
-
960
mW
Per transistor
single pulse; tp ≤ 1 ms
Per device
Ptot
total power dissipation
Tamb ≤ 25 °C
Tj
junction temperature
-
150
°C
Tamb
ambient temperature
-55
150
°C
Tstg
storage temperature
-65
150
°C
[1]
[2]
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
Device mounted on an FR4 Printed-Circuit Board (PCB), single sided copper, tin-plated; mounting pad for
[3]
[4]
collector 1 cm .
Device mounted on an FR4 Printed-Circuit Board (PCB), 4-layer copper, tin-plated and standard footprint.
Device mounted on an FR4 Printed-Circuit Board (PCB), 4-layer copper, tin-plated; mounting pad for
2
2
collector 1 cm .
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Product data sheet
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PBSS4220PANS
NXP Semiconductors
20 V, 2 A NPN/NPN low VCEsat BISS double transistor
aaa-020830
1
Ptot
(W)
0.8
(4)
0.6
(3)
(2)
0.4
(1)
0.2
0
-75
-25
25
75
125
175
Tamb (°C)
(1) FR4 PCB, single-sided copper, standard footprint
(2) FR4 PCB, 4-layer copper, standard footprint
(3) FR4 PCB, single-sided copper, 1 cm
(4) FR4 PCB, 4-layer copper, 1 cm
Fig. 1.
2
2
Power derating curves
9. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Conditions
thermal resistance
from junction to
ambient
in free air
Min
Typ
Max
Unit
[1]
-
-
338
K/W
[2]
-
-
219
K/W
[3]
-
-
236
K/W
[4]
-
-
179
K/W
[1]
-
-
246
K/W
[2]
-
-
161
K/W
[3]
-
-
172
K/W
[4]
-
-
131
K/W
Per transistor
Rth(j-a)
Per device
Rth(j-a)
thermal resistance
from junction to
ambient
[1]
in free air
[2]
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated, mounting pad for
[3]
[4]
collector 1 cm .
Device mounted on an FR4 Printed-Circuit Board (PCB), 4-layer copper, tin-plated and standard footprint.
Device mounted on an FR4 Printed-Circuit Board (PCB), 4-layer copper, tin-plated, mounting pad for
2
2
collector 1 cm .
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PBSS4220PANS
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20 V, 2 A NPN/NPN low VCEsat BISS double transistor
aaa-020831
103
duty cycle = 1
Zth(j-a)
(K/W)
102
0.50
0.20
0.75
0.33
0.10
0.05
10
0.02
0.01
0
1
10-1
10-5
10-4
10-3
10-2
10-1
1
10
102
tp (s)
103
FR4 PCB, standard footprint
Fig. 2.
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
aaa-020832
103
Zth(j-a)
(K/W)
102
duty cycle = 1
0.75
0.50
0.33
0.20
0.10
10
0.05
0.02
0.01
0
1
10-1
10-5
10-4
10-3
10-2
FR4 PCB, mounting pad for collector 1 cm
Fig. 3.
10-1
1
10
102
tp (s)
103
2
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
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PBSS4220PANS
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20 V, 2 A NPN/NPN low VCEsat BISS double transistor
aaa-020833
103
Zth(j-a)
(K/W)
102
10
duty cycle = 1
0.75
0.50
0.33
0.20
0.10
0.05
0.01
0.02
0
1
10-1
10-5
10-4
10-3
10-2
10-1
1
10
102
tp (s)
103
FR4 PCB, 4-layer copper, standard footprint
Fig. 4.
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
aaa-020834
103
Zth(j-a)
(K/W)
102
10
duty cycle = 1
0.75
0.50
0.33
0.20
0.10
0.05
0.02
0.01
0
1
10-1
10-5
10-4
10-3
10-2
10-1
FR4 PCB, 4-layer copper, mounting pad for collector 1 cm
Fig. 5.
1
10
102
tp (s)
103
2
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
PBSS4220PANS
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20 V, 2 A NPN/NPN low VCEsat BISS double transistor
10. Characteristics
Table 7.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
collector-base cut-off
current
VCB = 16 V; IE = 0 A; Tamb = 25 °C
-
-
100
nA
VCB = 16 V; IE = 0 A; Tj = 150 °C
-
-
50
µA
Per transistor
ICBO
ICES
collector-emitter cut-off VCE = 16 V; VBE = 0 V; Tamb = 25 °C
current
-
-
100
nA
IEBO
emitter-base cut-off
current
VEB = 5 V; IC = 0 A; Tamb = 25 °C
-
-
100
nA
hFE
DC current gain
VCE = 2 V; IC = 100 mA; pulsed;
250
450
-
230
400
-
200
350
-
150
260
-
-
60
90
mV
-
125
170
mV
-
240
320
mV
-
-
170
mΩ
-
0.92
1
V
-
0.96
1.1
V
-
1.18
1.3
V
-
0.77
0.9
V
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
VCE = 2 V; IC = 500 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
VCE = 2 V; IC = 1 A; pulsed; tp ≤ 300 µs;
δ ≤ 0.02; Tamb = 25 °C
VCE = 2 V; IC = 2 A; pulsed; tp ≤ 300 µs;
δ ≤ 0.02
VCEsat
collector-emitter
saturation voltage
IC = 0.5 A; IB = 50 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
IC = 1 A; IB = 50 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
IC = 2 A; IB = 200 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
RCEsat
VBEsat
collector-emitter
saturation resistance
IC = 1 A; IB = 50 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
base-emitter saturation IC = 0.5 A; IB = 50 mA; pulsed;
voltage
tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C
IC = 1 A; IB = 50 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
IC = 2 A; IB = 200 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
VBE
base-emitter voltage
IC = 0.5 A; VCE = 2 V; pulsed;
tp ≤ 300 µs; δfactor ≤ 0.02; Tamb = 25 °C
td
delay time
IC = 1 A; IBon = 50 mA; IBoff = -50 mA;
-
10
-
ns
tr
rise time
Tamb = 25 °C
-
50
-
ns
ton
turn-on time
-
60
-
ns
ts
storage time
-
310
-
ns
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20 V, 2 A NPN/NPN low VCEsat BISS double transistor
Symbol
Parameter
tf
Conditions
Min
Typ
Max
Unit
fall time
-
60
-
ns
toff
turn-off time
-
370
-
ns
fT
transition frequency
-
120
-
MHz
-
13.5
-
pF
VCE = 10 V; IC = 500 mA; f = 100 MHz;
Tamb = 25 °C
Cc
collector capacitance
VCB = 10 V; IE = 0 A; ie = 0 A;
f = 1 MHz; Tamb = 25 °C
aaa-021276
800
aaa-021277
3
hFE
14.4
12.8
11.2
IB (mA) = 16
IC
(A)
9.6
600
2
(1)
6.4
(2)
400
4.8
1.6
1
10
102
0
103
104
IC (mA)
0
1
2
3
4
VCE (V)
5
Tamb = 25 °C
VCE = 2 V
(1) Tamb = 100 °C
Fig. 7.
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 6.
3.2
1
(3)
200
0
10-1
8.0
Collector current as a function of collectoremitter voltage; typical values
DC current gain as a function of collector
current; typical values
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20 V, 2 A NPN/NPN low VCEsat BISS double transistor
aaa-021278
1.2
aaa-021279
1.2
VBEsat
(V)
VBE
(V)
0.9
0.8
(1)
(1)
0.4
(2)
0.6
(2)
(3)
(3)
0.3
0
10-1
Fig. 8.
1
10
102
0
10-1
103
104
IC (mA)
1
10
VCE = 2 V
IC/IB = 20
(1) Tamb = −55 °C
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
(3) Tamb = 100 °C
Base-emitter voltage as a function of collector
current; typical values
Fig. 9.
aaa-021280
1
102
Base-emitter saturation voltage as a function of
collector current; typical values
aaa-021281
1
VCEsat
(V)
103
104
IC (mA)
VCEsat
(V)
(1)
(2)
10-1
10-1
(3)
(1)
(2)
10-2
10-2
(3)
10-3
10-1
1
10
102
10-3
10-1
103
104
IC (mA)
1
VCE = 2 V
Tamb = 25 °C
(1) Tamb =100 °C
(1) IC/IB = 100
(2) Tamb = 25 °C
(2) IC/IB = 50
(3) Tamb = -55 °C
(3) IC/IB = 10
Fig. 10. Collector-emitter saturation voltage as a
function of collector current; typical values
PBSS4220PANS
Product data sheet
10
102
103
104
IC (mA)
Fig. 11. Collector-emitter saturation voltage as a
function of collector current; typical values
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NXP Semiconductors
20 V, 2 A NPN/NPN low VCEsat BISS double transistor
aaa-021282
103
aaa-021283
103
RCEsat
(Ω)
RCEsat
(Ω)
102
102
(1)
10
10
(2)
1
10-1
10-2
10-1
(3)
1
(1)
(2)
(3)
10-1
1
10
102
10-2
10-1
103
104
IC (mA)
1
IC/IB = 20
Tamb = 25 °C
(1) Tamb = 100 °C
(1) IC/IB = 100
(2) Tamb = 25 °C
(2) IC/IB = 50
(3) Tamb = −55 °C
(3) IC/IB = 10
Fig. 12. Collector-emitter saturation resistance as a
function of collector current; typical values
PBSS4220PANS
Product data sheet
10
102
103
104
IC (mA)
Fig. 13. Collector-emitter saturation resistance as a
function of collector current; typical values
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20 V, 2 A NPN/NPN low VCEsat BISS double transistor
11. Test information
IB
input pulse
(idealized waveform)
90 %
IBon (100 %)
10 %
IBoff
output pulse
(idealized waveform)
IC
90 %
IC (100 %)
10 %
t
td
ts
tr
ton
tf
toff
006aaa003
Fig. 14. BISS transistor switching time definition
VBB
RB
(probe)
oscilloscope
450 Ω
VCC
RC
Vo
(probe)
450 Ω
R2
VI
oscilloscope
DUT
R1
mlb826
Fig. 15. Test circuit for switching times
11.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is
suitable for use in automotive applications.
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20 V, 2 A NPN/NPN low VCEsat BISS double transistor
12. Package outline
DFN2020D-6: plastic, thermally enhanced ultra thin and small outline package; no leads;
6 terminals; body 2 x 2 x 0.65 mm
bp
(6x)
v
SOT1118D
A B
D
A
B
A
E
A1
pin 1
index area
detail X
solderable lead end
protrusion maximum 0.035 mm (6x)
D1
(2x)
pin 1
index area
1
C
e1
e1
y1 C
3
Lp
(6x)
cut-off end of
non-fuctional
bonding wire
(8x)
E1
(2x)
6
e
4
e
X
0
1
A
A1
bp
max 0.65 0.04 0.35
nom 0.62
0.30
min 0.59
0.25
mm
2 mm
scale
Dimensions (mm are the original dimensions)
Unit
y
D
D1
E
E1
2.1
2.0
1.9
0.77
0.67
0.57
2.1
2.0
1.9
1.0
0.9
0.8
e
e1
Lp
0.54 0.30
0.65 0.49 0.25
0.44 0.20
v
0.1
y
y1
0.05 0.05
Note
1. Dimension A is including plating thickness.
Outline
version
SOT1118D
sot1118d_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
14-07-16
14-10-16
---
Fig. 16. Package outline DFN2020D-6 (SOT1118D)
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20 V, 2 A NPN/NPN low VCEsat BISS double transistor
13. Soldering
SOT1118D
2.2
1.65
0.2
0.3
0.45
0.35
0.25
0.65
0.53 0.43 0.33
solder lands
0.12 0.22
2.5 2.3
0.9
1
1.1
solder paste
solder resist
0.935
occupied area
0.49
0.31
0.21
0.57
0.67
Dimensions in mm
0.77
1.65
sot1118d_fr
Fig. 17. Reflow soldering footprint for DFN2020D-6 (SOT1118D)
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20 V, 2 A NPN/NPN low VCEsat BISS double transistor
14. Revision history
Table 8.
Revision history
Data sheet ID
Release date
Data sheet status
Change notice
Supersedes
PBSS4220PANS v.1
20151214
Product data sheet
-
-
PBSS4220PANS
Product data sheet
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20 V, 2 A NPN/NPN low VCEsat BISS double transistor
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punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
15. Legal information
15.1 Data sheet status
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Document
status [1][2]
Product
status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Preliminary
[short] data
sheet
Qualification
This document contains data from the
preliminary specification.
Product
[short] data
sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Definition
Please consult the most recently issued document before initiating or
completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the Internet at URL http://www.nxp.com.
15.2 Definitions
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
PBSS4220PANS
Product data sheet
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their
applications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
14 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved
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PBSS4220PANS
NXP Semiconductors
20 V, 2 A NPN/NPN low VCEsat BISS double transistor
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Bitsound, CoolFlux, CoReUse, DESFire, FabKey, GreenChip,
HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, MIFARE,
MIFARE Plus, MIFARE Ultralight, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP
Semiconductors N.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
PBSS4220PANS
Product data sheet
All information provided in this document is subject to legal disclaimers.
14 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved
16 / 17
PBSS4220PANS
NXP Semiconductors
20 V, 2 A NPN/NPN low VCEsat BISS double transistor
16. Contents
1
General description ............................................... 1
2
Features and benefits ............................................1
3
Applications ........................................................... 1
4
Quick reference data ............................................. 1
5
Pinning information ............................................... 2
6
Ordering information ............................................. 2
7
Marking ................................................................... 2
8
Limiting values .......................................................3
9
Thermal characteristics .........................................4
10
Characteristics ....................................................... 7
11
11.1
Test information ................................................... 11
Quality information ............................................. 11
12
Package outline ................................................... 12
13
Soldering .............................................................. 13
14
Revision history ................................................... 14
15
15.1
15.2
15.3
15.4
Legal information .................................................15
Data sheet status ............................................... 15
Definitions ...........................................................15
Disclaimers .........................................................15
Trademarks ........................................................ 16
© NXP Semiconductors N.V. 2015. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 14 December 2015
PBSS4220PANS
Product data sheet
All information provided in this document is subject to legal disclaimers.
14 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved
17 / 17
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