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1-88
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EL2002
December 1995, Rev. D
Low Power, 180MHz Buffer Amplifier
Features
The EL2002 is a low cost monolithic,
high slew rate, buffer amplifier. Built
using the Elantec monolithic
Complementary Bipolar process, this patented buffer has a
-3dB bandwidth of 180MHz, and delivers 100mA, yet draws
only 5mA of supply current. It typically operates from ±15V
power supplies but will work with as little as ±5V.
• 180MHz bandwidth
This high speed buffer may be used in a wide variety of
applications in military, video and medical systems. Typical
examples include fast op-amp output current boosters,
coaxial cable drivers and A/D converter input buffers.
• Short circuit protected
Elantec's products and facilities comply with MIL-I-45208A,
and other applicable quality specifications. For information
on Elantec's processing, see the Elantec document, QRA-1:
Elantec's Processing, Monolithic Integrated Circuits.
• 2000V/µs slew rate
• Low bias current, 3µA typical
• 100mA output current
• 5mA supply current
• Low cost
• Stable with capacitive loads
• Wide supply range ±5V to ±15V
• No thermal runaway
Applications
• Op amp output current booster
Ordering Information
TEMP. RANGE
PACKAGE
PKG. NO.
• Cable/line driver
EL2002ACN
0°C to +75°C
P-DIP
MDP0031
• A/D input buffer
EL2002CM
0°C to +75°C
20-Pin SOL
MDP0027
• Isolation buffer
EL2002CN
0°C to +75°C
P-DIP
MDP0031
PART NUMBER
FN7021
Pinouts
EL2002
(8-PIN DIP)
TOP VIEW
EL2002
(20-PIN SOL)
TOP VIEW
Manufactured under U.S. Patent No. 4,833,424, 4,827,223 U.K. Patent No. 2217134
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL2002
Absolute Maximum Ratings (TA=25°C)
VS Supply Voltage (V+ - V-) . . . . . . . . . . . . . . . . . . . . ±18V or 36V
VIN Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±15V or VS
Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . Continuous
A heat sink is required to keep the junction temperature below the absolute
maximum when the output is short circuited.
If the input exceeds the ratings shown (or the supplies) or if the input to output
voltage exceeds ±7.5V then the input current must be limited to ±50mA. See
the applications section for more information.
TA
TJ
TST
IIN Input Current (See above note) . . . . . . . . . . . . . . . . . . . ±50mA
PD Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Operating Temperature Range . . . . . . . . . . . . . 0°C to +75°C
Operating Junction Temperature. . . . . . . . . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . .-65°C to +150°C
The maximum power dissipation depends on package type, ambient
temperature and heat sinking. See the characteristic curves for more details.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
VS= ±15V, RS = 50Ω, unless otherwise specified.
TEST CONDITIONS
PARAMETER
VOS
DESCRIPTION
Offset Voltage
Input Current
LOAD
TEMP
MIN
TYP
MAX
0
∞
25°C
-15
5
+15
mV
TMIN, TMAX
-20
+20
mV
25°C
-40
+40
mV
TMIN, TMAX
-50
+50
mV
25°C
-10
+10
µA
TMIN, TMAX
-15
+15
µA
25°C
-15
+15
µA
TMIN, TMAX
-20
+20
µA
25°C
1
TMIN, TMAX
0.1
25°C
0.990
TMIN, TMAX
0.985
25°C
0.85
TMIN, TMAX
0.83
25°C
0.83
TMIN, TMAX
0.80
25°C
±10
TMIN, TMAX
±9.5
0
0
RIN
AV1
AV2
AV3
VO
ROUT
Input Resistance
Voltage Gain
Voltage Gain
+12V
±12V
±10V
Voltage Gain
with VS = ±5V
±3V
Output Voltage Swing
±12V
Output Resistance
±2V
∞
∞
∞
100Ω
∞
100Ω
100Ω
100Ω
100Ω
25°C
10
3
5
3
IS
Output Current
Supply Current
±12V
0
(Note 1)
0.998
∞
+100
TMIN, TMAX
±95
25°C
0.93
Supply Rejection (Note 2)
0
∞
0.91
60
TMIN, TMAX
50
V/V
V/V
±11
V
V
13
Ω
15
Ω
+160
mA
mA
5
25°C
V/V
V/V
TMIN, TMAX
PSRR
V/V
V/V
8
25°C
MΩ
MΩ
TMIN, TMAX
IOUT
UNITS
VIN
0
IIN
LIMITS
75
7.5
mA
10
mA
dB
dB
tR
Rise Time
0.5V
100Ω
25°C
2.8
ns
tD
Propagation Delay
0.5V
100Ω
25°C
1.5
ns
2
EL2002
Electrical Specifications
VS= ±15V, RS = 50Ω, unless otherwise specified. (Continued)
TEST CONDITIONS
PARAMETER
SR
DESCRIPTION
Slew Rate (Note 3)
LIMITS
VIN
LOAD
TEMP
MIN
TYP
±10V
100Ω
25°C
1200
2000
UNITS
MAX
NOTES:
1. Force the input to +12V and the output to +10V and measure the output current. Repeat with -12VIN and -10V on the output.
2. VOS is measured at VS+ = +4.5V, VS- = -4.5V and VS+ = +18V, VS- = 18V. Both supplies are changed simultaneously.
3. Slew rate is measured between VOUT = +5V and -5V.
3
V/µs
EL2002
Typical Performance Curves
Offset Voltage
vs Temperature
Voltage Gain
vs Temperature
Output Voltage Swing
vs Temperature
Supply Current
vs Supply Voltage
Voltage Gain
vs Input Voltage
Voltage Gain
vs Source Resistance
Input Bias Current
vs Input Voltage
at Various Temperatures
Input Bias Current
vs Input Voltage
±Slew Rate vs
Supply Voltage
4
EL2002
Typical Performance Curves (Continued)
Slew Rate
vs Load Capacitance
Voltage Gain vs Frequency
for Various Resistive Loads
Voltage Gain
vs Frequency for Various
Capacitive Loads; RL = 100Ω
Voltage Gain
vs Frequency for Various
Capacitive Loads; RL = ∞
Phase Shift vs Frequency
for Various Capacitive Loads
-3dB Bandwidth
vs Supply Voltage
Power Supply Rejection Ratio
vs Frequency
5
Output Impedance vs
Frequency
Reverse Isolation vs Frequency
EL2002
Typical Performance Curves (Continued)
Small Signal Output Resistance
vs Output Current
8-Pin Plastic DIP
Maximum Power Dissipation
vs Ambient Temperature
20-Pin SOL
Maximum Power Dissipation
vs Ambient Temperature
Short Circuit Current
vs Temperature
Large Signal Response
Small Signal Response
OUTPUT
RL = 100Ω
CL = 10pF
f = 20MHz
6
OUTPUT
RL = ∞
CL = 220pF
f = 5MHz
EL2002
Burn-In Circuit
Bypass capacitors from each supply pin to ground are highly
recommended to reduce supply ringing and the interference
it can cause. At a minimum, 1µF tantalum capacitor with
short leads should be used for both supplies.
Input Characteristics
Simplified Schematic
The input to the EL2002 looks like a resistance in parallel
with about 3.5pF in addition to a DC bias current. The DC
bias current is due to the miss-match in beta and collector
current between the NPN and PNP transistors connected to
the input pin. The bias current can be either positive or
negative. The change in input current with input voltage
(RIN) is affected by the output load, beta and the internal
boost. RIN can actually appear negative over portions of the
input range; typical input current curves are shown in the
characteristic curves. Internal clamp diodes from the input to
the output are provided. These diodes protect the transistor
base emitter junctions and limit the boost current during slew
to avoid saturation of internal transistors. The diodes begin
conduction at about ±2.5V input to output differential. When
that happens, the input resistance drops dramatically. The
diodes are rated at 50mA. When conducting they have a
series resistance of about 20Ω. There is also 100Ω in series
with the input that limits input current. Above ±7.5V
differential input to output, additional series resistance
should be added.
Source Impedance
Application Information
The EL2002 is a monolithic buffer amplifier built on Elantec's
proprietary dielectric isolation process that produces NPN
and PNP transistors with essentially identical DC and AC
characteristics. The EL2002 takes full advantage of the
complementary process with a unique circuit topology.
Elantec has applied for two patents based on the EL2001’s
topology. The patents relate to the base drive and feedback
mechanism in the buffer. This feedback makes 2000V/µs
slew rates with 100Ω loads possible with very low supply
current.
Power Supplies
The EL2002 may be operated with single or split supplies
with total voltage difference between 10V (±5V) and 36V
(±18V). It is not necessary to use equal split value supplies.
For example -5V and +12V would be excellent for signals
from -2V to +9V.
7
The EL2002 has good input to output isolation. When the
buffer is not used in a feedback loop, capactive and resistive
sources up to 1MHz present no oscillation problems. Care
must be used in board layout to minimize output to input
coupling. CAUTION: When using high source impedances
(RS > 100kΩ), significant gain errors can be observed due to
output offset, load resistor, and the action of the boost circuit.
See typical performance curves.
EL2002
EL2002 Macromodel
* Connections:
+input
*
|
+Vsupply
*
|
|
-Vsupply
*
|
|
|
output
*
|
|
|
|
.subckt M2002
2
1 4
7
* Input Stage
e1 10 0 2 0 1.0
r1 10 0 1K
rh 10 11 150
ch 11 0 2pF
rc 11 12 100
cc 12 0 3pF
e2 13 0 12 0 1.0
* Output Stage
q1 4 13 14 qp
q2 1 13 15 qn
q3 1 14 16 qn
q4 4 15 19 qp
r2 16 7 1
r3 19 7 1
i1 1 14 2mA
i2 15 4 2mA
* Bias Current
iin+ 2 0 3uA
* Models
.model qn npn(is=5e-15 bf=150 rb=200 ptf=45 tf=0.1nS)
.model qp pnp(is=5e-15 bf=150 rb=200 ptf=45 tf=0.1nS)
.ends
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
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