BeagleBone Rev A3 Schematic

5
REV
A3
D
A3A
4
Description
3
2
1
DATE BY
Production release.
10/21/2011
GC
Updated in conjunction with the release of the SRM. Typos and naming changes. No change
in design.
11/5/2011
GC
C
PAGE NO.
SCHEMATIC PAGE
1
COVER PAGE
2
POWER MANAGEMENT
3
PROCESSOR 1 OF 3
4
PROCESSOR 2 OF 3
5
PROCESSOR 3 OF 3
6
LED, CONFIGURATION AND BUTTON
7
MEMORY
8
ETHERNET AND USB HOST
9
USB CONCENTRATOR
10
SERIAL AND JTAG
11
EXP CONN, uSD, AND LDO
D
C
This schematic is *NOT SUPPORTED* and DOES NOT constitute
a reference design. Only “community” support is allowed
via resources at BeagleBoard.org/discuss.
B
THERE IS NO WARRANTY FOR THIS DESIGN , TO THE EXTENT
PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED
IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
PROVIDE THE DESIGN “AS IS” WITHOUT WARRANTY OF ANY KIND,
EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE
QUALITY AND PERFORMANCE OF THE DESIGN IS WITH YOU. SHOULD
THE DESIGN PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL
NECESSARY SERVICING, REPAIR OR CORRECTION.
B
A
A
Title
Size
BeagleBone Cover Page
Document Number
450-5500-001
Date: Saturday, November 05, 2011
Rev
A3A
B
5
4
3
2
Sheet
1
1
of
11
5
4
3
2
D
VDD_3V3B
7
1
3
6
SYS_5V
IN0
IN1
5
4
OUT1
OUT0
EN
2
2
R1
FLAG
R2
12.1K,1%
4.75K,1%
3
R3
10
DC_IN
NCP349
12
USB_DC
DGND
VDD_3V3A
C1
17
15
C2
R7
R4
1.5K,5%
1.5K,5%
DGND
4.7uF,6.3V 4.7uF,6.3V
DGND
DGND
C4
10uF,10V
P_INT_LDO
48
C5
10uF,10V
P_BYPASS
47
P_MUXIN
14
DGND
9
44
25
28
27
4 PMIC_POW R_EN
11
VDD_3V3B
.1,0805
1
PW R_BUT
I2C0_SCL
I2C0_SDA
BL_ISET2 36
C
AC
SYS1
SYS2
USB
BAT1
BAT2
BAT_SENSE
TS
NC1
NC
BAT
BAT_TEMP
BL_ISET1
BL_IN
BL_SINK2
2
4
6
8
10
1
3
5
7
9
DGND
BAT
BAT_SENSE
BL_ISET2
BL_OUT
BL_SINK1
HDR5x2
C8
21
10uF,10V
C9
10uF,10V
22
C10
10uF,10V
32
10uF,10V
39
C19
10uF,10V
42
BAT
MUX_IN
MUX_OUT
PWR_EN
RESET
PB_IN
SCL
SDA
VIO
PGOOD
LDO_PGOOD
WAKEUP
INT
ISINK1
ISINK2
ISET2
16
C3
10uF,10V
P_MUXOUT
18
26
46
13
45
VDCDC1
VIN_DCDC2
L2
VDCDC2
VIN_DCDC3
L3
LDO3_IN
LDO3
LDO4_IN
LDO4
2
10uF,10V
VINLDO
VLDO1
34
33
BL_SINK1
BL_SINK2
38
BL_OUT
37
BL_IN
SN74LVC2G00DCU
VLDO2
R9
100K,1%
PMIC_PGOOD
LDO_PGOOD
W AKEUP
R15
PPAD
PGND
4
TESTPT1
TP15
1
20
P_L1
VDCDC1
23
P_L2
24
VDCDC2
2
2.2uH,2.6A
L2
1
31
P_L3
29
VDCDC3
1
VDD_1V8
VDDS_DDR
L1
R12
0,1%
2
2.2uH,2.6A
R204
LDO3
R19
43
LDO4
R121
0,1%
TP18
TESTPT1
TP17TESTPT1
VDD_CORE
2
2.2uH,2.6A
40
R14
VDD_MPU
0,1%
L3
R13
0,1%
VDD_3V3A
0,1%
3.25V
VDD_3V3B
C165
10uF,10V
0,1%
[email protected]
C14
C15
10uF,10V
10uF,10V 22uF,6.3V
C16
B
DGND
C135
10uF,10V DGND
1
C20
POWER LED
R6
DGND
PW R_LED
GRN
PW R_LEDR
470,5%
D1
DGND
598-8170-107F
TP14
TESTPT1
0,1%
MHOLE
3
3
C7
4.7uF,50V
49
TPS65217b
30
MTG2
TESTPT1
41
AGND
TP1
DGND
0,1%
DGND
MHOLE
4
AIN7
100K,1%
2.2uF,6.3V
MTG1
D
C
19
3
3
0,DNI
DGND
L1
PMIC_INT
R10
P_W AKEUP
R11
PMIC_INT_SRC
VRTC
C17
R8
ISET1
VIN_DCDC1
0,1%
DGND
BAT_SENSE
BAT_TEMP
BYPASS
VDCDC3
C18
100K,1%
PMIC_INT_PU
R28
DGND
EXPANSION HEADER
B
7
VDD_3V3A
L4
P6
4
5
6
11
INT_LDO
FB_WLED
BL_ISET1 35
7
8
U14A
2
R203
U2
DGND
8
1
PJ-200A
4,7
4,7
1
4
P5
1
2
SYS_VOLT
U1
GND
5V DC POWER
3
VDD_5V
MTG3
DGND
AGND
DGND
MHOLE
AGND
MTG4
DGND
MHOLE
A
A
Title
Size
BeagleBone Power Management
Document Number
450-5500-001
Date: Saturday, November 05, 2011
Rev
A3A
B
5
4
3
2
Sheet
1
2
of
11
5
4
3
2
1
VRTC
C21
VRTC
R141
10K,1%
LDO_PGOOD
2
1
C23
8
U17A
DGND
7
2
25pF,50V
VRTC_DET
1.1K,1%
25pF,50V
2
OSC1_OUT1
C24
D
Y1
4
SN74AUP2G08
1
R17
5
VRTC_DETB
6
U17B
VRTC_DET_OUT
RTC_PORZ
0,1%,DNI
SN74AUP2G08
C22
0.01uf,16V
DGND
32.768KHz MC-306
R143
3
4
8
0.01uf,16V
R18
DGND
12.1K,1%
D
2 PMIC_PGOOD
R20
4
24MHz,DNI
Y3
2
3
Y2
3
DGND
4
OSC0_OUT1
R21
1M,1%
1
1
18pF,50V
24MHz
2
C26
C27
18pF,50V
DGND
R22
0,1%
0,1%
DDR_D[15..0]
DDR_D[15..0]
7
7
7
7
B
OSC0_OUT
GND_OSC0
U11
V11
OSC1_IN
A6
OSC1_OUT
GND_OSC1
A4
A5
R29
R25
R30
R26
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
PDDR_A0
PDDR_A1
PDDR_A2
PDDR_A3
PDDR_A4
PDDR_A5
PDDR_A6
PDDR_A7
PDDR_A8
PDDR_A9
PDDR_A10
PDDR_A11
PDDR_A12
PDDR_A13
DDR_BA0
DDR_BA1
DDR_BA2
R41
R42
R43
33,0402
33,0402
33,0402
PDDR_BA0
PDDR_BA1
PDDR_BA2
F3
H1
E4
C3
C2
B1
D5
E2
D4
C1
F4
F2
E3
H3
H4
D3
C4
E1
B3
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
PDDR_D0
PDDR_D1
PDDR_D2
PDDR_D3
PDDR_D4
PDDR_D5
PDDR_D6
PDDR_D7
PDDR_D8
PDDR_D9
PDDR_D10
PDDR_D11
PDDR_D12
PDDR_D13
PDDR_D14
PDDR_D15
M3
M4
N1
N2
N3
N4
P3
P4
J1
K1
K2
K3
K4
L3
L4
M1
R60
R61
R62
R63
R64
R65
R66
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
PDDR_CLK
PDDR_CLKn
PDDR_CKE
PDDR_CSn
PDDR_CASn
PDDR_RASn
PDDR_WEn
D2
D1
G3
H2
F1
G4
B2
R67
R68
R69
R70
R71
R72
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
PDDR_DQM0
PDDR_DQS0
PDDR_DQSN0
PDDR_DQM1
PDDR_DQS1
PDDR_DQSN1
M2
P1
P2
J2
L1
L2
R73
33,0402
PDDR_ODT
DDR_RESETN
G1
G2
J3
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_BA[2..0]
DDR_BA[2..0]
C
7
V10
7
7
7
7
7
7
7
DDR_CLK
DDR_CLKn
DDR_CKE
DDR_CSn
DDR_CASn
DDR_RASn
DDR_WEn
7
7
DDR_DQM0
DDR_DQS0
DDR_DQSN0
DDR_DQM1
DDR_DQS1
DDR_DQSN1
7
DDR_ODT
TP3
VDDS_DDR
7
R74
TESTPT1
J4
2.2K,1%
DDR_VTP
7
OSC0_IN
U5A
OSC0_IN
PORZ
NRESET_INOUT
RTC_PORZ
OSC0_OUT
VSS_OSC0
NNMI
EVENT_INTR0/TIMER4/CLKOUT1/SPI1_CS1/PR1PRU1R31_16/EMU2/GPIO0_19
EVENT_INTR1/TCLKIN/CLKOUT2/TIMER7/PR1PRU0_PRUR31_16/EMU3/GPIO0_20
OSC1_IN
OSC1_OUT
VSS_RTC
NTRST
TMS
TDI
TCK
TDO
EMU0/GPIO3_7
EMU1/GPIO3_8
DDR_A[13..0]
DDR_A[13..0]
VDD_3V3A
DGND
R24
GND_OSC0
7
100K,1%
C25
0.01uf,16V
DDR_VREF
R75
2.2K,1%
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_A14
DDR_A15
DDR_BA0
DDR_BA1
DDR_BA2
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_CK
DDR_NCK
DDR_CKE
DDR_CSN0
DDR_CASN
DDR_RASN
DDR_WEn
DDR_DQM0
DDR_DQS0
DDR_DQSN0
DDR_DQM1
DDR_DQS1
DDR_DQSN1
DDR_ODT
DDR_RESETN
DDR_VTP
GPMC_CLK/LCD_MEM_CLK/GPMC_WAIT1/MMC2_CLK/PRT1_MII1_TXEN/MCASP0_FSR/GPIO2_1
GPMC_CSN0/GPIO1_29
GPMC_CSN1/GPMC_CLK/MMC1_CLK/PRT1EDIO_DATA_IN6/PRT1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_12/PR1_PRU1_PRU_R31_12/GPIO1_30
GPMC_CSN2/GPMC_BE1N/MMC1_CMD/PR1_EDIO_DATA_IN7/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_13/PR1_PRU1_PRU_R31_13/GPIO1_31
GPMC_CSN3/MMC2_CMD/PR1_MDIO_DATA/GPIO2_0
GPMC_WEN/TIMER6/GPIO2_4
GPMC_OEN_REN/TIMER7/EMU4/GPIO2_3
GPMC_ADVN_ALE/TIMER4/GPIO2_2
GPMC_BE0N_CLE/TIMER5/GPIO2_5
GPMC_BE1N/GMII2_COL/GPMC_CSN6/MMC2_DAT3/GPMC_DIR/PR1_MII1_RXLINK/MCASP0_ACLKR/GPIO1_28
GPMC_WAIT0/GM112_CRS/GPMC_CSN4/RMII2_CRS_DV/MMC1_SDCD/PR1_MII1_RXDV/UART4_RXD/GPIO0_30
GPMC_WPN/GMII2_RXERR/GPMC_CSN5/RMII2_RXERR/MMC2_SDCD/PR1_MDIO_MDCLK/UART4_TXD/GPIO0_31
GPMC_AD0/MMC1_DAT0//////GPIO1_0
GPMC_AD1/MMC1_DAT1//////GPIO1_1
GPMC_AD2/MMC1_DAT2//////GPIO1_2
GPMC_AD3/MMC1_DAT3//////GPIO1_3
GPMC_AD4/MMC1_DAT4//////GPIO1_4
GPMC_AD5/MMC1_DAT5//////GPIO1_5
GPMC_AD6/MMC1_DAT6//////GPIO1_6
GPMC_AD7/MMC1_DAT7//////GPIO1_7
GPMC_AD8/LCD_DATA23/MMC1_DAT0/MMC2_DAT4/EHRPWM2A/PR1_MII_MT0_CLK//GPIO0_22
GPMC_AD9/LCD_DATA22/MMC1_DAT1/MMC2_DAT5/EHRPWM2B/PR1_MII0_CRS//GPIO0_23
GPMC_AD10/LCD_DATA21/MMC1_DAT2/MMC2_DAT6/EHRPWM2_TRIPZONE_INPUT/PR1_MII0_TXEN//GPIO0_26
GPMC_AD11/LCD_DATA20/MMC1_DAT3/MMC2_DAT7/EHRPWM2_SYNCI_O/PR1_MII0_TXD3//GPIO0_27
GPMC_AD12/LCD_DATA19/MMC1_DAT4/MMC2_DAT0/EQEP2A_IN/PR1_MII0_TXD2/PR1_PRU0_PRU_R30_14/GPIO1_12
GPMC_AD13/LCD_DATA18/MMC1_DAT5/MMC2_DAT1/EQEP2B_IN/PR1_MII0_TXD1/PR1_PRU0_PRU_R30_15/GPIO1_13
GPMC_AD14/LCD_DATA17/MMC1_DAT6/MMC2_DAT2/EQEP2_INDEX/PR1_MII0_TXD0/PR1_PRU0_PRU_R31_14/GPIO1_14
GPMC_AD15/LCD_DATA16/MMC1_DAT7/MMC2_DAT3/EQEP2_STROBE/PR1_ECAP0_ECAP_CAPIN_APWM_O/PR1_PRU0_PRU_R31_15/GPIO1_15
GPMC_A0/GMII2_TXEN/RGMII2_TCTL/RMII2_TXEN/GPMC_A16/PR1_MII_MT1_CLK/EHRPWM1_TRIPZONE_INPUT/GPIO1_16
GPMC_A1/GMII2_RXDV/RGMII2_RCTL/MMC2_DAT0/GPMC_A17/PR1_MII1_TXD3/EHRPWM1_SYNCI_O/GPIO1_17
GPMC_A2/GMII2_TXD3/RGMII2_TD3/MMC2_DAT1/GPMC_A18/PR1_MII1_TXD2/EHRPWM1A/GPIO1_18
GPMC_A3/GMII2_TXD2/RGMII2_TD2/MMC2_DAT2/GPMC_A19/PR1_MII1_TXD1/EHRPWM1B/GPIO1_19
GPMC_A4/GMII2_TXD1/RGMII2_TD1/RMII2_TXD1/GPMC_A20/PR1_MII1_TXD0/EQEP1A_IN/GPIO1_20
GPMC_A5/GMII2_TXD0/RGMII2_TD0/RMII2_TXD0/GPMC_A21/PR1_MII1_RXD3/EQEP1B_IN/GPIO1_21
GPMC_A6/GMII2_TXCLK/RGMII2_TCLK/MMC2_DAT4/GPMC_A22/PR1_MII1_RXD2/EQEP1_INDEX/GPIO1_22
GPMC_A7/GMII2_RXCLK/RGMII2_RCLK/MMC2_DAT5/GPMC_A23/PR1_MII1_RXD1/EQEP1_STROBE/GPIO1_23
GPMC_A8/GMII2_RXD3/RGMII2_RD3/MMC2_DAT6/GPMC_A24/PR1_MII1_RXD0/MCASP0_ACLKX/GPIO1_24
GPMC_A9/GMII2_RXD2/RGMII2_RD2/MMC2_DAT7/GPMC_A25/PR1_MII_MR1_CLK/MCASP0_FSX/GPIO1_25
GPMC_A10/GMII2_RXD1/RGMII2_RD1/RMII2_RXD1/GPMC_A26/PR1_MII1_CRS/MCASP0_AXR0/GPIO1_26
GPMC_A11/GMII2_RXD0/RGMII2_RD0/RMII2_RXD0/GPMC_A27/PR1_MII1_RXER/MCASP0_AXR1/GPIO1_27
MMC0_CLK/GPMC_A24/UART3_CTSN/UART2_RXD/DCAN1_TX/PR1_PRU0_PRU_R30_12/PR1_PRU0_PRU_R31_12/GPIO2_30
MMC0_CMD/GPMC_A25/UART3_RTSN/UART2_TXD/DCAN1_RX/PR1_PRU0_PRU_R30_13/PR1_PRU0_PRU_R31_13/GPIO2_31
MMC0_DAT0/GPMC_A23/UART5_RTSN/UART3_TXD/UART1_RIN/PR1_PRU0_PRU_R30_11/PR1_PRU0_PRU_R31_11/GPIO2_29
MMC0_DAT1/GPMC_A22/UART5_CTSN/UART3_RXD/UART1_DTRN/PR1_PRU0_PRU_R30_10/PR1_PRU0_PRU_R31_10/GPIO2_28
MMC0_DAT2/GPMC_A21/UART4_RTSN/TIMER6/UART1_DSRN/PR1_PRU0_PRU_R30_9/PR1_PRU0_PRU_R31_9/GPIO2_27
MMC0_DAT3/GPMC_A20/UART4_CTSN/TIMER5/UART1_DCDN/PR1_PRU0_PRU_R30_8/PR1_PRU0_PRU_R31_8/GPIO2_26
B15
A10
B5
B18
A15
D14
B10
C11
B11
A12
A11
C14
B14
V12
V6
U9
V9
T13
U6
T7
R7
T6
U18
T17
U17
U7
V7
R8
T8
U8
V8
R9
T9
U10
T10
T11
U12
T12
R12
V13
U13
R13
V14
U14
T14
R14
V15
U15
T15
V16
U16
T16
V17
G17
G18
G16
G15
F18
F17
R23
10K,1%
DGND
11,8
SYS_RESETn
R27
0,1%
10,6
SYS_WARMRESETn
2
PMIC_INT
10
XDMA_EVENT_INTR0
10,11
CLKOUT2
JTAG_TRSTn
JTAG_TMS
JTAG_TDI
JTAG_TCK
JTAG_TDO
JTAG_EMU0
JTAG_EMU1
10
10
10
10
10
10
10
GPIO2_1
GPIO1_29
GPIO1_30
GPIO1_31
TIMER6
TIMER7
TIMER4
TIMER5
GPIO1_28
UART4_RXD
UART4_TXD
11
11
11
11
11
11
11
11
11
11
11
GPIO1_0
GPIO1_1
GPIO1_2
GPIO1_3
GPIO1_4
GPIO1_5
GPIO1_6
GPIO1_7
EHRPWM2A
EHRPWM2B
GPIO0_26
GPIO0_27
GPIO1_12
GPIO1_13
GPIO1_14
GPIO1_15
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
GPIO1_16
GPIO1_17
EHRPWM1A
EHRPWM1B
11
11
11
11
USR0
USR1
USR2
USR3
6
6
6
6
USB1_OC
8
MMC0_CLKO
MMC0_CMD
MMC0_DAT0
MMC0_DAT1
MMC0_DAT2
MMC0_DAT3
C
11
11
11
11
11
11
B
VREFSSTL
AM335X_ZCZ
R76
50,1%
DGND
DGND
A
A
Title
Size
BeagleBone Processor 1 of 3
Document Number
Rev
A3A
C
450-5500-001
Date: Saturday, November 05, 2011
5
4
3
2
1
Sheet
3
of
11
5
4
3
2
1
VRTC
R77
4.75K,1%
U5B
VDD_ADC
C6
C5
2 PMIC_POWR_EN
2
WAKEUP
GMII1_TXCLK/UART2_RXD/RGMII1_TCLK/MMC0_DAT7/MMC1_DAT0/UART1_DCDN/MCASP0_ACLKX/GPIO3_9
GMII1_TXD0/RMII1_TXD0/RGMII1_TD0/MCASP1_AXR2/MCASP1_ACLKR/EQEP0B_IN/MMC1_CLK/GPIO0_28
GMII1_TXD1/RMII1_TXD1/RGMII1_TD1/MCASP1_FSR/MCASP1_AXR1/EQEP0A_IN/MMC1_CMD/GPIO0_21
GMII1_TXD2/DCAN0_RX/RGMII1_TD2/UART4_TXD/MCASP1_AXR0/MMC2_DAT2/MCASP0_AHCLKX/GPIO0_17
GMII1_TXD3/DCAN0_TX/RGMII1_TD3/UART4_RXD/MCASP1_FSX/MMC2_DAT1/MCASP0_FSR/GPIO0_16
GMII1_TXEN/RMII1_TXEN/RGMII1_TCTL/TIMER4/MCASP1_AXR0/EQEP0_INDEX/MMC2_CMD/GPIO3_3
GMII1_CRS/RMII1_CRS_DV/SPI1_D0/I2C1_SDA/MCASP1_ACLKX/UART5_CTSN/UART2_RXD/GPIO3_1
GMII1_COL/RMII2_REFCLK/SPI1_SCLK/UART5_RXD/MCASP1_AXR2/MMC2_DAT3/MCASP0_AXR2/GPIO3_0
PMIC_POWER_EN
EXT_WAKEUP
D
11
11
11
11
11
11
11
2
R78
0,1%
C28
0.01uf,16V
C29
0.01uf,16V
B6
C7
B7
A7
C8
B8
A8
C9
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
B9
A9
VREFP_ADC
VREFN_ADC
A17
B17
B16
A16
C15
11
UART2_RXD
11
UART2_TXD
11
I2C1_SDA
11
I2C1_SCL
10,11 CD/EMU4
C30
0.001uf,50V
10
10
10
10
GNDA_ADC
GNDA_ADC
11
11
11
11
C
E16
E15
E18
E17
UART0_RX
UART0_TX
UART0_RTS
UART0_CTS
D15
D16
D18
D17
UART1_TXD
UART1_RXD
I2C2_SDA
I2C2_SCL
2,7
2,7
I2C0_SCL
I2C0_SDA
9
9
USB0_DP
USB0_DM
C16
C17
TP4
9
USB0_VBUS
8
8
USB1_DP
USB1_DM
8
USB1_ID
8 USB1_DRVVBUS
USB1_VBUS
8
11
USB0_ID
TESTPT1
N17
N18
M15
P16
F16
P15
R17
R18
P18
P17
F15
T18
GPIO0_7
C18
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
GMII1_RXCLK/UART2_TXD/RGMII1_RCLK/MMC0_DAT6/MMC1_DAT1/UART1_DSRN/MCASP0_FSX/GPIO3_10
GMII1_RXD0/RMII1_RXD0/RGMII1_RD0/MCASP1_AHCLKX/MCASP1_AHCLKR/MCASP1_ACLKR/MCASP0_AXR3/GPIO2_21
GMII1_RXD1/RMII1_RXD1/RGMII1_RD1/MCASP1_AXR3/MCASP1_FSR/EQEP0_STROBE/MMC2_CLK/GPIO2_20
GMII1_RXD2/UART3_TXD/RGMII1_RD2/MMC0_DAT4/MMC1_DAT3/UART1_RIN/MCASP0_AXR1/GPIO2_19
GMII1_RXD3/UART3_RXD/RGMII1_RD3/MMC0_DAT5/MMC1_DAT2/UART1_DTRN/MCASP0_AXR0/GPIO2_18
GMII1_RXERR/RMII1_RXERR/SPI1_D1/I2C1_SCL/MCASP1_FSX/UART5_RTSN/UART2_TXD/GPIO3_2
GMII1_RXDV/LCD_MEMORY_CLK/RGMII1_RCTL/UART5_TXD/MCASP1_ACLKX/MMC2_DAT0/MCASP0_ACLKR/GPIO3_4
VREFP
VREFN
SPI0_SCLK/UART2_RXD/I2C2_SDA/EHRPWM0A/PR1_UART0_CTS_N/PR1_EDIO_SOF/EMU2/GPIO0_2
RMII1_REFCLK/XDMA_EVENT_INTR2/SPI1_CS0/UART5_TXD/MCASP1_AXR3/MMC0_POW/MCASP1_AHCLKX/GPIO0_29
SPI0_D0/UART2_TXD/I2C2_SCL/EHRPWM0B/PR1_UART0_RTS_N/PR1_EDIO_LATCH_IN/EMU3/GPIO0_3
MDIO_CLK/TIMER5/UART5_TXD/UART3_RTSN/MMC0_SDWP/MMC1_CLK/MMC2_CLK/GPIO0_1
SPI0_D1/MMC1_SDWP/I2C1_SDA/EHRPWM0_TRIPZONE_INPUT/PR1_UART0_RXD/PR1_EDIO_DATA_IN0/PR1_EDIO_DATA_OUT0/GPIO0_4
MDIO_DATA/TIMER6/UART5_RXD/UART3_CTSN/MMC0_SDCD/MMC1_CMD/MMC2_CMD/GPIO0_0
SPI0_CS0/MMC2_SDWP/I2C1_SCL/EHRPWM0_SYNCI_O/PR1_UART0_TXD/PR1_EDIO_DATA_IN1/PR1_EDIO_DATA_OUT1/GPIO0_5
SPI0_CS1/UART3_RXD/ECAP1_IN_PWM1_OUT/MMC0_POW/XDMA_EVENT_INTR2/MMC0_SDCD/EMU4/GPIO0_6
LCD_DATA0/GPMC_A0//EHRPWM2A//PR1_PRU1_PRU_R30_0/PR1_PRU1_PRU_R31_0/GPIO2_6
UART0_TXD/SPI1_CS1/DCAN0_RX/I2C2_SCL/ECAP1_IN_PWM1_OUT/PR1_PRU1_PRU_R30_15/PR1_PRU1_PRU_R31_15/GPIO1_11
LCD_DATA1/GPMC_A1//EHRPWM2B//PR1_PRU1_PRU_R30_1/PR1_PRU1_PRU_R31_1/GPIO2_7
UART0_RXD/SPI1_CS0/DCAN0_TX/I2C2_SDA/ECAP2_IN_PWM2_OUT/PR1_PRU1_PRU_R30_14/PR1_PRU1_PRU_R31_14/GPIO1_10
LCD_DATA2/GPMC_A2//EHRPWM2_TRIPZONE_INPUT//PR1_PRU1_PRU_R30_2/PR1_PRU1_PRU_R31_2/GPIO2_8
UART0_CTSN/UART4_RXD/DCAN1_TX/I2C1_SDA/SPI1_D0/TIMER7/PR1_EDC_SYNC0_OUT/GPIO1_8
LCD_DATA3/GPMC_A3//EHRPWM2_SYNCI_O//PR1_PRU1_PRU_R30_3/PR1_PRU1_PRU_R31_3/GPIO2_9
UART0_RTSN/UART4_TXD/DCAN1_RX/I2C1_SCL/SPI1_D1/SPI1_CS0/PR1_EDC_SYNC1_OUT/GPIO1_9
LCD_DATA4/GPMC_A4//EQEP2A_IN//PR1_PRU1_PRU_R30_4/PR1_PRU1_PRU_R31_4/GPIO2_10
LCD_DATA5/GPMC_A5//EQEP2B_IN//PR1_PRU1_PRU_R30_5/PR1_PRU1_PRU_R31_5/GPIO2_11
LCD_DATA6/GPMC_A6/PR1_EDIO_DATA_IN6/EQEP2_INDEX/PR1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_6/PR1_PRU1_PRU_R31_6/GPIO2_12
LCD_DATA7/GPMC_A7/PR1_EDIO_DATA_IN7/EQEP2_STROBE/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_7/PR1_PRU1_PRU_R31_7/GPIO2_13
LCD_DATA8/GPMC_A12/EHRPWM1_TRIPZONE_INPUT/MCASP0_ACLKX/UART5_TXD/PR1_MII0_RXD3/UART2_CTSN/GPIO2_14
UART1_TXD/MMC2_SDWP/DCAN1_RX/I2C1_SCL//PR1_UART0_TXD/PR1_PRU0_PRU_R31_16/GPIO0_15
LCD_DATA9/GPMC_A13/EHRPWM1_SYNCI_O/MCASP0_FSX/UART5_RXD/PR1_MII0_RXD2/UART2_RTSN/GPIO2_15
UART1_RXD/MMC1_SDWP/DCAN1_TX/I2C1_SDA//PR1_UART0_RXD/PR1_PRU1_PRU_R31_16/GPIO0_14
LCD_DATA10/GPMC_A14/EHRPWM1A/MCASP0_AXR0//PR1_MII0_RXD1/UART3_CTSN/GPIO2_16
UART1_CTSN/TIMER6/DCAN0_TX/I2C2_SDA/SPI1_CS0/PR1_UART0_CTS_N/PR1_EDC_LATCH0_IN/GPIO0_12
LCD_DATA11/GPMC_A15/EHRPWM1B/MCASP0_AHCLKR/MCASP0_AXR2/PR1_MII0_RXD0/UART3_RTSN/GPIO2_17
UART1_RTSN/TIMER5/DCAN0_RX/I2C2_SCL/SPI1_CS1/PR1_UART0_RTS_N/PR1_EDC_LATCH1_IN/GPIO0_13
LCD_DATA12/GPMC_A16/EQEP1A_IN/MCASP0_ACLKR/MCASP0_AXR2/PR1_MII0_RXLINK/UART4_CTSN/GPIO0_8
LCD_DATA13/GPMC_A17/EQEP1B_IN/MCASP0_FSR/MCASP0_AXR3/PR1_MII0_RXER/UART4_RTSN/GPIO0_9
I2C0_SCL/TIMER7/UART2_RTSN/ECAP1_IN_PWM1_OUT////GPIO3_6
LCD_DATA14/GPMC_A18/EQEP1_INDEX/MCASP0_AXR1/UART5_RXD/PR1_MII_MR0_CLK/UART5_CTSN/GPIO0_10
I2C0_SDA/TIMER4/UART2_CTSN/ECAP2_IN_PWM2_OUT////GPIO3_5
LCD_DATA15/GPMC_A19/EQEP1_STROBE/MCASP0_AHCLKX/MCASP0_AXR3/PR1_MII0_RXDV/UART5_RTSN/GPIO0_11
USB0_DP
USB0_DM
USB0_CE
USB0_ID
USB0_DRVVBUS/GPIO0_18
USB0_VBUS
USB1_DP
USB1_DM
USB1_CE
USB1_ID
USB1_DRVVBUS/GPIO3_13
USB1_VBUS
LCD_PCLK/GPMC_A10//PR1_EDIO_DATA_IN4/PR1_EDIO_DATA_OUT4/PR1_PRU1_PRU_R30_10/PR1_PRU1_PRU_R31_10/GPIO2_24
LCD_VSYNC/GPMC_A8//PR1_EDIO_DATA_IN2/PR1_EDIO_DATA_OUT2/PR1_PRU1_PRU_R30_8/PR1_PRU1_PRU_R31_8/GPIO2_22
LCD_HSYNC/GPMC_A9//PR1_EDIO_DATA_IN3/PR1_EDIO_DATA_OUT3/PR1_PRU1_PRU_R30_9/PR1_PRU1_PRU_R31_9/GPIO2_23
LCD_AC_BIAS_EN/GPMC_A11//PR1_EDIO_DATA_IN5/PR1_EDIO_DATA_OUT5/PR1_PRU1_PRU_R30_11/PR1_PRU1_PRU_R31_11/GPIO2_25
MCASP0_AHCLKX/EQEP0_STROBE/MCASP0_AXR3/MCASP1_AXR1/EMU4/PR1_PRU0_PRU_R30_7/PR1_PRU0_PRU_R31_7/GPIO3_21
MCASP0_ACLKX/EHRPWM0A//SPI1_SCLK/MMC0_SDCD/PR1_PRU0_PRU_R30_0/PR1_PRU0_PRU_R31_0/GPIO3_14
MCASP0_FSX/EHRPWM0B//SPI1_D0/MMC1_SDCD/PR1_PRU0_PRU_R30_1/PR1_PRU0_PRU_R31_1/GPIO3_15
MCASP0_AXR0/EHRPWM0_TRIPZONE_INPUT//SPI1_D1/MMC2_SDCD/PR1_PRU0_PRU_R30_2/PR1_PRU0_PRU_R31_2/GPIO3_16
MCASP0_AHCLKR/EHRPWM0_SYNCI_O/MCASP0_AXR2/SPI1_CS0/ECAP2_IN_PWM2_OUT/PR1_PRU0_PRU_R30_3/PR1_PRU0_PRU_R31_3/GPIO3_17
MCASP0_ACLKR/EQEP0A_IN/MCASP0_AXR2/MCASP1_ACLKX/MMC0_SDWP/PR1_PRU0_PRU_R30_4/PR1_PRU0_PRU_R31_4/GPIO3_18
MCASP0_FSR/EQEP0B_IN/MCASP0_AXR3/MCASP1_FSX/EMU2/PR1_PRU0_PRU_R30_5/PR1_PRU0_PRU_R31_5/GPIO3_19
MCASP0_AXR1/EQEP0_INDEX//MCASP1_AXR0/EMU3/PR1_PRU0_PRU_R30_6/PR1_PRU0_PRU_R31_6/GPIO3_20
K18
K17
K16
K15
J18
J16
H17
H16
L18
M16
L15
L16
L17
J15
J17
H18 U5_H18
M18
M17
R201
33,0402
R1
R2
R3
R4
T1
T2
T3
T4
U1
U2
U3
U4
V2
V3
V4
T5
V5
U5
R5
R6
A14
A13
B13
D12
C12
B12
C13
D13
RMII1_TXCLK
RMII1_TXD0
RMII1_TXD1
RMII1_TXD2
RMII1_TXD3
RMII1_TXEN
RMII1_CRS_DV
RMII1_COL
8
8
8
8
8
8
8
8
RMII1_RXCLK
RMII1_RXD0
RMII1_RXD1
RMII1_RXD2
RMII1_RXD3
RMII1_RXERR
RMII1_RXDV
8
8
8
8
8
8
8
D
RMII1_REFCLK 8
8
MDIO_CLK
8
MDIO_DATA
GPIO2_6
GPIO2_7
GPIO2_8
GPIO2_9
GPIO2_10
GPIO2_11
GPIO2_12
GPIO2_13
UART5_TXD
UART5_RXD
UART3_CTSN
UART3_RTSN
UART4_CTSN
UART4_RTSN
UART5_CTSN
UART5_RTSN
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
GPIO2_24
GPIO2_22
GPIO2_23
GPIO2_25
11
11
11
11
GPIO3_21
SPI1_SCLK
SPI1_D0
SPI1_D1
SPI1_CS0
11
11
11
11
11
GPIO3_19
11
C
ECAP0_IN_PWM0_OUT/UART3_TXD/SPI1_CS1/PR1_ECAP0_ECAP_CAPIN_APWM_O/SPI1_SCLK/MMC0_SDWP/XDMA_EVENT_INTR2/GPIO0_7
AM335X_ZCZ
B
B
A
A
Title
Size
BeagleBone Processor 2 of 3
Document Number
Rev
A3A
C
450-5500-001
Date: Saturday, November 05, 2011
5
4
3
2
1
Sheet
4
of
11
5
4
3
2
1
VDD_3V3A
VDD_CORE
C50
10uF,10V
F6
F7
G6
G7
G10
H11
J12
K6
K8
K12
L6
L7
L8
L9
M11
M13
N8
N9
N12
N13
DGND
VDD_MPU
0.01uf,16V
C46
C47
VDD_MPU
0.01uf,16V
C45
0.01uf,16V
C44
10uF,10V
DGND
VDD_PLL
TP5
FB1
2
VDD_MPUON
TESTPT1
CAP_VDD_SRAM_CORE
C82
0.01uf,16V
0.01uf,16V
C81
C85
C80
C84
N15
N16
VDD_3V3A
VDD_1V8
DGND
1uF,10V
DGND
C83
C
0.01uf,16V
VDD_1V8
1uF,10V
0.01uf,16V
C73
0.01uf,16V
C72
M14
R15
R16
N14
E7
DGND
VDD_1V8
DGND
E5
F5
G5
H5
J5
K5
L5
C86
0.01uf,16V
VDDS_DDR
C89
10uF,10V
D9
H15
D10
CAP_VDD_SRAM_MPU D11
CAP_VBB_MPU C10
E9
150OHM800mA
1uF,10V
VDD_1V8
1
F10
F11
F12
F13
G13
H13
J13
A2
DGND
C90
0.01uf,16V
C91
0.01uf,16V
C92
C93
0.01uf,16V 0.01uf,16V
C94
C95
0.01uf,16V 0.01uf,16V
C96
VDD_CORE1
VDD_CORE2
VDD_CORE3
VDD_CORE4
VDD_CORE5
VDD_CORE6
VDD_CORE7
VDD_CORE8
VDD_CORE9
VDD_CORE10
VDD_CORE11
VDD_CORE12
VDD_CORE13
VDD_CORE14
VDD_CORE15
VDD_CORE16
VDD_CORE17
VDD_CORE18
VDD_CORE19
VDD_CORE20
VDDSHV1
VDDSHV1
VDDSHV2
VDDSHV2
VDDSHV3
VDDSHV3
C51
0.01uf,16V
P7
P8
C43
0.01uf,16V
C52
0.01uf,16V
VDDSHV4
VDDSHV4
VDDSHV5
VDDSHV5
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
CAP_VDD_SRAM_CORE
VDDS_PLL_MPU
VDDS_SRAM_MPU_BB
CAP_VDD_SRAM_MPU
CAP_VBB_MPU
VDDS_SRAM_CORE_BG
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDA3P3V_USB0
VDDA1P8V_USB0
VSSA_USB
C56
P12
P13
C57
0.01uf,16V 0.01uf,16V
DGND
H14
J14
VDDA_ADC
VSSA_USB
VSSA_ADC
VPP
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_RTC
CAP_VDD_RTC
ENZ_KALDO_1P8V
VDDS_OSC
TESTOUT
C59
0.01uf,16V
0.01uf,16V
K14
L14
C60
E10
E11
E12
E13
F14
G14
N5
P5
P6
C61
0.01uf,16V
0.01uf,16V
DGND
C70
C62
0.01uf,16V
C71
C63
C64
C65
C75
0.01uf,16V
C76
0.01uf,16V
C77
0.01uf,16V
C78
0.01uf,16V
C68
C69
C79
0.01uf,16V
DGND
D8
FB2
2
1
1
C
FB3
2
150OHM800mA
VDD_CORE
VDD_PLL
C87
0.01uf,16V
VRTC
VDD_RTC
ENZ_KALDO_1P8V
GNDA_ADC
R11
GNDA_ADC
DGND
C88
0.01uf,16V
DGND
VDD_PLL
TP6
TESTOUT
TESTPT1
0.01uf,16V
VDD_1V8
150OHM800mA
M5
R10
A3
C67
VDD_1V8
C74
E8
D7
D6
B4
C66
0.01uf,16V 0.01uf,16V 0.01uf,16V0.01uf,16V0.01uf,16V 0.01uf,16V 0.01uf,16V 10uF,10V
0.01uf,16V
E6
E14
F9
K13
N6
P9
P14
VDD_ADC
VDDA3P3V_USB1
VDDA1P8V_USB1
D
P10
P11
C58
VDD_MPU1
VDD_MPU2
VDD_MPU3
VDD_MPU4
VDD_MPU5
VDD_MPU6
VDD_MPU7
VDD_MPU_MON
AM335X_ZCZ
0.01uf,16V
C42
0.01uf,16V
DGND
U5C
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C48
R79
A1
A18
F8
G8
G9
G11
G12
H6
H7
H8
H9
H10
H12
J6
J7
J8
J9
J10
J11
K7
K9
K10
K11
L10
L11
L12
L13
M6
M7
M8
M9
M10
M12
N7
N10
N11
V1
V18
C55
0.01uf,16V
C54
0.01uf,16V
C53
0.01uf,16V
C41
0.01uf,16V
C40
0.01uf,16V
C39
0.01uf,16V
C38
0.01uf,16V
C37
0.01uf,16V
C36
0.01uf,16V
C49
0.01uf,16V
C35
0.01uf,16V
C34
0.01uf,16V
10uF,10V
10uF,10V
C33
0.01uf,16V
D
C32
0.01uf,16V
VDD_CORE
C31
C97
1uF,10V
C98
C99
0.01uf,16V
0.01uf,16V
10K,1%
DGND
GND_OSC0
DGND
DGND
B
B
A
A
Title
Size
BeagleBone Processr 3 of 3
Document Number
Rev
A3A
C
450-5500-001
Date: Saturday, November 05, 2011
5
4
3
2
1
Sheet
5
of
11
5
4
3
2
1
SYS_5V
FB4
150OHM800mA
R95
VDD_LED
100K,1%,DNI
B
4
LEDDC
3
Q2A
5
DMC56404
R118
100K,1%
Q2B
DMC56404
R119
100K,1%
DGND
4
LEDCC
6
2
DMC56404
DGND
DGND
DGND
USR1
USR2
USR3
B
RESET BUTTON
S1
B3U-1100
3
1
2
C
DGND
DGND
3
3
3
598-8170-107F
1
LEDBC
3
Q1B
DGND
DGND
LEDDA
LEDCA
LEDBA
LEDAA
LEDAC
100K,1%
100K,1%,DNI
100K,1%
100K,1%
100K,1%
100K,1%
100K,1%
100K,1%
100K,1%
100K,1%
100K,1%
100K,1%,DNI
6
R117
100K,1%
598-8170-107F
47k
BOOT ORDER....MMC....SPI....UART....USB......24MHZ
DMC56404
47k
R116
100K,1%
DGND
5
Q1A
D5
47k
100K,1%
2
USR0
10k
3
598-8170-107F
TP13 TESTPT1
D4
598-8170-107F
!"#'
10k
User LED's
D3
R99
470,5%
!"#&
TP12 TESTPT1
D2
Boot Configuration
!"#%
TP11 TESTPT1
1
R115
100K,1%
R114
100K,1%,DNI
R113
100K,1%,DNI
R112
100K,1%,DNI
R111
100K,1%,DNI
R110
100K,1%,DNI
R109
100K,1%,DNI
R108
100K,1%,DNI
R107
100K,1%,DNI
R106
100K,1%,DNI
R105
100K,1%
R104
100K,1%,DNI
R103
100K,1%
100K,1%
R102
TP10 TESTPT1
R98
470,5%
47k
100K,1%,DNI
!"#$
10k
100K,1%,DNI
DGND
R97
470,5%
R96
470,5%
C100
4.7uF,6.3V
10k
100K,1%,DNI
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
GRN
C
GPIO2_6
GPIO2_7
GPIO2_8
GPIO2_9
GPIO2_10
GPIO2_11
GPIO2_12
GPIO2_13
UART5_TXD
UART5_RXD
UART3_CTSN
UART3_RTSN
UART4_CTSN
UART4_RTSN
UART5_CTSN
UART5_RTSN
GRN
SYS_BOOT0
SYS_BOOT1
SYS_BOOT2
SYS_BOOT3
SYS_BOOT4
SYS_BOOT5
SYS_BOOT6
SYS_BOOT7
SYS_BOOT8
SYS_BOOT9
SYS_BOOT10
SYS_BOOT11
SYS_BOOT12
SYS_BOOT13
SYS_BOOT14
SYS_BOOT15
GRN
R101
D
GRN
R100
D
100K,1%
1
R94
R93
R92
R91
R90
R89
R88
R87
R86
R85
R84
R83
R82
R81
R80
2
VDD_3V3A
SYS_W ARMRESETn
10,3
C101
1uF,10V,DNI
DGND
DGND
A
A
Title
Size
BeagleBone LED, Configuration and Reset
Document Number
450-5500-001
Date: Saturday, November 05, 2011
Rev
A3A
B
5
4
3
2
Sheet
1
6
of
11
5
4
3
3
3
3
3
3
3
D
3
3
3
3
3
3
3
C
J8
K8
K2
L8
K7
L7
K3
DDR_CLK
DDR_CLKn
DDR_CKE
DDR_CSn
DDR_RASn
DDR_CASn
DDR_W En
DDR_D[15..0]
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
C114
C115
UDQS
UDQSn
UDM
LDQSn
LDQS
LDM
VDD
VDD
VDD
VDD
VDD
E3
P9
J3
N1
A3
R7
R3
E2
A2
VDDS_DDR
C113
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A1
E1
M9
R1
J9
VDDS_DDR
C112
CK
CKn
CKE
CSn
RASn
CASn
WEn
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
C117
C116
0.01uf,16V
0.01uf,16V 0.01uf,16V0.01uf,16V0.01uf,16V
VSS
VSS
VSS
VSS
VSS
RFU2
RFU1
NC1
NC2
22uF,6.3V
2
DDR_A[13..0]
U6
B7
A8
B3
E8
F7
F3
DDR_DQS1
DDR_DQSN1
DDR_DQM1
DDR_DQSN0
DDR_DQS0
DDR_DQM0
3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
(RFU)A13
BA0
BA1
BA2
ODT
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VDDL
VSSDL
VREF
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
L2
L3
L1
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13R 0,1%
3
D
DDR_A13
R120
DDR_BA[2..0]
DDR_BA0
DDR_BA1
DDR_BA2
3
Variable & MAC Memory
2,4
K9
3
DDR_ODT
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
1
2,4
6
5
I2C0_SCL
I2C0_SDA
U7
SCL
SDA
1
2
3
VDDS_DDR
A0
A1
A2
VCC
VSS
WP
VDD_3V3B
8
C102
0.1uf,16V
4
7
WP
R210
10K,1%,DNI DGND
CAT24C256W
256KX8
DGND
VDDS_DDR
H8
B2
D2
F2
H2
A7
E7
B8
D8
F8
C103
C104
0.01uf,16V
0.01uf,16V
C105
C106
0.01uf,16V
0.01uf,16V
C
C107
0.01uf,16V
C108
0.01uf,16V
C109
C110
0.01uf,16V
0.01uf,16V
C111
0.01uf,16V
DGND
J1
VDDS_DDR
J7
J2
DDR_VREF
3
MT47H128M16RT-25E:C
DDR2 SDRAM
B
DGND
C118
0.01uf,16V
DGND
DGND
B
DGND
A
A
Title
Size
BeagleBone DDR2 Memory
Document Number
450-5500-001
Date: Saturday, November 05, 2011
Rev
A3A
B
5
4
3
2
Sheet
1
7
of
11
5
4
3
2
1
VDD_PHYA
VDD_3V3B
C119
0.1uf,16V
DGND
C122
0.1uf,16V
PHY_XTAL1
1M,1%,DNI
PHY_XTAL2
R199
4
XTAL1/CLKIN
XTAL2
15pF,DNI
15pF,DNI
15pF,DNI
DGND
DGND
R129
R130
R133
R134
49.9,1%
49.9,1%
49.9,1%
R16
C129
R128 470,5%
PHYX
C131
2
11
12
10
9
YEL_C
GRN_C
YELA
GRNA
15pF,DNI
DGND
DGND
8
13
14
YELC SHD1
YELA SHD2
GRNC
GRNA
DGND
WE_7499010211A
DGND
LED1/REGOFF
LED2/nINTSEL
RBIAS
3
2
RBIAS
QFN32_5X5MM_EP3P3MM
VDD_PHYA
R142
0,1%
0.022uF,10V
PHYAD0 MODE2 MODE1
18
32
C130
VDD_3V3B
ACTIVE WHEN LINK PRESENT.
BLINKS OFF DURING ACTIVITY.
ACTIVE WHEN AT 100MB
LED2
R145
12.1K,1%
RXD0/MODE0
Y4
C
470,5%
R138
TCT_RCT
nINT/TXER/TXD4
33
R144
10,1%
49.9,1%
6
VDDCR
VDD2A
VDD1A
VDDIO
1
27
12
5
RCLKIN
0,1%
C128
7
NC
GND
1
RXD1/MODE1
MODE0 RMISEL PHYAD1 PHYAD0
ESD_RING
.1,0805
DGND
DGND
R215
R140
nRST
C127
TCT
TD+
TDRD+
RDRCT
10K,1%,DNI
SYS_RESETn
C126
R213
11,3
19
RXP
RXN
10K,1%,DNI
R200 0,1%,DNI
31
30
5
3
6
1
2
4
R124
COL/CRS_DV/MODE2
CRS_DV/MODE2
U15
TXCLK
TXEN
LAN8710A
TXD0
TXD1
TXD2
TXD3
COL/CRS_DV/MODE2
CRS
TXP
TXN
R211
100,1%
100,1%
20
21
22
23
24
25
15
14
RXP
RXN
29
28
10K,1%,DNI
R207
R139
TXCLK
TXP
TXN
R123
100,1%
MDIO
MDC
RXD3/PHYAD2
RXD2/RMIISEL
RXD1/MODE1
RXD0/MODE0
RXDV
RXCLK/PHYAD1
RXER/RXD4/PHYAD0
10K,1%
R206
16
17
8
9
10
11
26
7
13
D
P10
10K,1%
100,1%
100,1%
100,1%
100,1%
100,1%
100,1%
100,1%
RXD3/PHYAD2
RXD2/RMIISEL
RXD1/MODE1
RXD0/MODE0
RXDV
REFCLKO
RXER/PHYAD0
ETHERNET
CONNECTOR
R126
RMII1_TXCLK
RMII1_TXEN
RMII1_TXD0
RMII1_TXD1
RMII1_TXD2
RMII1_TXD3
RMII1_COL
RMII1_CRS_DV
10,1%,DNI
R205
R153
R132
R135
R208
R136
R137
VDD_PHYA
C125
1uF,10V
DGND
GND_EP
4
4
4
4
4
4
4
4
R209
MDIO_DATA
MDIO_CLK
RMII1_RXD3
RMII1_RXD2
RMII1_RXD1
RMII1_RXD0
RMII1_RXDV
RMII1_RXCLK
RMII1_RXERR
1.5K,5%
DGND
RMII1_REFCLK
DGND
C124
470pF
50V
5%
C123
0.1uf,16V
R131
D
4
DGND
C121
4.7uF,6.3V
PHY_VDDCR
DGND
4
4
4
4
4
4
4
4
4
C120
0.1uf,16V
10K,1%R122
10K,1%R122
2
FB5
10K,1%,DNI
1
150OHM800mA
C
CRS_DV/MODE2
25.000MHz
XTAL2_5X3P2_SMD
C132
30pF,50V
DGND
DGND
30pF,50V
RXER/PHYAD0
RXD2/RMIISEL
RXD3/PHYAD2
DGND
USB1_VBUS
4
4
4
P2
4 USB-A Conn. - 87520-xx1xx
1 VBUS
2 D3 D+
4 GND
USB1_DM
USB1_DP
USB1_ID
SHIELD
SHIELD
5
R5
R198
R212
R214
R216
10K,1%,DNI
10K,1%
10K,1%
10K,1%
R127
10K,1%,DNI
10K,1%,DNI
R125
nINT/RXCLK/PHYAD1
10K,1%
DGND
DGND
6
SYS_5V
U9
B
2
3
4
1
4 USB1_DRVVBUS
+
R147
10K,1%
C133
100uF,6.3V
IN OUT
IN OUT
EN OUT
GND OC
PAD
DGND
8
7
6
5
9
VDD_3V3B
TPS2051 (DGN)
R146
0,1%
3
DGND
DGND
DGND
DGND
USB1_OC
DGND
1
2
R148
10K,1%
3
D+
DID
B
USB HOST CONNECTOR
U10
VBUS
NC
GND
6
5
C134
0.01uf,16V
4
TPD4S012
DGND
A
A
Title
Size
BeagleBone Ethernet and USB Host
Document Number
Rev
A3A
C
450-5500-001
Date: Saturday, November 05, 2011
5
4
3
2
1
Sheet
8
of
11
5
4
3
2
1
USBDP_UP
USBDM_UP
VBUS_DET
R151
100K,1%
Downstream 1 USBDP_DN1
8
DGND
USBDM_DN1
OCS1
PRTPWR1
DownstreamUSBDP_DN2
2
12
OCS2
USBDM_DN2
PRTPWR2
VDD_3V3B
NON_REM[0:1]/nc
NC
NON_REM1
SUSP_IND/NON_REM0
R156
100K,1%
17
RESETn
C
6
C136
0.1uf,16V
DGND
RESET
RBIAS
DGND
1
28
7
3
2
11
4
10
FT_VBUS
10
USB0_DP
4
USB0_DM
4
13
19
NON_REM1
NON_REM2
VDD33
VDDCRREF/VDD33
SYS_5V
G5
D
mini USB-B
R152
4.75K,1%
U16B
4
SN74LVC2G07DCK
4
USB0_VBUS
VDD_3V3B
26
HUB_BIAS
R155
10K,1%,DNI
TP7
R157
12.1K,1%
DGND
VDD_3V3B
R158
10K,1%
14
10
R159
100K,1%
TESTPT1
C
DGND
DGND
C139
C140
0.1uf,16V 4.7uF,6.3V
VDD33
VDD33
VDDPLLREF/VDD33
2
FT_DM
P3
R154
10K,1%,DNI
XTALIN/CLKIN
24MHz
3
Y5
R160
24
10
5
Common
TEST
FT_DP
USB PC
CONNECTOR
USB0_VBUS_PW R
C138
XTALIN
18pF,50V
G1
ID
D+
DVB
3
DGND
C137
9
USBDP_UP
USBDM_DN
7
D
18
22
21
G2
VBUS_DET
5
4
3
2
1
USB2412_QFN28
Upstream
G3
U11
G4
R149
100K,1%
6
USB_DC
8
USB_DC
4
20
27
DGND
DGND
0.1uf,16V
DGND
1M,1%,DNI
XTALOUT
23
HS_IND
16
TP8
18pF,50V
C142
0.1uf,16V
C143
0.1uf,16V
XTALOUT
HS_IND
CRFILT
9
CRFILT
DGND
TESTPT1
DGND
B
C141
0.1uf,16V
1
C144
R161
rsvd3
0,1%
15
29
VSS
PLLFILT
25
PLLFILT
C145
VSS(FLAG)
0.1uf,16V,DNI
B
C146
0.1uf,16V,DNI
DGND
DGND
DGND
A
A
Title
Size
BeagleBone USB Concentrator
Document Number
450-5500-001
Date: Saturday, November 05, 2011
Rev
A3A
B
5
4
3
2
Sheet
1
9
of
11
5
4
VDD_3V3B
1
150OHM800mA
1
150OHM800mA
0.1uf,16V
1
DGND
VDD_3V3B
2 FB6 VDD_FTVPLL
R162
VDD_3V3B
C157
VDD_3V3B
VDD_3V3B
0.1uf,16V
C149
0.1uf,16V
D
2 FB7
VDD_FTVPHY
C147 0.1uf,16V
2 FB8
DGND
VDD_FTREGIN
DGND
4.75K,1%
C148
0.1uf,16V
C150
0.1uf,16V
C151
0.1uf,16V
5
5
D
0.1uf,16V
C158
2
8
1
150OHM800mA
C161
3
U14B
3
FT_VBUS 6
FT_SRESETn
1
U16A
6
FT_SRESETB
SN74LVC2G07DCK
R163
0,1%
3,6
SYS_W ARMRESETn
2
C164
50
VDD_1V8FT
49
VREGIN
VREGOUT
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
DGND
R167
DGND
12.1K,1% FT_REF
6
C
9
9
7
8
FT_DM
FT_DP
C153 27pF,50V
DGND
XTIN
2
REF
USBDM
USBDP
ACBUS0
ACBUS1
ACBUS2
ACBUS3
ACBUS4
ACBUS5
ACBUS6
ACBUS7
OSCIN
Y6
12.000MHz
50ppm
VDD_3V3B
C155 27pF,50V
DGND
XTOUT
R175
R174
R173
U13
B
6
2
VCC
5
4
3
1
CS
SK
DIN
DOUT
93LC56B_SOT23-6
DGND
14
63
62
61
F_EECS
F_EESK
F_EEDATA
F_EEDOUT
GND
10K,1%
10K,1%
FT_RESETn
2.2K,1%
3
13
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
OSC0
RESET
BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
BCBUS5
BCBUS6
BCBUS7
EECS
EECLK
EEDATA
10
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
DGND
AGND
2.2K,1%
1
5
11
15
25
35
47
51
R188
10K,1%
VDD_3V3B
DGND
16
17
18
19
21
22
23
24
F_ADBUS0
F_ADBUS1
F_ADBUS2
F_ADBUS3
F_ADBUS4
R164
R165
R166
R168
R169
0,1%
0,1%
0,1%
0,1%
0,1%
F_ADBUS6
R170
0,1%
26
27
28
29
30
32
33
34
F_ADBUS5
38
39
40
41
43
44
45
46
48
52
53
54
55
57
58
59
R172
SUSPEND
0,1%
DGND
FT_SRESET
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRSTn
3
3
3
3
3
JTAG_EMU0
3
JTAG_EMU1
3
C
VDD_3V3B
F_ADBUS7
R171
UART0_TX
UART0_RX
UART0_CTS
UART0_RTS
0,1%
4
4
4
4
VDD_3V3B
R179
4.75K,1%
VDD_3V3B
C154
R176
DGND
VDD_3V3B
R178
R180
4.75K,1%
R181
10K,1%,DNI
FT_VBUS
9
OPTIONAL JTAG
0.01uf,16V
DGND
TEST
PWREN
R187
DGND
20
31
42
56
VCCIOA
VCCIOB
VCCIOB
VCCIOD
U12
12
37
64
0.1uf,16V 0.1uf,16V
VCOREC
VCOREB
VCOREA
C163
0.1uf,16V
4
9
C162
VPHY
VPLL
C152
4.7uF,6.3V
4
SN74LVC2G00DCU
3XDMA_EVENT_INTR0
11,4
CD/EMU4
R182
R183
R185
100,1%,DNI
0,DNI
0,DNI
1
3
5
7
0,DNI
RTCK 9
11
0,DNI
TCK
13
15
EMU_RSTn
17
EMU2R
19
EMU4R
P7
TMS
TRSTn
TDI
TDIS
TVDD
NC
TDO
GND
TCKRTN GND
TCK
GND
EMU0
EMU1
SRST
GND
EMU2
EMU3
EMU4
GND
2
4
6
8
10
12
14
16
18
20
TDIS
R177
0,DNI
B
DGND
EMU3R
R184
CLKOUT2
0,DNI
CTI JTAG,DNI
11,3
R186
4.75K,1%
C156
60
0.1uf,16V
36
DGND
DGND
DGND
FT2232LQFN64
DGND
A
A
Title
Size
BeagleBone Serial and JTAG
Document Number
450-5500-001
Date: Saturday, November 05, 2011
Rev
A3A
B
5
4
3
2
Sheet
1
10 of 11
5
4
3
2
P8
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4,6
4,6
4,6
4,6
4,6
4,6
4,6
4,6
D
P9
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
GPIO1_6
GPIO1_2
TIMER4
TIMER5
GPIO1_13
EHRPW M2B
GPIO1_15
GPIO0_27
EHRPW M2A
GPIO1_30
GPIO1_4
GPIO1_0
GPIO2_22
GPIO2_23
UART5_CTSN
UART4_RTSN
UART4_CTSN
UART5_TXD
GPIO2_12
GPIO2_10
GPIO2_8
GPIO2_6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
GPIO1_7
GPIO1_3
TIMER7
TIMER6
GPIO1_12
GPIO0_26
GPIO1_14
GPIO2_1
GPIO1_31
GPIO1_5
GPIO1_1
GPIO1_29
GPIO2_24
GPIO2_25
UART5_RTSN
UART3_RTSN
UART3_CTSN
UART5_RXD
GPIO2_13
GPIO2_11
GPIO2_9
GPIO2_7
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4,6
4,6
4,6
4,6
4,6
4,6
4,6
4,6
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
DGND
VDD_3V3EXP
VDD_5V
SYS_5V
PW R_BUT
UART4_RXD
UART4_TXD
GPIO1_16
I2C1_SCL
I2C2_SCL
UART2_TXD
GPIO1_17
GPIO3_21
GPIO3_19
SPI1_D0
SPI1_SCLK
AIN4
AIN6
AIN2
AIN0
CLKOUT2
2
3
3
3
4
4
4
3
4
4
4
4
4
4
4
4
10,3
FEMALE HEADER 2x23
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
DGND
VDD_3V3EXP
VDD_5V
SYS_5V
3,8
SYS_RESETn
3
GPIO1_28
3
EHRPW M1A
3
EHRPW M1B
4
I2C1_SDA
4
I2C2_SDA
4
UART2_RXD
4
UART1_TXD
4
UART1_RXD
4
SPI1_CS0
4
SPI1_D1
VDD_ADC
AIN5
AIN3
AIN1
GPIO0_7
FEMALE HEADER 2x23
DGND
VDD_3V3A
DGND
8
2
5
9
4
C6
VDD_3V3A
4.7uF,6.3V
VDD_3V3EXP
IN
NC1
EN
PAD
GND
OUT
NC2
NC3
FB
1
6
7
3
TPS73701DRBR
R195
R194
R193
C159
R192
C
SYS_VOLT
U8
R191
4
4
4
4
EXPANSION HEADER
DGND
EXPANSION HEADER
R190
D
GNDA_ADC
DGND
C
1
3V3EXP_FB
R150
52.3K,1%
C166
0.1uf,16V
R189
30.1K,1%
10uF,10V
C160
0.1uf,16V
DGND
DGND
3
3
3
3
3
3
10K,1%
10K,1%
10K,1%
10K,1%
B
10K,1%
10K,1%
DGND
B
1
2
3
4
5
6
7
8
MMC0_DAT2
MMC0_DAT3
MMC0_CMD
MMC0_CLKO
MMC0_DAT0
MMC0_DAT1
P4
DAT2
GND
CD/DAT3
CD
CMD
GND3
VDD
GND4
CLOCK
GND5
VSS
GND6
DAT0
GND7
DAT1 microSDGND8
9
10
11
12
13
14
15
16
DGND
SD_CD
R196
10K,1%
VDD_3V3B
R197
0,1%
SCHA5B0200
uSD CONNECTOR
DGND
10,4
CD/EMU4
A
A
Title
Size
BeagleBone Expansion Headers, SD/MMC.and LDO
Document Number
450-5500-001
Date: Saturday, November 05, 2011
Rev
A3A
B
5
4
3
2
Sheet
1
11 of 11