DATASHEET

EL5100, EL5101, EL5300
®
Data Sheet
May 3, 2007
FN7330.3
200MHz Slew Enhanced VFA
Features
The EL5100, EL5101, and EL5300 represent high-speed
voltage feedback amplifiers based on the current feedback
amplifier architecture. This gives the typical high slew rate
benefits of a CFA family along with the stability and ease of
use associated with the VFA type architecture. This family is
available in single, dual, and triple versions, with 200MHz,
400MHz, and 700MHz versions. This family operates on
single 5V or ±5V supplies from minimum supply current. The
EL5100 and EL5300 also feature an output enable function,
which can be used to put the output in to a high-impedance
mode. This enables the outputs of multiple amplifiers to be
tied together for use in multiplexing applications.
• Pb-free plus anneal available (RoHS compliant)
• Specified for 5V or ±5V applications
• Power-down to 17µA/amplifier
• -3dB bandwidth = 200MHz
• ±0.1dB bandwidth = 20MHz
• Low supply current = 2.5mA
• Slew rate = 2200V/µs
• Low offset voltage = 4mV max
• Output current = 100mA
• AVOL = 1000
• Diff gain/phase = 0.08%/0.1°
Applications
• Video amplifiers
• PCMCIA applications
• A/D drivers
• Line drivers
• Portable computers
• High speed communications
• RGB applications
• Broadcast equipment
• Active filtering
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2006, 2007. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL5100, EL5101, EL5300
Ordering Information
PART
MARKING
PART NUMBER
TAPE AND REEL
PACKAGE
PKG.
DWG. #
EL5100IS
5100IS
-
8 Ld SOIC (150 mil)
MDP0027
EL5100IS-T7
5100IS
7”
8 Ld SOIC (150 mil)
MDP0027
EL5100IS-T13
5100IS
13”
8 Ld SOIC (150 mil)
MDP0027
EL5100ISZ (Note)
5100ISZ
-
8 Ld SOIC (150 mil) (Pb-free)
MDP0027
EL5100ISZ-T7 (Note)
5100ISZ
7”
8 Ld SOIC (150 mil) (Pb-free)
MDP0027
EL5100ISZ-T13 (Note)
5100ISZ
13”
8 Ld SOIC (150 mil) (Pb-free)
MDP0027
EL5100IW-T7
y
7” (3k pcs)
6 Ld SOT-23
MDP0038
EL5100IW-T7A
y
7” (250 pcs)
6 Ld SOT-23
MDP0038
EL5101IW-T7
2
7” (3k pcs)
5 Ld SOT-23
MDP0038
EL5101IW-T7A
2
7” (250 pcs)
5 Ld SOT-23
MDP0038
EL5300IU
5300IU
-
16 Ld QSOP (150 mil)
MDP0040
EL5300IU-T7
5300IU
7”
16 Ld QSOP (150 mil)
MDP0040
EL5300IU-T13
5300IU
13”
16 Ld QSOP (150 mil)
MDP0040
EL5300IUZ (Note)
5300IUZ
-
16 Ld QSOP (150 mil) (Pb-free)
MDP0040
EL5300IUZ-T7 (Note)
5300IUZ
7”
16 Ld QSOP (150 mil) (Pb-free)
MDP0040
EL5300IUZ-T13 (Note)
5300IUZ
13”
16 Ld QSOP (150 mil) (Pb-free)
MDP0040
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN7330.3
May 3, 2007
EL5100, EL5101, EL5300
Pinouts
EL5101
(5 LD SOT-23)
TOP VIEW
EL5100
(6 LD SOT-23)
TOP VIEW
OUT 1
VS- 2
6 VS+
+ -
IN+ 3
OUT 1
5 ENABLE
VS- 2
4 IN-
IN+ 3
IN- 2
IN+ 3
8 ENABLE
+
VS- 4
+ 4 IN-
EL5300
(16 LD QSOP)
TOP VIEW
EL5100
(8 LD SOIC)
TOP VIEW
NC 1
5 VS+
INA+ 1
7 VS+
CEA 2
6 OUT
VS- 3
5 NC
CEB 4
16 INA+
14 VS+
+
-
INB+ 5
INC+ 8
3
13 OUTB
12 INB-
NC 6
CEC 7
15 OUTA
11 NC
+
-
10 OUTC
9 INC-
FN7330.3
May 3, 2007
EL5100, EL5101, EL5300
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . 13.2V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±4V
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mA
Maximum Slewrate from VS+ to VS- . . . . . . . . . . . . . . . . . . . . 1V/µs
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature Range . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
VS = ±5V, GND = 0V, TA = +25°C, VCM = 0V, VOUT = 0V, VENABLE = GND or OPEN, Unless Otherwise
Specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
-4
1
4
mV
VOS
Offset Voltage
TCVOS
Offset Voltage Temperature Coefficient
Measured from TMIN to TMAX
IB
Input Bias Current
VIN = 0V
-6
2
6
µA
IOS
Input Offset Current
VIN = 0V
-2.5
0.5
2.5
µA
TCIOS
Input Bias Current Temperature
Coefficient
Measured from TMIN to TMAX
PSRR
Power Supply Rejection Ratio
CMRR
Common Mode Rejection Ratio
CMIR
8
µV/°C
8
nA/°C
70
90
dB
VCM from -3V to +3V
60
75
dB
Common Mode Input Range
Guaranteed by CMRR test
-3
RIN
Input Resistance
VIN = -3V to +3V
0.7
CIN
Input Capacitance
IS,ON
Supply Current - Enabled
Per amplifier
2.1
2.5
2.9
mA
IS,OFF
Supply Current - Shut Down
VS+, per amplifier
-5
0
5
µA
VS-, per amplifier
5
17
25
µA
12
V
+3
V
1.2
MΩ
1
pF
PSOR
Power Supply Operating Range
AVOL
Open Loop Gain
RL = 1kΩ to GND, VOUT from -2.5V to +2.5V
55
60
dB
VOP
Positive Output Voltage Swing
RL = 150Ω to GND
3.2
3.4
V
RL = 1kΩ to GND
3.6
3.8
V
VON
Negative Output Voltage Swing
IOUT
Output Current
VIH-EN
ENABLE pin Voltage for Power Up
VIL-EN
ENABLE pin Voltage for Shut Down
IEN
Enable Pin Current
4
3.3
RL = 150Ω to GND
-3.4
-3.2
V
RL = 1kΩ to GND
-3.8
-3.6
V
RL = 10Ω to 0V
±60
±100
mA
VS+ -4
Enabled, VEN = 0V
-1
Disabled, VEN = 5V
5
V
17
VS+ -1
V
1
µA
25
µA
FN7330.3
May 3, 2007
EL5100, EL5101, EL5300
Closed Loop AC Electrical SpecificationsVS = ±5V, TA = 25°C, VENABLE = 0V, AV = +1, RF = 0Ω, RL = 150Ω to GND, unless
otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
BW
-3dB Bandwidth (VOUT = 200mVP-P)
VS = ±5V, AV = 1, RF = 0Ω
150
200
SR
Slew Rate
RL = 100Ω, VOUT = -3V to +3V, AV = +2
1500
2200
tR,tF
Rise Time, Fall Time
±0.1V step
2.8
ns
OS
Overshoot
±0.1V step
10
%
tPD
Propagation Delay
±0.1V step
3.2
ns
tS
0.1% Settling Time
VS = ±5V, RL = 500Ω, AV = 1, VOUT = ±2.5V
20
ns
dG
Differential Gain
AV = 2, RL = 150Ω, VINDC = -1 to +1V
0.08
%
dP
Differential Phase
AV = 2, RL = 150Ω, VINDC = -1 to +1V
0.1
°
eN
Input Noise Voltage
f = 10kHz
10
nV/√Hz
iN
Input Noise Current
f = 10kHz
7
pA/√Hz
tDIS
Disable Time
180
ns
tEN
Enable Time
650
ns
MHz
4500
V/µs
Typical Performance Curves
5
5
3
4
±1.75
±2.0
2
±4.0
±5.0
±3.0
1
0
-1
-2
-3
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
4
AV=+1
RL=50Ω
SUPPLY=±5.0V
3
2
AV=+1
RL=500Ω
CIN-=0pF
SUPPLY=±5.0V
2.2pF
1
0pF
0
-1
-2
-3
-4
-4
-5
100K
1M
10M
100M
-5
100K
1G
1M
FIGURE 1. GAIN vs FREQUENCY FOR VARIOUS CL
1G
5
17.1pF
AV=+2
RL=150Ω
CL=2.2pF
RF=383Ω
4
11.5pF
5.8pF
1
0
-1
-2
2.2pF
-3
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
2
100M
FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS CL
5
3
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
4
8.8pF
6.6pF
4.4pF
3
2
FREQUENCY (Hz)
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS CIN-
5
0pF
-2
-3
-4
600M
2.2pF
0
-5
100M
4.4pF
-1
-5
100K
10M
6.6pF
1
-4
1M
AV=+2
RF=RG=383Ω
CL=2.2pF
RL=150Ω
100K
1M
10M
100M
600M
FREQUENCY (Hz)
FIGURE 4. GAIN vs FREQUENCY FOR VARIOUS CIN-
FN7330.3
May 3, 2007
EL5100, EL5101, EL5300
Typical Performance Curves (Continued)
5
3
2
A =+1
4 RV=500Ω
L
3 CL=2.5pF
CIN-=0pF
2 SUPPLY=±5.0V
1
13.4pF
AV=+5
RF=383Ω
CL=2.2pF
RL=150Ω
4
7.8pF
1
0
-1
2.2pF
-2
-3
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
5
-5
100K
100Ω
-1
50Ω
-2
-3
20Ω
1M
10M
-5
100K
100M
1M
FIGURE 5. GAIN vs FREQUENCY FOR VARIOUS CIN (-)
5
1
750Ω
150Ω
2.0Ω
0
-1
-2
-3
1M
3
10M
100M
1500Ω
2
1000Ω
1
0
500Ω
-1
400Ω
-2
200Ω
-3
-4
-5
1.5Ω
-5
100K
100K
1M
FIGURE 7. GAIN vs FREQUENCY FOR VARIOUS RL
1
0
1.5kΩ
-1
715Ω
-2
383Ω
-3
-4
-5
600M
VS=±5V
AV=+2
RF=RG=383Ω
CL=2.2pF
RL=150Ω
NOISE VOLRAGE (nv/√Hz)
NORMALIZED GAIN (dB)
2
100M
FIGURE 8. GAIN vs FREQUENCY FOR VARIOUS RL
5
3
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
4
1G
AV=+1
CL=2.2pF
4
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
AV=+5
RF=383Ω
CL=2.2pF
RL=150Ω
-4
100M
FIGURE 6. GAIN vs FREQUENCY FOR VARIOUS RL
5
2
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
3
200Ω
0
-4
-4
4
500Ω
100
10
150Ω
100K
1M
10M
100M
600M
FREQUENCY (Hz)
FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS RL
6
1
10
100
1K
10K
100K
FREQUENCY (Hz)
FIGURE 10. EQUIVALENT INPUT VOLTAGE NOISE vs
FREQUENCY
FN7330.3
May 3, 2007
EL5100, EL5101, EL5300
Typical Performance Curves (Continued)
0
OPEN LOOP GAIN (dB)
80
PHASE
108
60
144
180
GAIN
40
10
72
70
50
216
252
30
VS=±5V
AV=+1
36
ZOUT (Ω)
VS=±5V
90
PHASE (°)
100
1
0.1
20
10
0
500 1K
10K
100K
10M
1M
0.01
10K
100M 500M
100K
FREQUENCY (Hz)
10M
100M
FREQUENCY (Hz)
FIGURE 11. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 12. ZOUT vs FREQUENCY
10
-10
AV=+1
VS=±5V
RL=150Ω
-10
AV=+10
VS=±5V
-20
-30
-20
-30
-VS
-40
+VS
-50
-60
CMRR (dB)
0
PSRR (dB)
1M
-40
-50
-60
-70
-80
-70
-90
-80
-100
-90
10
100
1K
10K 100K
1M
10M 100M 500M
-110
1K
10K
FREQUENCY (Hz)
100K
10M
1M
100M 500M
FREQUENCY (Hz)
FIGURE 13. PSRR vs FREQUENCY
FIGURE 14. CMRR vs FREQUENCY
INPUT CH1
CH1 RISE
1.408ns
CH1
CH1
OUTPUT CH2
CH1 FALL
1.103ns
INPUT CH1
CH2 RISE
1.787ns
CH2
CH2
CH2 FALL
1.549ns
OUTPUT CH2
CH1=500mV/DIV 50Ω
CH2=100mV/DIV 50Ω
TIME (2ns/DIV)
FIGURE 15. LARGE SIGNAL RISE TIME
7
CH1=500mV/DIV 50Ω
CH2=100mV/DIV 50Ω
TIME (2ns/DIV)
FIGURE 16. LARGE SIGNAL FALL TIME
FN7330.3
May 3, 2007
EL5100, EL5101, EL5300
Typical Performance Curves (Continued)
CH1
VCC VEE = 5V
AV=1
RL=150Ω
INPUT CH1
CH1 RISE
1.717ns
CH2
AV=+1
RL=150Ω
VS=±5V
CH1
CHANNEL 1
CH2
OUTPUT CH2
CHANNEL 2
CH2 RISE
1.808ns
CH1=10mV
CH2=2mV
CH1=10mV/DIV
CH2=2mV/DIV
TIME (2ns/DIV)
TIME (2ns/DIV)
FIGURE 17. SMALL SIGNAL RISE TIME
VCC VEE = 5V
AV=1
RL=150Ω
INPUT CH1
CURRENT NOISE (pA)
CH1
FIGURE 18. SMALL SIGNAL RISE TIME
CH1 FALL
1.306ns
CH2
OUTPUT CH2
CH2 FALL
2.351ns
100
10
CH1=10mV/DIV
CH2=2mV/DIV
1
100
1K
TIME (2ns/DIV)
AV=+1
RL=150Ω
5
15pF
4
13.4pF
3
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
4
2
1
0
7.8pF
-1
2.2pF
-2
-3
-4
-5
100K
FIGURE 20. CURRENT NOISE
FIGURE 19. SMALL SIGNAL FALL TIME
5
10K
FREQUENCY (Hz)
RL=150Ω
CIN-=0pF
24.6 pF
3
19pF
2
13.4pF
1
7.8pF
0
-1
2.2pF
-2
-3
-4
100K
1M
10M
100M
600M
FREQUENCY (Hz)
FIGURE 21. GAIN vs FREQUENCY FOR VARIOUS CL
8
-5
100K
1M
10M
100M
600M
FREQUENCY (Hz)
FIGURE 22. GAIN vs FREQUENCY FOR VARIOUS CL
FN7330.3
May 3, 2007
EL5100, EL5101, EL5300
Typical Performance Curves (Continued)
5
AV=+5
RF=383Ω
RL=150Ω
4
3
72pF
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
5
50pF
2
38pF
1
0
20pF
-1
-2
2.2pF
-3
AV=+2
RF=383Ω
RL=150Ω
CIN=0pF
4
3
2
0
-1
-2
7.8pF
-3
-4
-5
100K
-5
100K
10M
100M
38pF
26pF
1
-4
1M
50pF
44pF
2.2pF
1M
FREQUENCY (Hz)
FIGURE 23. GAIN vs FREQUENCY FOR VARIOUS CL
100M
FIGURE 24. GAIN vs FREQUENCY FOR VARIOUS CL
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.8
1.2
1.6
POWER DISSIPATION (W)
POWER DISSIPATION (W)
10M
FREQUENCY (Hz)
1.4
1.2 1.136W
θJ
1 1.116W
0.8
S
A =1 O8
10
°C
/
W
0.6 543mW
QSOP16
SOT
θJ = 23-5/6
A 230
° C/ W
0.4
0.2
θJA=112°C/W
0
1
791mW
0.8
QS
θJ
A =1
781mW
0.6
0.4 488mW
θJ
0.2
SO
OP
58
16
°C
/W
T
23
A =25 -5/6
6°C
/W
SO8
θJA=160°C/W
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
9
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7330.3
May 3, 2007
DIFFERENTIAL GAIN (%)
EL5100, EL5101, EL5300
0.02
0.01
0.00
-0.01
-0.02
-0.03
0
10
20
30
40
50
60
70
80
90
100
IRE
DIFFERENTIAL PHASE (°)
FIGURE 27. DIFFERENTIAL GAIN (%)
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
0
10
20
30
40
50
60
70
80
90
100
IRE
FIGURE 28. DIFFERENTIAL PHASE (°)
10
FN7330.3
May 3, 2007
EL5100, EL5101, EL5300
Application Information
Video Amplifier with Reduced Size Output
Capacitance
If you have a video line driver Z = 75Ω, the DC decoupling
capacitor could be relatively large.
C=
1
2π × R × f
=
f = 10Hz, R = Z = 75Ω,
C = 132µF
By using the circuit below, C could be reduced to C2 = 22µF.
Vs+
C5
C4
1n
R8
3R3
22µF
C6
33nF
20K
C1
7
U1
3
2
C
R2
20K
+
EL5104
R4
C2
6
22µF
4
R1
R3
10k
R5
Z = 75Ω
75
500
C3
R7
75
1.5µF
R6
500
FIGURE 29.
By selecting a different value for C1, we could reduce the
effect, created by C3 R3 and get flat response from 16Hz
with an 1/5 value, price and size output capacitor. There is
another, very important issue by using high bandwidth
amplifiers.
10
5
0
GAIN (dB)
-5
-10
-15
-20
-25
Conditions/comments:
(1) C1 = 1µF Vs = +10V
(2) C1 = 0.47µF Vs = +10V
(3) C1 = 0.47µF Vs = +5V
-30
-35
-40
-45
1.00E+00 1.00E+02 1.00E+04 1.00E+06 1.00E+08
1.00E+01 1.00E+03 1.00E+05 1.00E+07 1.00E+09
FREQUENCY (Hz)
FIGURE 30. VIDEO-
The test result is shown on Figure 30.
11
In the past when the bandwidth of the operational amplifier
ended at a few hundred kHz even at few MHz, the powersupply bypass was not a very critical issue, since a 0.1µF
capacitor “did the job”, but today’s amplifiers could have
bandwidth, what used to be reserved for microwave circuits
not to long time ago.
Therefore that high bandwidth amplifiers require the same
respect what we reserve for microwave circuits. Particularly
the power supply bypass and the pcb-layout could very
heavily influence the performance of a modern high
bandwidth amplifiers. It could happen above a few MHz, but
it will happen above 100MHz, that the capacitor will behave
like an inductor.
FN7330.3
May 3, 2007
EL5100, EL5101, EL5300
CAPACITIVE
Z
INDUCTIVE
The reason for that is the very small but not zero value serial
inductance of the capacitor.
The impedance of a parallel tank circuit at resonance is
dependent from it’s Q. High Q high impedance.
The Q of a parallel tank circuit could be reduced by
bypassing it with a resistor, or adding a resistor in serial to
one of the reactive components. Since the bypassing would
short the DC supply we do have to go to add resistor in serial
to the reactive component, we will ad a resistor serial with
the inductor. (See Figure 33.)
Ci
Li
C3
F
Z
F RES
FIGURE 31.
R3 = 0
The capacitor will behave as a capacitor up to its resonance
frequency, above the resonance frequency it will behave as
an inductor.
L3
R3 = 3
R3
2 to 3Ω
Just 1nHy inductance serial with 1nF capacitance will have
serial resonance at:
1
F=
2π L × C
F
F RES
C = 1nF, L = 1nHy, F = 159 MHz
FIGURE 33.
And an other 1nHy is very easy to get together with the
inductance of traces on the pcb, and therefore you could
encounter resonances from ca 50MHz and above anywhere.
So if the amplifier has a bandwidth of a few hundred MHz,
the proper power supply by-pass could become a serious if
not difficult task.
Intuitively, you would use capacitors value 0.1µF parallel
with a few µF tantalum, and to cure the effect of it’s serial
resonance put a smaller one parallel to it.
The result will surprise to you, because you will get even
something worse than without the small capacitor.
C2
1n
1n
C3
0.1µF
22µF
=
0.1µF
L1
<
Vs+
C11
C1
1n
R10
3R3
22µF
C12
33nF
C3
C2
C1
The final power supply bypass circuit will look:
FIGURE 34.
What is happening there? Just look what we get:
C1
0.1µF
C1
22µF
L2
FIGURE 32.
Above its serial resonance C2* the ideal capacitance of C2 is
a short, the Tantalum capacitor for high frequencies is not
effective, the left over is C1 capacitor and L1 + L2 inductors,
we get a parallel tank circuit, which is at it’s resonance a high
impedance path and do not carry any high frequency
current, it does not work as bypass at all!
12
FN7330.3
May 3, 2007
EL5100, EL5101, EL5300
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
13
FN7330.3
May 3, 2007
EL5100, EL5101, EL5300
SOT-23 Package Family
MDP0038
e1
SOT-23 PACKAGE FAMILY
D
A
MILLIMETERS
6
N
SYMBOL
4
E1
2
E
3
0.15 C D
1
2X
2
3
0.20 C
5
2X
e
0.20 M C A-B D
B
b
NX
0.15 C A-B
1
3
SOT23-5
SOT23-6
A
1.45
1.45
MAX
A1
0.10
0.10
±0.05
A2
1.14
1.14
±0.15
b
0.40
0.40
±0.05
c
0.14
0.14
±0.06
D
2.90
2.90
Basic
E
2.80
2.80
Basic
E1
1.60
1.60
Basic
e
0.95
0.95
Basic
e1
1.90
1.90
Basic
L
0.45
0.45
±0.10
L1
0.60
0.60
Reference
N
5
6
Reference
Rev. F 2/07
D
2X
TOLERANCE
NOTES:
C
A2
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
SEATING
PLANE
A1
0.10 C
3. This dimension is measured at Datum Plane “H”.
NX
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
(L1)
6. SOT23-5 version has no center lead (shown as a dashed line).
H
A
GAUGE
PLANE
c
L
14
0.25
0° +3°
-0°
FN7330.3
May 3, 2007
EL5100, EL5101, EL5300
Quarter Size Outline Plastic Packages Family (QSOP)
MDP0040
A
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
D
(N/2)+1
N
INCHES
SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
E
PIN #1
I.D. MARK
E1
1
(N/2)
A
0.068
0.068
0.068
Max.
-
A1
0.006
0.006
0.006
±0.002
-
A2
0.056
0.056
0.056
±0.004
-
b
0.010
0.010
0.010
±0.002
-
c
0.008
0.008
0.008
±0.001
-
D
0.193
0.341
0.390
±0.004
1, 3
E
0.236
0.236
0.236
±0.008
-
E1
0.154
0.154
0.154
±0.004
2, 3
e
0.025
0.025
0.025
Basic
-
L
0.025
0.025
0.025
±0.009
-
L1
0.041
0.041
0.041
Basic
-
N
16
24
28
Reference
-
B
0.010
C A B
e
H
C
SEATING
PLANE
0.007
0.004 C
b
C A B
Rev. F 2/07
NOTES:
L1
A
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
c
SEE DETAIL "X"
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010
A2
GAUGE
PLANE
L
A1
4°±4°
DETAIL X
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15
FN7330.3
May 3, 2007
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