DATASHEET

S
NEW DESIGN
ENDED FOR
M
M
O
C
T
E
N
R
E
T
M
O
E
N
C
ENDED REPLA
NO RECOMM
Center at
rt
po
up
S
chnical
contact our Te or www.intersil.com/tsc
IL
1-888-INTERS
12MHz Rail-to-Rail Input-Output Operational Amplifier
EL5120T
Features
The EL5120T is a high voltage rail-to-rail input-output amplifier
with low power consumption. The EL5120T is a single amplifier
that exhibits beyond the rail input capability, rail-to-rail output
capability, and is unity gain stable.
• 750µA supply current
• 12MHz (-3dB) bandwidth
• 4.5V to 19V maximum supply voltage range
The operating voltage range is from 4.5V to 19V. It can be
configured for single or dual supply operation, and typically
consumes only 750µA. The EL5120T has an output short circuit
capability of ±200mA and a continuous output current capability
of ±70mA.
The EL5120T features a slew rate of 12V/µs. Also, the device
provides common mode input capability beyond the supply rails,
rail-to-rail output capability, and a bandwidth of 12MHz (-3dB).
This enables the amplifier to offer maximum dynamic range at
any supply voltage. These features make the EL5120T an ideal
amplifier solution for use in TFT-LCD panels as a VCOM or static
gamma buffer, and in high speed filtering and signal conditioning
applications. Other applications include battery power and
portable devices, especially where low power consumption is
important.
The EL5120T is available in small 5 Ld TSOT package. It features a
standard operational amplifier pinout. The device operates over
an ambient temperature range of -40°C to +125°C.
• 12V/µs slew rate
• ±70mA continuous output current
• ±200mA output short circuit current
• Unity-gain stable
• Beyond the rails input capability
• Rail-to-rail output swing
• Built-in thermal protection
• -40°C to +125°C ambient temperature range
• Pb-free (RoHS compliant)
Applications
• TFT-LCD panel - tablet, monitor, notebook
- VCOM amplifier, static gamma buffer, panel repair
• Electronic notebooks, games
• Touch-screen displays
• Personal communication devices, digital assistants (PDA)
• Portable instrumentation
• Sampling ADC amplifiers
• Wireless LANs
• Office automation
• Active filters
• ADC/DAC buffer
5
10kΩ
PANEL
LOAD
VOUT
+15V
EL5120T
+15V
VS+
+
VSVIN+
0.1µF
VIN-
TFT-LCD
PANEL
4.7µF
NORMALIZED GAIN (dB)
0
0
1kΩ
-5
560Ω
150Ω
-10 VS = ±5V
AV = 1
CL = 8pF
-15
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 1. TYPICAL TFT-LCD VCOM APPLICATION
September 26, 2013
FN6895.1
1
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS RL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
EL5120T
Pin Configuration
EL5120T
(5 LD TSOT)
TOP VIEW
VOUT 1
VS- 2
VIN+ 3
5 VS+
+ 4 VIN-
Pin Descriptions
PIN NUMBER
PIN
NAME
EQUIVALENT
CIRCUIT
1
VOUT
2
VS-
3
VIN+
Amplifier non-inverting input
(Reference “CIRCUIT 2”)
4
VIN-
Amplifier inverting input
(Reference “CIRCUIT 2”)
5
VS+
Positive power supply
FUNCTION
Amplifier output
(Reference “CIRCUIT 1”)
Negative power supply
VS+
VS+
VOUT
VIN
VS-
GND
VS-
CIRCUIT 1
CIRCUIT 2
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
EL5120TIWTZ-T7 (Note 1)
BESA
PACKAGE
(Pb-Free)
5 Ld TSOT
PKG.
DWG. #
MDP0049
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for EL5120T. For more information on MSL please see techbrief TB363.
2
FN6895.1
September 26, 2013
EL5120T
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage between VS+ and VS-. . . . . . . . . . . . . . . . . . . . . . . . . +19.8V
Input Voltage Range (VIN+, VIN-). . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS+ + 0.5V
Input Differential Voltage (VIN+ - VIN-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VS+ + 0.5V)-(VS- - 0.5V)
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . ±70mA
ESD Rating
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . 4000V
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . 2000V
Latch Up (Tested per JESD78; Class II, Level A) . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
5 Ld TSOT (Notes 4, 5)
215
290
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figures 30 and 31
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For JC, the “case temp” location is taken at the package top center.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 10kΩ to 0V, TA = +25°C, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
5
18
mV
INPUT CHARACTERISTICS
VOS
TCVOS
Input Offset Voltage
VCM = 0V
Average Offset Voltage Drift (Note 6)
5
µV/°C
IB
Input Bias Current
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
2
pF
VCM = 0V
2
+5.5
nA
CMIR
Common-Mode Input Range
CMRR
Common-Mode Rejection Ratio
For VIN from -5.5V to +5.5V
50
75
dB
Open Loop Gain
-4.5V VOUT 4.5V
75
105
dB
AVOL
-5.5
50
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = +5mA
ISC
Short Circuit Current
VCM = 0V, Source: VOUT short to VS-,
Sink: VOUT short to VS+
IOUT
Output Current
-4.94
4.85
-4.85
V
4.94
V
±200
mA
±70
mA
POWER SUPPLY PERFORMANCE
(VS+) - (VS-)
IS
PSRR
Supply Voltage Range
4.5
Supply Current
VCM = 0V, No load
Power Supply Rejection Ratio
Supply is moved from ±2.25V to ±9.5V
750
60
19
V
950
µA
75
dB
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 7)
-4.0V VOUT 4.0V, 20% to 80%
12
V/µs
tS
Settling to +0.1% (Note 8)
AV = +1, VOUT = 2V step,
RL = 10kΩ, CL = 8pF
500
ns
-3dB Bandwidth
RL = 10kΩ, CL = 8pF
12
MHz
BW
3
FN6895.1
September 26, 2013
EL5120T
Electrical Specifications
PARAMETER
GBWP
PM
VS+ = +5V, VS- = -5V, RL = 10kΩ to 0V, TA = +25°C, unless otherwise specified. (Continued)
DESCRIPTION
CONDITIONS
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
Gain-Bandwidth Product
AV = -50, RF = 5kΩRG = 100Ω
RL = 10kΩ, CL = 8pF
8
MHz
Phase Margin
AV = -50, RF = 5kΩRG = 100Ω
RL = 10kΩ, CL = 8pF
50
°
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = 0V, RL = 10kΩ to 2.5V, TA = +25°C, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
5
18
mV
INPUT CHARACTERISTICS
VOS
TCVOS
Input Offset Voltage
VCM = 2.5V
Average Offset Voltage Drift (Note 6)
5
µV/°C
IB
Input Bias Current
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
2
pF
VCM = 2.5V
2
+5.5
nA
CMIR
Common-Mode Input Range
CMRR
Common-Mode Rejection Ratio
For VIN from -0.5V to +5.5V
45
70
dB
Open Loop Gain
0.5V VOUx 4.5V
75
105
dB
AVOL
-0.5
50
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -2.5mA
VOH
Output Swing High
IL = +2.5mA
ISC
Short Circuit Current
VCM = 2.5V, Source: VOUT short to VS-,
Sink: VOUT short to VS+
IOUT
Output Current
30
4.85
150
mV
4.97
V
±125
mA
±70
mA
POWER SUPPLY PERFORMANCE
(VS+) - (VS-)
IS
PSRR
Supply Voltage Range
4.5
Supply Current
VCM = 2.5V, No load
Power Supply Rejection Ratio
Supply is moved from 4.5V to 19V
750
60
19
V
950
µA
75
dB
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 7)
1V VOUT 4V, 20% to 80%
12
V/µs
tS
Settling to +0.1% (Note 8)
AV = +1, VOUT = 2V step,
RL = 10kΩ, CL = 8pF
500
ns
-3dB Bandwidth
RL = 10kΩ, CL = 8pF
12
MHz
Gain-Bandwidth Product
AV = -50, RF = 5kΩRG = 100Ω
RL = 10kΩ, CL = 8pF
8
MHz
Phase Margin
AV = -50, RF = 5kΩRG = 100Ω
RL = 10kΩ, CL = 8pF
50
°
BW
GBWP
PM
4
FN6895.1
September 26, 2013
EL5120T
Electrical Specifications
PARAMETER
VS+ = +18V, VS- = 0V, RL = 10kΩ to 9V, TA = +25°C, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
6
18
mV
INPUT CHARACTERISTICS
VOS
TCVOS
Input Offset Voltage
VCM = 9V
Average Offset Voltage Drift (Note 6)
6
µV/°C
IB
Input Bias Current
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
2
pF
VCM = 9V
2
nA
CMIR
Common-Mode Input Range
CMRR
Common-Mode Rejection Ratio
For VIN from -0.5V to +18.5V
53
78
dB
Open Loop Gain
0.5V VOUT 17.5V
75
90
dB
AVOL
-0.5
50
+18.5
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -9mA
VOH
Output Swing High
IL = +9mA
ISC
Short Circuit Current
VCM = 9V, Source: VOUT short to VS-,
Sink: VOUT short to VS+
IOUT
Output Current
120
17.85
150
mV
17.88
V
±200
mA
±70
mA
POWER SUPPLY PERFORMANCE
(VS+) - (VS-)
IS
PSRR
Supply Voltage Range
4.5
Supply Current
VCM = 9V, No load
Power Supply Rejection Ratio
Supply is moved from 4.5V to 19V
900
60
19
V
1100
µA
75
dB
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 7)
1V VOUT 17V, 20% to 80%
12
V/µs
tS
Settling to +0.1% (Note 8)
AV = +1, VOUT = 2V step,
RL = 10kΩ, CL = 8pF
500
ns
-3dB Bandwidth
RL = 10kΩ, CL = 8pF
12
MHz
Gain-Bandwidth Product
AV = -50, RF = 5kΩRG = 100Ω
RL = 10kΩ, CL = 8pF
8
MHz
Phase Margin
AV = -50, RF = 5kΩRG = 100Ω
RL = 10kΩ, CL = 8pF
50
°
BW
GBWP
PM
NOTES:
6. Measured over -40°C to +85°C ambient operating temperature range. See the typical TCVOS production distribution shown in the “Typical
Performance Curves” on page 6.
7. Typical slew rate is an average of the slew rates measured on the rising (20% to 80%) and the falling (80% to 20%) edges of the output signal.
8. Settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the output level settles within a
±0.1% error band. The range of the error band is determined by: Final Value(V)±[Full Scale(V)*0.1%]
9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
5
FN6895.1
September 26, 2013
EL5120T
500 V = ±5V
S
TA = +25°C
NO LOAD
400 VCM = 0.5 x VS
45
TYPICAL
PRODUCTION
DISTRIBUTION
VS = ±5V
TA = -40°C TO 85°C
NO LOAD
VCM = 0.5 x VS
40
QUANTITY (AMPLIFIERS)
QUANTITY (AMPLIFIERS)
Typical Performance Curves
300
200
100
35
30
25
20
15
10
5
0
-10
-8
-6
-4
-2
0
2
4
6
8
0
10
FIGURE 3. INPUT OFFSET VOLTAGE DISTRIBUTION
7.5
5.0
2.5
50
4
6
100
20
22
24
26
2
1
0
0
50
100
150
FIGURE 6. INPUT BIAS CURRENT vs TEMPERATURE
-4.90
4.93
OUTPUT LOW VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
18
3
-1
-50
150
VS = ±5V
IL = +2.5mA
4.92
4.91
4.90
4.89
100
TEMPERATURE (°C)
FIGURE 7. OUTPUT HIGH VOLTAGE vs TEMPERATURE
6
16
TEMPERATURE (°C)
4.94
50
14
4
FIGURE 5. INPUT OFFSET VOLTAGE vs TEMPERATURE
0
10 12
VS = ±5V
TEMPERATURE (°C)
4.88
-50
8
5
VS = ±5V
0
2
FIGURE 4. INPUT OFFSET VOLTAGE DRIFT (TSOT)
INPUT BIAS CURRENT (nA)
INPUT OFFSET VOLTAGE (mV)
10.0
0.0
-50
0
INPUT OFFSET VOLTAGE DRIFT (|µV|/°C)
INPUT OFFSET VOLTAGE (mV)
150
VS = ±5V
IL = -2.5mA
-4.91
-4.92
-4.93
-4.94
-4.95
-4.96
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 8. OUTPUT LOW VOLTAGE vs TEMPERATURE
FN6895.1
September 26, 2013
EL5120T
Typical Performance Curves (Continued)
13.0
VS = ±5V
RL = 10kΩ
120
SLEW RATE (V/µs)
100
80
60
40
-50
0
50
TEMPERATURE (°C)
100
VS = ±5V
RL = 10kΩ
12.5
12.0
11.5
11.0
-50
150
150
1000
770
SUPPLY CURRENT (µA)
VS = ±5V
NO LOAD
VCM = 0.5 x VS
AV = +1
750
730
710
-50
VS = ±5V
TA = +25°C
NO LOAD
VCM = 0.5 x VS
900
AV = +1
800
700
600
0
50
100
150
4
8
12
16
FIGURE 11. SUPPLY CURRENT vs TEMPERATURE
FIGURE 12. SUPPLY CURRENT vs SUPPLY VOLTAGE
60
250
VS = ±5V
TA = +25°C
RL = 10kΩ 200
CL = 8pF
150
40
100
100
16
TA = +25°C
AV = 1
RL = 10kΩ
14 C = 8pF
L
OPEN LOOP GAIN (dB)
80
12
10
4
6
8
10
12
14
16
SUPPLY VOLTAGE (±V)
FIGURE 13. SLEW RATE vs SUPPLY VOLTAGE
7
20
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SLEW RATE (V/µs)
100
FIGURE 10. SLEW RATE vs TEMPERATURE
790
8
50
TEMPERATURE (°C)
FIGURE 9. OPEN-LOOP GAIN vs TEMPERATURE
SUPPLY CURRENT (µA)
0
18
20
GAIN
PHASE
20
50
0
0
-20
10
100
1k
10k
100k
1M
10M
PHASE (°)
OPEN LOOP GAIN (dB)
140
-50
100M
FREQUENCY (Hz)
FIGURE 14. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FN6895.1
September 26, 2013
EL5120T
Typical Performance Curves (Continued)
20
VS = ±5V
AV = 1
CL = 8pF
10kΩ
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
5
0
1kΩ
-5
560Ω
150Ω
-10
VS = ±5V
A =1
15 RV = 10kΩ
L
10
100pF
5
0
50pF
8pF
-5
-10
-15
100k
1M
10M
1000pF
-15
100k
100M
1M
FREQUENCY (Hz)
FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS RL
MAXIMUM OUTPUT SWING (VP-P)
OUTPUT IMPEDANCE (Ω)
12
VS = ±5V
RF = 2kVΩ
RG = 1kΩ
100
RL = 450Ω
SOURCE = 0dBm
10
1
0.1
1k
100k
1M
VS = ±5V
TA = +25°C
AV = 1
RL = 10kΩ
CL = 8pF
10
8
6
4
2
0
10k
100M
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 17. CLOSED LOOP OUTPUT IMPEDANCE vs FREQUENCY
0
VS = ±5V
T = +25°C
-10 A
VIN = -10dBm
VS = ±5V
-10 TA = +25°C
-20
-20
-30
-30
PSRR (dB)
CMRR (dB)
10M
FIGURE 18. MAXIMUM OUTPUT SWING vs FREQUENCY
0
-40
-50
-40
-50
-60
-60
-70
-70
-80
10
100M
FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS CL
1000
0.01
10
10M
FREQUENCY (Hz)
1k
100k
FREQUENCY (Hz)
FIGURE 19. CMRR vs FREQUENCY
8
100M
-80
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 20. PSRR vs FREQUENCY
FN6895.1
September 26, 2013
EL5120T
Typical Performance Curves (Continued)
0.050
1000
VS = ±5V
0.045 R = 10kΩ
L
0.040 AV = 1
VIN = 1.4VRMS
0.035
VOLTAGE NOISE (nV/√Hz)
TA = +25°C
THD+N (%)
100
0.030
0.025
0.020
10
0.015
0.010
1
100
1k
10k
100k
1M
10M
0.005
100
100M
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 22. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
FIGURE 21. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs
FREQUENCY
OVERSHOOT (%)
80
60
5
VS = ±5V
TA = +25°C
AV = 1
RL = 10kΩ
VIN = ±50mV
4
3
STEP SIZE (V)
100
100k
40
20
2
VS = ±5V
TA = +25°C
AV = 1
RL = 10kΩ
CL = 8pF
0.1%
1
0
-1
-2
0.1%
-3
-4
0
10
100
1000
-5
100
200
LOAD CAPACITANCE (pF)
400
500
600
700
SETTLING TIME (ns)
VS = ±5V
TA = +25°C
AV = 1
RL = 10kΩ
CL = 8pF
FIGURE 24. STEP SIZE vs SETTLING TIME
VS = ±5V
TA = +25°C
AV = 1
RL = 10kΩ
CL = 8pF
50mV/DIV
FIGURE 23. SMALL SIGNAL OVERSHOOT vs LOAD CAPACITANCE
1V/DIV
300
200ns/DIV
100mV STEP
6V STEP
1µs/DIV
FIGURE 25. LARGE SIGNAL TRANSIENT RESPONSE
9
FIGURE 26. SMALL SIGNAL TRANSIENT RESPONSE
FN6895.1
September 26, 2013
EL5120T
RF
1
V OUT
VOUT
Vs+
5
V S+
+
RL
CL
0.1µF
2
V S4.7µF
+
4.7µF
Vs-
0.1µF
4
3
VIN+
VIN+
VIN-
49.9 
RG
EL5120T
(5 LD TSOT)
FIGURE 27. BASIC TEST CIRCUIT
10
FN6895.1
September 26, 2013
EL5120T
Applications Information
VS = ±2.5V, TA = +25°C, AV = 1, VIN = 6VP-P, RL = 10kΩ TO GND
OUTPUT
The EL5120T features a slew rate of 12V/µs. Also, the device
provides common mode input capability beyond the supply rails,
rail-to-rail output capability, and a bandwidth of 12MHz (-3dB).
This enables the amplifier to offer maximum dynamic range at
any supply voltage.
INPUT
100µs/DIV
Operating Voltage, Input and Output
Capability
The input common-mode voltage range of the EL5120T extends
500mV beyond the supply rails. Also, the EL5120T is immune to
phase reversal. However, if the common mode input voltage
exceeds the supply voltage by more than 0.5V, electrostatic
protection diodes in the input stage of the device begin to conduct.
Even though phase reversal will not occur, to maintain optimal
reliability it is suggested to avoid input overvoltage conditions.
Figure 28 shows the input voltage driven 500mV beyond the
supply rails and the device output swinging between the supply
rails.
The EL5120T output typically swings to within 50mV of positive
and negative supply rails with load currents of ±5mA. Decreasing
load currents will extend the output voltage range even closer to
the supply rails. Figure 29 shows the input and output waveforms
for the device in a unity-gain configuration. Operation is from ±5V
supply with a 10kΩ load connected to GND. The input is a 10VP-P
sinusoid and the output voltage is approximately 9.9VP-P.
Refer to the “Electrical Specifications” table beginning on page 3
for specific device parameters. Parameter variations with
operating voltage, loading and/or temperature are shown in the
“Typical Performance Curves” beginning on page 6.
INPUT
VS = ±5V, TA = +25°C, AV = 1, VIN = 10VP-P, RL = 10kΩ TO GND
5V/DIV
The EL5120T can operate on a single supply or dual supply
configuration. The EL5120T operating voltage ranges from a
minimum of 4.5V to a maximum of 19V. This range allows for a
standard 5V (or ±2.5V) supply voltage to dip to -10%, or a standard
18V (or ±9V) to rise by +5.5% without affecting performance or
reliability.
FIGURE 28. OPERATION WITH BEYOND-THE-RAILS INPUT
OUTPUT
The EL5120T is a high voltage rail-to-rail input-output amplifier
with low power consumption. The EL5120T is a single amplifier
which exhibits beyond the rail input capability, rail-to-rail output
capability, and is unity gain stable.
1V/DIV
Product Description
100µs/DIV
FIGURE 29. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT
Output Current
The EL5120T is capable of output short circuit currents of
200mA (source and sink), and the device has built-in protection
circuitry, which limits the output current to ±200mA (typical).
To maintain maximum reliability, the continuous output current
should never exceed ±70mA. This ±70mA limit is determined by
the characteristics of the internal metal interconnects. Also, see
“Power Dissipation” on page 12 for detailed information on
ensuring proper device operation and reliability for temperature
and load conditions.
Thermal Shutdown
The EL5120T has a built-in thermal protection, which ensures
safe operation and prevents internal damage to the device due to
overheating. When the die temperature reaches +165°C
(typical), the device automatically shuts OFF the outputs by
putting them in a high impedance state. When the die cools by
+15°C (typical), the device automatically turns ON the outputs by
putting them in a low impedance (normal) operating state.
11
FN6895.1
September 26, 2013
EL5120T
Driving Capacitive Loads
• VOUT = Output voltage
Purely capacitive loads on the EL5120T should not exceed 1nF
without appropriate output load isolation or amplifier
compensation techniques.
• ILOAD = Load current
A snubber is a shunt load consisting of a resistor in series with a
capacitor. An optimized snubber can improve the phase margin
and the stability of the EL5120T. The advantage of a snubber
circuit is that it does not draw any DC load current or reduce the
gain.
Another method to reduce peaking is to add a series output
resistor (typically between 1 to 10). Depending on the
capacitive loading, a small value resistor may be the most
appropriate choice to minimize any reduction in gain.
Power Dissipation
With the high-output drive capability of the EL5120T amplifier, it
is possible to exceed the +150°C absolute maximum junction
temperature under certain load current conditions. It is
important to calculate the maximum power dissipation of the
EL5120T in the application. Proper load conditions will ensure
that the EL5120T junction temperature stays within a safe
operating region.
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.6
0.5
POWER DISSIPATION (W)
As load capacitance increases, the -3dB bandwidth will decrease
and peaking can occur. Depending on the application, it may be
necessary to reduce peaking and to improve device stability. To
improve device stability, a snubber circuit (compensation) or a
series resistor (isolation) may be added to the output of the
EL5120T.
Device overheating can be avoided by calculating the minimum
resistive load condition, RLOAD, resulting in the highest power
dissipation. To find RLOAD set the two PDMAX equations equal to
each other and solve for VOUT/ILOAD. Reference the package
power dissipation curves, Figures 30 and 31, for further
information.
417mW
0.4
0.2
0.1
0.0
50
75
100
125
150
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD - EXPOSED DIEPAD
SOLDERED TO PCB PER JESD51-5
0.8
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
• PDMAX = Maximum power dissipation allowed
The total power dissipation produced by an IC is the total
quiescent supply current times the total power supply voltage,
plus the power dissipation in the IC due to the load, or:
(EQ. 2)
when sourcing, and:
POWER DISSIPATION (W)
where:
P DMAX = V S  I SMAX +  V OUT – V S -   I LOAD
25
AMBIENT TEMPERATURE (°C)
(EQ. 1)
P DMAX = V S  I SMAX +  V S + – V OUT   I LOAD
0
FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
The maximum power dissipation allowed in a package is
determined according to Equation 1:
T JMAX – T AMAX
P DMAX = -------------------------------------------- JA
TSOT5
JA = +300°C/W
0.3
581mW
0.6
TSOT5
JA = +215°C/W
0.4
0.2
0.0
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 31. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
(EQ. 3)
when sinking,
where:
• VS = Total supply voltage (VS+ - VS-)
• VS+ = Positive supply voltage
• VS- = Negative supply voltage
• ISMAX = Maximum supply current
(ISMAX = EL5120T quiescent current)
12
FN6895.1
September 26, 2013
EL5120T
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5120T can provide gain at high frequency, so good printed
circuit board layout is necessary for optimum performance.
Ground plane construction is highly recommended, trace lengths
should be as short as possible and the power supply pins must
be well bypassed to reduce any risk of oscillation.
For normal single supply operation (the VS- pin is connected to
ground) a 4.7µF capacitor should be placed from VS+ to ground,
then a parallel 0.1µF capacitor should be connected as close to
the amplifier as possible. One 4.7µF capacitor may be used for
multiple devices. For dual supply operation the same capacitor
combination should be placed at each supply pin to ground.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
September 26, 2013
FN6895.1
Features on page 1: Updated operation temperature range from ” -40°C to +85°C” to “-40°C to +125°C”.
Thermal Information table on page 3 under Ambient operation temperature changed the temperature range
from “-40°C to +85°C” to “-40°C to +125°C”.
Updated Figure 30, “PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE,” on page 12 and Figure 31,
“PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE,” on page 12.
September 27, 2012
FN6895.0
Initial release.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN6895.1
September 26, 2013
EL5120T
TSOT Package Family
MDP0049
e1
D
TSOT PACKAGE FAMILY
A
MILLIMETERS
6
N
SYMBOL
4
E1
2
E
3
0.15 C D
2X
1
5
2
(N/2)
0.25 C
2X N/2 TIPS
e
ddd M
B
C A-B D
b
NX
0.15 C A-B
1
3
D
2X
TSOT5
TSOT6
TSOT8
TOLERANCE
A
1.00
1.00
1.00
Max
A1
0.05
0.05
0.05
±0.05
A2
0.87
0.87
0.87
±0.03
b
0.38
0.38
0.29
±0.07
c
0.127
0.127
0.127
+0.07/-0.007
D
2.90
2.90
2.90
Basic
E
2.80
2.80
2.80
Basic
E1
1.60
1.60
1.60
Basic
e
0.95
0.95
0.65
Basic
e1
1.90
1.90
1.95
Basic
L
0.40
0.40
0.40
±0.10
L1
0.60
0.60
0.60
Reference
ddd
0.20
0.20
0.13
-
N
5
6
8
Reference
Rev. B 2/07
C
A2
SEATING
PLANE
1. Plastic or metal protrusions of 0.15mm maximum per side are
not included.
2. Plastic interlead protrusions of 0.15mm maximum per side are
not included.
A1
0.10 C
NOTES:
NX
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
(L1)
5. Index area - Pin #1 I.D. will be located within the indicated zone
(TSOT6 AND TSOT8 only).
H
A
GAUGE
PLANE
c
L
14
6. TSOT5 version has no center lead (shown as a dashed line).
0.25
4° ±4°
FN6895.1
September 26, 2013
Similar pages