DATASHEET

EL2125
®
Data Sheet
May 4, 2007
Ultra-Low Noise, Low Power, Wideband
Amplifier
The EL2125 is an ultra-low noise, wideband amplifier that
runs on half the supply current of competitive parts. It is
intended for use in systems such as ultrasound imaging
where a very small signal needs to be amplified by a large
amount without adding significant noise. Its low power
dissipation enables it to be packaged in the tiny SOT-23
package, which further helps systems where many input
channels create both space and power dissipation problems.
The EL2125 is stable for gains of 10 and greater and uses
traditional voltage feedback. This allows the use of reactive
elements in the feedback loop, a common requirement for
many filter topologies. It operates from ±2.5V to ±15V
supplies and is available in the 5 Ld SOT-23 and 8 Ld SOIC
packages.
The EL2125 is fabricated using Elantec’s proprietary
complementary bipolar process, and is specified for
operation from -45°C to +85°C.
FN7045.3
Features
• Voltage noise of only 0.83nV/√Hz
• Current noise of only 2.4pA/√Hz
• 200µV offset voltage
• 175MHz -3dB BW for AV = 10
• Low supply current - 10mA
• SOT-23 package available
• ±2.5V to ±15V operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Ultrasound input amplifiers
• Wideband instrumentation
• Communication equipment
• AGC and PLL active filters
• Wideband sensors
Pinouts
Ordering Information
PART NUMBER
PART
TAPE &
MARKING REEL
PACKAGE
EL2125CW-T7
F
7”
5 Ld SOT-23 MDP0038
(3k pcs)
EL2125CW-T7A
F
7”
5 Ld SOT-23 MDP0038
(250 pcs)
EL2125CS
2125CS
-
8 Ld SOIC
MDP0027
EL2125CS-T7
2125CS
7”
8 Ld SOIC
MDP0027
EL2125CS-T13
2125CS
13”
8 Ld SOIC
MDP0027
EL2125CSZ
(See Note)
2125CSZ
-
8 Ld SOIC
(Pb-free)
MDP0027
EL2125CSZ-T7
(See Note)
2125CSZ
7”
8 Ld SOIC
(Pb-free)
MDP0027
EL2125CSZ-T13
(See Note)
2125CSZ
13”
8 Ld SOIC
(Pb-free)
MDP0027
OUT 1
VS- 2
5 VS+
+ -
IN+ 3
4 IN-
EL2125
(8 LD SOIC)
TOP VIEW
NC 1
IN- 2
IN+ 3
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
EL2125
(5 LD SOT-23)
TOP VIEW
PKG.
DWG. #
VS- 4
8 NC
+
7 VS+
6 OUT
5 NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2005, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL2125
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
Any Input . . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.3V to VS+ + 0.3V
Ambient Operating Temperature . . . . . . . . . . . . . . . .-45°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Maximum Die Junction Temperature . . . . . . . . . . . . . . . . . . . +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
VS = ±5V, TA = +25°C, RF = 180Ω, RG = 20Ω, RL = 500Ω unless otherwise specified.
Electrical Specifications
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
0.2
2
mV
3
mV
DC PERFORMANCE
VOS
Input Offset Voltage (SO8)
Input Offset Voltage (SOT23-5)
TCVOS
Offset Voltage Temperature Coefficient
IB
Input Bias Current
IOS
Input Bias Current Offset
0.4
TCIB
Input Bias Current Temperature
Coefficient
0.09
µA/°C
CIN
Input Capacitance
2.2
pF
AVOL
Open Loop Gain
80
87
dB
PSRR
Power Supply Rejection Ratio
(Note 1)
80
97
dB
CMRR
Common Mode Rejection Ratio
80
106
dB
CMIR
Common Mode Input Range
VOUTH
Output Voltage Swing High
No load, RF = 1kΩ
VOUTL
Output Voltage Swing Low
No load, RF = 1kΩ
VOUTH2
Output Voltage Swing High
RL = 100Ω
VOUTL2
Output Voltage Swing Low
RL = 100Ω
IOUT
Output Short Circuit Current (Note 2)
IS
Supply Current
-30
at CMIR
1.8
µV/°C
-22
µA
-4.6
3.5
3.8
3.65
-3.87
3
-3.7
V
V
V
-3
100
10.1
µA
V
3.3
-3.5
80
2
V
mA
11
mA
AC PERFORMANCE - RG = 20Ω, CL = 5pF
BW
-3dB Bandwidth
175
MHz
BW ±0.1dB
±0.1dB Bandwidth
34
MHz
BW ±1dB
±1dB Bandwidth
150
MHz
Peaking
Peaking
0.4
dB
SR
Slew Rate
VOUT = 2VP-P, measured at 20% to 80%
185
V/µs
OS
Overshoot, 4VP-P Output Square Wave
Positive
0.6
%
Negative
2.7
%
42
ns
tS
Settling Time to 0.1% of ±1V Pulse
2
150
FN7045.3
May 4, 2007
EL2125
VS = ±5V, TA = +25°C, RF = 180Ω, RG = 20Ω, RL = 500Ω unless otherwise specified. (Continued)
Electrical Specifications
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
VN
Voltage Noise Spectral Density
10kHz
0.83
nV/√Hz
IN
Current Noise Spectral Density
10kHz
2.4
pA/√Hz
HD2
2nd Harmonic Distortion (Note 3)
-74
dBc
HD3
3rd Harmonic Distortion
-91
dBc
NOTES:
1. Measured by moving the supplies from ±4V to ±6V
2. Pulse test only
3. Frequency = 1MHz, VOUT = 2VP-P, into 500Ω and 5pF load
VS = ±15V, TA = +25°C, RF = 180Ω, RG = 20Ω, RL = 500Ω unless otherwise specified.
Electrical Specifications
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
0.6
3
mV
3
mV
DC PERFORMANCE
VOS
Input Offset Voltage (SO8)
Input Offset Voltage (SOT23-5)
TCVOS
Offset Voltage Temperature Coefficient
IB
Input Bias Current
IOS
Input Bias Current Offset
0.4
TCIB
Input Bias Current Temperature
Coefficient
0.08
µA/°C
CIN
Input Capacitance
2.2
pF
AVOL
Open Loop Gain
80
87
dB
PSRR
Power Supply Rejection Ratio
(Note 4)
80
97
dB
CMRR
Common Mode Rejection Ratio
75
105
dB
CMIR
Common Mode Input Range
VOUTH
Output Voltage Swing High
No load, RF = 1kΩ
VOUTL
Output Voltage Swing Low
No load, RF = 1kΩ
VOUTH2
Output Voltage Swing High
RL = 100Ω
VOUTL2
Output Voltage Swing Low
RL = 100Ω
IOUT
Output Short Circuit Current (Note 5)
IS
Supply Current
-30
at CMIR
4.9
µV/°C
-24
µA
-14.6
13.35
13.8
13.5
-13.6
11
-13
V
V
V
-9.8
250
10.8
µA
V
11.6
-10.4
120
2
V
mA
12
mA
AC PERFORMANCE - RG = 20Ω, CL = 5pF
BW
-3dB Bandwidth
220
MHz
BW ±0.1dB
±0.1dB Bandwidth
23
MHz
BW ±1dB
±1dB Bandwidth
63
MHz
Peaking
Peaking
2.5
dB
SR
Slew Rate
225
V/µs
OS
Overshoot, 4VP-P Output Square Wave
0.6
%
tS
Settling Time to 0.1% of ±1V Pulse
38
ns
VOUT = 2VP-P, measured at 20% to 80%
3
180
FN7045.3
May 4, 2007
EL2125
VS = ±15V, TA = +25°C, RF = 180Ω, RG = 20Ω, RL = 500Ω unless otherwise specified. (Continued)
Electrical Specifications
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
VN
Voltage Noise Spectral Density
10kHz
0.95
nV/√Hz
IN
Current Noise Spectral Density
10kHz
2.1
pA/√Hz
HD2
2nd Harmonic Distortion (Note 6)
-73
dBc
HD3
3rd Harmonic Distortion
-96
dBc
NOTES:
4. Measured by moving the supplies from ±13.5V to ±16.5V
5. Pulse test only
6. Frequency = 1MHz, VOUT = 2VP-P, into 500Ω and 5pF load
Typical Performance Curves
5
VS = ±5V
AV = 10
RL = 500Ω
CL = 5pF
RF = 1kΩ
RF = 499Ω
0
RF = 180Ω
RF = 100Ω
-5
1M
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
5
RF = 499Ω
RF = 180Ω
RF = 100Ω
10M
FIGURE 1. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
6
RF = 499Ω
2
-2
RF = 350Ω
RF = 200Ω
-6
RF = 97.6Ω
VS = ±5V
AV = -10
RL = 560Ω
CL = 5pF
10M
100M
300M
FREQUENCY (Hz)
FIGURE 3. INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
4
NORMALIZED GAIN (dB)
RF = 1kΩ
NORMALIZED GAIN (dB)
300M
FIGURE 2. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
6
-14
1M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
-10
RF = 700Ω
RF = 1kΩ
0
-5
1M
100M 200M
10M
VS = ±15V
AV = 10
RL = 500Ω
CL = 5pF
RF = 1kΩ
2
-2
RF = 350Ω
RF = 200Ω
-6
-10
-14
1M
RF = 499Ω
VS = ±15V
AV = -10
RL = 500Ω
CL = 5pF
RF = 97.6Ω
10M
100M
300M
FREQUENCY (Hz)
FIGURE 4. INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
FN7045.3
May 4, 2007
EL2125
Typical Performance Curves
(Continued)
5
5
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
VS = ±5V
RL = 500Ω
CL = 5pF
RG = 20Ω
AV = 10
0
AV = 20
AV = 50
-5
1M
10M
VS = ±15V
RL = 500Ω
CL = 5pF
RF = 700Ω
0
AV = 20
AV = 50
-5
1M
100M 200M
AV = 10
10M
FREQUENCY (Hz)
100M 200M
FREQUENCY (Hz)
FIGURE 5. NON-INVERTING FREQUENCY RESPONSE vs GAIN
FIGURE 6. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS GAIN
6
2
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
6
AV = -10
-2
AV = -50
-6
VS = ±5V
-10 RL = 500Ω
CL = 5pF
RG = 35Ω
-14
1M
AV = -20
10M
100M
AV = -10
0
AV = -20
AV = -50
VS = ±15V
RL = 500Ω
CL = 5pF
RG = 50Ω
-14
1M
300M
FREQUENCY (Hz)
FIGURE 7. INVERTING FREQUENCY RESPONSE vs GAIN
300M
6
VS = ±5V
AV = 10
RF = 180Ω
RL = 500Ω
CL = 5pF
3mVPP
30mVPP
500mVPP
0
4VPP
2VPP
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
100M
FIGURE 8. INVERTING FREQUENCY RESPONSE vs GAIN
5
10M
100M 200M
FREQUENCY (Hz)
FIGURE 9. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS OUTPUT SIGNAL LEVELS
5
500mVPP
250mVPP
0
3.3VPP
VS = ±5V
AV = -10
RF = 350Ω
RL = 500Ω
CL = 5pF
1VPP
-5
1M
10M
FREQUENCY (Hz)
-14
1M
2.5VPP
1VPP
10M
100M
300M
FREQUENCY (Hz)
FIGURE 10. INVERTING FREQUENCY RESPONSE FOR
VARIOUS OUTPUT SIGNAL LEVELS
FN7045.3
May 4, 2007
EL2125
Typical Performance Curves
(Continued)
5
3
VS = ±5V
AV = 10
RF = 180Ω
RL = 500Ω
CL = 28.5pF
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
5
CL = 16pF
1
-1
CL = 5pF
-3
CL = 1pF
-5
1M
10M
VS = ±5V
AV = 10
RF = 700Ω
RL = 500Ω
CL = 5pF
CL = 1.2pF
10M
FIGURE 11. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS CL
FIGURE 12. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS CL
6
6
NORMALIZED GAIN (dB)
CL = 29.4pF
CL = 29.4pF
NORMALIZED GAIN (dB)
CL = 16.4pF
0
CL = 11.4pF
CL = 5.1pF
CL = 1.2pF
-14
1M
10M
100M 200M
FREQUENCY (Hz)
FREQUENCY (Hz)
VS = ±5V
AV = 10
RF = 350Ω
RL = 500Ω
CL = 11pF
0
-5
1M
100M 200M
CL = 17pF
100M
2
CL = 16.4pF
-2
CL = 11.4pF
-6
CL = 5.1pF
VS = ±15V
AV = 10
RF = 500Ω
RL = 500Ω
-10
-14
1M
300M
CL = 1.2pF
10M
FREQUENCY (Hz)
100M
300M
FREQUENCY (Hz)
FIGURE 13. INVERTING FREQUENCY RESPONSE FOR
VARIOUS CL
100
FIGURE 14. INVERTING FREQUENCY RESPONSE FOR
VARIOUS CL
250
PHASE
60
50
40
-50
20
-150
VS = ±5V
0
10K
100K
1M
10M
100M
-250
400M
FREQUENCY (Hz)
FIGURE 15. OPEN LOOP GAIN AND PHASE
6
SUPPLY CURRENT (mA)
150
PHASE (°)
OPEN LOOP GAIN (dB)
12
GAIN
80
9.6
7.2
4.8
2.4
0
0
3
6
9
12
15
SUPPLY VOLTAGE (±V)
FIGURE 16. SUPPLY CURRENT vs SUPPLY VOLTAGE
FN7045.3
May 4, 2007
EL2125
Typical Performance Curves
(Continued)
3
250
PEAKING (dB)
BANDWIDTH (MHz)
2.5
AV = 10
200
AV = -10
150
100
AV = -20 AV = 20
AV = 50 AV = -50
2
AV = 10
AV = -10
1.5
1
50
AV = 20
AV = -20
AV = -50
AV = 50
0.5
0
0
2
4
6
8
10
12
14
2
16
6
8
10
12
14
16
VS (±V)
VS (±V)
VS = ±5V
RL = 500Ω
RF = 180Ω
AV = 10
CL = 5pF
VINx2
FIGURE 18. PEAKING vs SUPPLY VOLTAGE
20mV/DIV
FIGURE 17. 3dB BANDWIDTH vs SUPPLY VOLTAGE
20mV/DIV
4
VS = ±15V
RL = 500Ω
RF = 180Ω
AV = 10
CL = 5pF
VINx2
VO
VO
10ns/DIV
10ns/DIV
OUTPUT VOLTAGE (0.5V/DIV)
VS = ±5V
RL = 500Ω
RF = 180Ω
AV = 10
CL = 5pF
TIME (20ns/DIV)
FIGURE 21. LARGE SIGNAL STEP RESPONSE
7
FIGURE 20. SMALL SIGNAL STEP RESPONSE
VS = ±15V
RL = 500Ω
RF = 180Ω
AV = 10
CL = 5pF
OUTPUT VOLTAGE (0.5V/DIV)
FIGURE 19. SMALL SIGNAL STEP RESPONSE
TIME (20ns/DIV)
FIGURE 22. LARGE SIGNAL STEP RESPONSE
FN7045.3
May 4, 2007
EL2125
Typical Performance Curves
(Continued)
-40
-30
VS = ±5V
RF = 180Ω
AV = 10
RL = 500Ω
-60
VS = ±15V
RF = 180Ω
AV = 10
RL = 500Ω
-40
2ND HD
-70
-80
3RD HD
-90
-50
DISTORTION (dBc)
DISTORTION (dBc)
-50
-100
2ND HD
-60
-70
-80
3RD HD
-90
-100
-110
-110
0
1
2
3
4
5
6
0
7
5
10
VOLTAGE NOISE (nV/√Hz),
CURRENT NOISE (pA/√Hz)
THD (dBc)
100
VS = ±5V
VO = 2VPP
AV = 10
RF = 180Ω
RL = 500Ω
-60
-70
-80
-90
1K
10K
100K
1M
10M
10
IN, VS = ±5V
VN, VS = ±15V
1
VN, VS = ±5V
0.1
10
100M
100
FREQUENCY (Hz)
100K
14
VS = ±15V
VS = ±15V
VO = 5VPP
GROUP DELAY (ns)
SETTLING TIME (ns)
10K
FIGURE 26. VOLTAGE AND CURRENT NOISE vs FREQUENCY
60
VS = ±5V
VO = 5VPP
40
30
VS = ±5V
20 VO = 2VPP
10
1K
IN, VS = ±15V
FREQUENCY (Hz)
FIGURE 25. TOTAL HARMONIC DISTORTION vs FREQUENCY
50
25
FIGURE 24. 1MHz HARMONIC DISTORTION vs OUTPUT
SWING
-30
-50
20
VOUT (VPP)
VOUT (VPP)
FIGURE 23. 1MHz HARMONIC DISTORTION vs OUTPUT
SWING
-40
15
VS = ±15V
VO = 2VPP
0
0.1
1
10
ACCURACY (%)
FIGURE 27. SETTLING TIME vs ACCURACY
8
10
AV = 20
6
2
AV = 10
-2
-6
1
10
100
400
FREQUENCY (MHz)
FIGURE 28. GROUP DELAY
FN7045.3
May 4, 2007
EL2125
Typical Performance Curves
(Continued)
-10
110
-30
90
PSRR (dB)
-50
-70
-99
70
PSRR+
50
30
-110
10
100
1k
10k
100k
1M
10
10k
10M 100M
100k
FIGURE 29. CMRR
-3dB BANDWIDTH (MHz)
1
0.1
0.01
0.001
10K
100K
1M
600M
3.5
200
10
ROUT (Ω)
100M
10M
FIGURE 30. PSRR
100
10M
BANDWIDTH
160
3
2.5
120
2
PEAKING
1.5
80
1
40
0.5
0
-40
100M
FREQUENCY (Hz)
0
40
80
120
0
160
TEMPERATURE (°C)
FIGURE 31. CLOSED LOOP OUTPUT IMPEDANCE vs
FREQUENCY
FIGURE 32. BANDWIDTH vs TEMPERATURE
350
13
300
12
15VSR-
250
IS (mA)
SLEW RATE (V/µs)
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
PEAKING (dB)
CMRR (dB)
PSRR-
5VSR200
VS = ±15V
11
10
150
5VSR+
VS = ±5V
15VSR+
100
0
5
10
15
VOUT SWING (VPP)
FIGURE 33. SLEW RATE vs SWING
9
20
9
-50
0
50
100
150
DIE TEMPERATURE (°C)
FIGURE 34. SUPPLY CURRENT vs TEMPERATURE
FN7045.3
May 4, 2007
EL2125
Typical Performance Curves
(Continued)
0
-10
VS = ±5V
-15
-1
IB+ (µA)
VOS (mV)
VS = ±15V
-20
-2
-25
-3
-50
0
50
100
-30
-50
150
DIE TEMPERATURE (°C)
0
50
100
150
DIE TEMPERATURE (°C)
FIGURE 35. OFFSET VOLTAGE vs TEMPERATURE
FIGURE 36. INPUT BIAS CURRENT vs TEMPERATURE
120
110
VS = ±15V
80
PSRR (dB)
CMRR (dB)
VS = ±5V
100
VS = ±5V
60
-50
0
50
100
100
VS = ±15V
90
80
-50
150
DIE TEMPERATURE (°C)
50
100
150
DIE TEMPERATURE (°C)
FIGURE 37. CMRR vs TEMPERATURE
FIGURE 38. PSRR vs TEMPERATURE
240
3.9
VO = 2VPP
VS = ±15V
3.8
VOUTH (V)
220
SR (V/µs)
0
200
VS = ±5V
180
160
-50
3.7
VS = ±5V
3.6
0
50
100
150
DIE TEMPERATURE (°C)
FIGURE 39. SLEW RATE vs TEMPERATURE
10
3.5
-50
0
50
100
150
DIE TEMPERATURE (°C)
FIGURE 40. POSITIVE OUTPUT SWING vs TEMPERATURE
FN7045.3
May 4, 2007
EL2125
Typical Performance Curves
(Continued)
13.6
-9.75
-9.8
VOUTL (V)
VOUTH (V)
VS = ±15V
13.5
VS = ±5V
-9.85
-9.9
13.4
-50
0
50
100
-9.95
-50
150
0
50
150
100
DIE TEMPERATURE (°C)
DIE TEMPERATURE (°C)
FIGURE 41. POSITIVE OUTPUT SWING vs TEMPERATURE
FIGURE 42. NEGATIVE OUTPUT SWING vs TEMPERATURE
-13.4
-3.42
-13.5
VOUTL2 (V)
VOUTL (V)
-3.44
VS = ±15V
-13.6
-3.46
VS = ±5V
-3.48
-3.5
-13.7
-50
0
50
100
-3.52
-50
150
0
50
100
150
DIE TEMPERATURE (°C)
DIE TEMPERATURE (°C)
FIGURE 43. NEGATIVE OUTPUT SWING vs TEMPERATURE
FIGURE 44. LOADED NEGATIVE OUTPUT SWING vs
TEMPERATURE
-9.6
3.35
-10
VOUTH2 (V)
VOUTL2 (V)
-9.8
VS = ±15V
-10.2
-10.4
VS = ±5V
3.3
-10.6
-10.8
-50
0
50
100
150
DIE TEMPERATURE (°C)
FIGURE 45. NEGATIVE OUTPUT SWING vs TEMPERATURE
11
3.25
-50
0
50
100
150
DIE TEMPERATURE (°C)
FIGURE 46. LOADED POSITIVE OUTPUT SWING vs
TEMPEARTURE
FN7045.3
May 4, 2007
EL2125
Typical Performance Curves
(Continued)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
12
1.2
POWER DISSIPATION (W)
11.8
VOUTH2 (V)
VS = ±15V
11.6
11.4
11.2
11
-50
0
50
100
150
1
781mW
0.8
SO8
θJA=160°C/W
0.6
0.4 488mW
SOT23-5
θJA=256°C/W
0.2
0
0
DIE TEMPERATURE (°C)
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 47. LOADED POSITIVE OUTPUT SWING vs
TEMPERATURE
POWER DISSIPATION (W)
1.8
FIGURE 48. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.6
1.4
1.2 1.136W
SO8
θJA=110°C/W
1
0.8
0.6 543mW
0.4
SOT23-5
θJA=230°C/W
0.2
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 49. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
12
FN7045.3
May 4, 2007
EL2125
Pin Descriptions
5 LD SOT-23
8 LD SO
PIN NAME
PIN FUNCTION
1
6
VOUT
Output
EQUIVALENT CIRCUIT
VS+
VOUT
CIRCUIT 1
2
4
VS-
Supply
3
3
VINA+
Input
VS+
VIN+
VIN-
VSCIRCUIT 2
4
2
VINA-
Input
5
7
VS+
Supply
Applications Information
Product Description
The EL2125 is an ultra-low noise, wideband monolithic
operational amplifier built on Elantec's proprietary high
speed complementary bipolar process. It features
0.83nV/√Hz input voltage noise, 200µV offset voltage, and
73dB THD. It is intended for use in systems such as
ultrasound imaging where very small signals are needed to
be amplified. The EL2125 also has excellent DC
specifications: 200µV VOS, 22µA IB, 0.4µA IOS, and 106dB
CMRR. These specifications allow the EL2125 to be used in
DC-sensitive applications such as difference amplifiers.
Gain-Bandwidth Product
The EL2125 has a gain-bandwidth product of 800MHz at
±5V. For gains greater than 20, its closed-loop -3dB
bandwidth is approximately equal to the gain-bandwidth
product divided by the small signal gain of the circuit. For
gains less than 20, higher-order poles in the amplifier's
transfer function contribute to even higher closed-loop
bandwidths. For example, the EL2125 has a -3dB bandwidth
of 175MHz at a gain of 10 and decreases to 40MHz at gain
of 20. It is important to note that the extra bandwidth at lower
gain does not come at the expenses of stability. Even though
the EL2125 is designed for gain > 10 with external
13
Reference Circuit 2
compensation, the device can also operate at lower gain
settings. The RC network shown in Figure 50 reduces the
feedback gain at high frequency and thus maintains the
amplifier stability. R values must be less than RF divided by
9 and 1 divided by 2πRC must be less than 400MHz.
RF
R
C
+
VOUT
VIN
FIGURE 50.
Choice of Feedback Resistor, RF
The feedback resistor forms a pole with the input
capacitance. As this pole becomes larger, phase margin is
reduced. This increases ringing in the time domain and
peaking in the frequency domain. Therefore, RF has some
maximum value which should not be exceeded for optimum
performance. If a large value of RF must be used, a small
capacitor in the few pF range in parallel with RF can help to
reduce this ringing and peaking at the expense of reducing
the bandwidth. Frequency response curves for various RF
values are shown the in typical performance curves section
of this data sheet.
FN7045.3
May 4, 2007
EL2125
Noise Calculations
Driving Cables and Capacitive Loads
The primary application for the EL2125 is to amplify very
small signals. To maintain the proper signal-to-noise ratio, it
is essential to minimize noise contribution from the amplifier.
Figure 51 below shows all the noise sources for all the
components around the amplifier.
Although the EL2125 is designed to drive low impedance
load, capacitive loads will decrease the amplifier's phase
margin. As shown the in the performance curves, capacitive
load can result in peaking, overshoot and possible
oscillation. For optimum AC performance, capacitive loads
should be reduced as much as possible or isolated with a
series resistor between 5Ω to 20Ω. When driving coaxial
cables, double termination is always recommended for
reflection-free performance. When properly terminated, the
capacitance of the coaxial cable will not add to the capacitive
load seen by the amplifier.
R3
VIN
VR3
VN
+
-
IN+
VR1
IN-
VON
R1
VR2
Power Supply Bypassing And Printed Circuit
Board Layout
R2
As with any high frequency devices, good printed circuit
board layout is essential for optimum performance. Ground
plane construction is highly recommended. Lead lengths
should be kept as short as possible. The power supply pins
must be closely bypassed to reduce the risk of oscillation.
The combination of a 4.7µF tantalum capacitor in parallel
with 0.1µF ceramic capacitor has been proven to work well
when placed at each supply pin. For single supply operation,
where pin 4 (VS-) is connected to the ground plane, a single
4.7µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor across pins 7 (VS+) and pin 4 (VS-) will suffice.
FIGURE 51.
• VN is the amplifier input voltage noise
• IN+ is the amplifier positive input current noise
• IN- is the amplifier negative input current noise
• VRX is the thermal noise associated with each resistor:
V RX =
4kTRx
where:
• k is Boltzmann's constant = 1.380658 x 10-23
• T is temperature in degrees Kelvin (273+ °C)
The total noise due to the amplifier seen at the output of the
amplifier can be calculated by using the equation below
(Figure 52).
As the equation shows, to keep noise at a minimum, small
resistor values should be used. At higher amplifier gain
configuration where R2 is reduced, the noise due to IN-, R2,
and R1 decreases and the noise caused by IN+, VN, and R3
starts to dominate. Because noise is summed in a root-meansquares method, noise sources smaller than 25% of the largest
noise source can be ignored. This can greatly simplify the
formula and make noise calculation much easier to calculate.
Output Drive Capability
The EL2125 is designed to drive low impedance load. It can
easily drive 6VP-P signal into a 100Ω load. This high output
drive capability makes the EL2125 an ideal choice for RF, IF,
and video applications. Furthermore, the EL2125 is currentlimited at the output, allowing it to withstand momentary short to
ground. However, the power dissipation with output-shorted
cannot exceed the power dissipation capability of the package.
V ON =
For good AC performance, parasitic capacitance should be
kept to a minimum. Ground plane construction again should
be used. Small chip resistors are recommended to minimize
series inductance. Use of sockets should be avoided since
they add parasitic inductance and capacitance which will
result in additional peaking and overshoot.
Supply Voltage Range and Single Supply
Operation
The EL2125 has been designed to operate with supply
voltage range of ±2.5V to ±15V. With a single supply, the
EL2125 will operate from +5V to +30V. Pins 4 and 7 are the
power supply pins. The positive power supply is connected
to pin 7. When used in single supply mode, pin 4 is
connected to ground. When used in dual supply mode, the
negative power supply is connected to pin 4.
As the power supply voltage decreases from +30V to +5V, it
becomes necessary to pay special attention to the input
voltage range. The EL2125 has an input voltage range of
0.4V from the negative supply to 1.2V from the positive
supply. So, for example, on a single +5V supply, the EL2125
has an input voltage range which spans from 0.4V to 3.8V.
The output range of the EL2125 is also quite large, on a +5V
supply, it swings from 0.4V to 3.6V.
R 1⎞ 2
R 1⎞ 2
R 1⎞ 2⎞
⎛
⎛ R 1⎞ 2
⎛
2 ⎛
2
2
2
2 ⎛
BW × ⎜ VN × ⎜ 1 + -------⎟ + IN- × R 1 + IN+ × R 3 × ⎜ 1 + -------⎟ + 4 × K × T × R 1 + 4 × K × T × R 2 × ⎜ -------⎟ + 4 × K × T × R 3 × ⎜ 1 + -------⎟ ⎟
R 2⎠
R 2⎠
R 2⎠ ⎠
⎝
⎝
⎝
⎝ R 2⎠
⎝
FIGURE 52.
14
FN7045.3
May 4, 2007
EL2125
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
15
FN7045.3
May 4, 2007
EL2125
SOT-23 Package Family
MDP0038
e1
D
SOT-23 PACKAGE FAMILY
A
MILLIMETERS
6
N
SYMBOL
4
E1
2
E
3
0.15 C D
1
2X
2
3
0.20 C
5
2X
e
0.20 M C A-B D
B
b
NX
0.15 C A-B
1
3
SOT23-5
SOT23-6
TOLERANCE
A
1.45
1.45
MAX
A1
0.10
0.10
±0.05
A2
1.14
1.14
±0.15
b
0.40
0.40
±0.05
c
0.14
0.14
±0.06
D
2.90
2.90
Basic
E
2.80
2.80
Basic
E1
1.60
1.60
Basic
e
0.95
0.95
Basic
e1
1.90
1.90
Basic
L
0.45
0.45
±0.10
L1
0.60
0.60
Reference
N
5
6
Reference
D
2X
Rev. F 2/07
NOTES:
C
A2
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
SEATING
PLANE
A1
0.10 C
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
NX
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
(L1)
6. SOT23-5 version has no center lead (shown as a dashed line).
H
A
GAUGE
PLANE
c
L
0.25
0° +3°
-0°
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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16
FN7045.3
May 4, 2007
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