DATASHEET

EL2126
®
Data Sheet
May 2, 2007
Ultra-Low Noise, Low Power, Wideband
Amplifier
The EL2126 is an ultra-low noise, wideband amplifier that
runs on half the supply current of competitive parts. It is
intended for use in systems such as ultrasound imaging
where a very small signal needs to be amplified by a large
amount without adding significant noise. Its low power
dissipation enables it to be packaged in the tiny SOT-23
package, which further helps systems where many input
channels create both space and power dissipation problems.
The EL2126 is stable for gains of 10 and greater and uses
traditional voltage feedback. This allows the use of reactive
elements in the feedback loop, a common requirement for
many filter topologies. It operates from ±2.5V to ±15V
supplies and is available in the 5 Ld SOT-23 and 8 Ld SO
packages.
The EL2126 is fabricated in Elantec’s proprietary
complementary bipolar process, and is specified for
operation over the full -40°C to +85°C temperature range.
FN7046.4
Features
• Voltage noise of only 1.3nV/√Hz
• Current noise of only 1.2pA/√Hz
• 200µV offset voltage
• 100MHz -3dB BW for AV = 10
• Very low supply current - 4.7mA
• SOT-23 package
• ±2.5V to ±15V operation
• Pb-free plus anneal available (RoHS compliant)
Applications
• Ultrasound input amplifiers
• Wideband instrumentation
• Communication equipment
• AGC and PLL active filters
• Wideband sensors
Pinouts
EL2126
(5 LD SOT-23)
TOP VIEW
OUT 1
5 VS+
VS- 2
+
-
IN+ 3
4 IN-
EL2126
(8 LD SOIC)
TOP VIEW
8 NC
NC 1
IN- 2
IN+ 3
7 VS+
+
6 OUT
5 NC
VS- 4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2005, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL2126
Ordering Information
PART
NUMBER
PART
MARKING
TEMP RANGE
(°C)
TAPE AND REEL
PACKAGE
PKG. DWG. #
EL2126CW-T7
G
-40 to +85
7” (3k pcs)
5 Ld SOT-23
MDP0038
EL2126CW-T7A
G
-40 to +85
7” (250 pcs)
5 Ld SOT-23
MDP0038
EL2126CS
2126CS
-40 to +85
-
8 Ld SOIC (150 mil)
MDP0027
EL2126CS-T7
2126CS
-40 to +85
7”
8 Ld SOIC (150 mil)
MDP0027
EL2126CS-T13
2126CS
-40 to +85
13”
8 Ld SOIC (150 mil)
MDP0027
EL2126CSZ ( Note)
2126CSZ
-40 to +85
-
8 Ld SOIC (150 mil)
(Pb-free)
MDP0027
EL2126CSZ-T7 ( Note)
2126CSZ
-40 to +85
7”
8 Ld SOIC (150 mil)
(Pb-free)
MDP0027
EL2126CSZ-T13 ( Note)
2126CSZ
-40 to +85
13”
8 Ld SOIC (150 mil)
(Pb-free)
MDP0027
EL2126CWZ-T7 (Note)
BAAH
-40 to +85
7”
5 Ld SOT-23 (SC74)
(1.65mm) (Green)
P5.064
EL2126CWZ-T7A (Note)
BAAH
-40 to +85
7”
5 Ld SOT-23 (SC74)
(1.65mm) (Green)
P5.064
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN7046.4
May 2, 2007
EL2126
Absolute Maximum Ratings
Thermal Information
VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
Any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . VS+ -0.3V to VS- +0.3V
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-60°C to +150°C
Maximum Die Junction Temperature . . . . . . . . . . . . . . . . . . . +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
Parameter
VS+ = +5V, VS- = -5V, TA = +25°C, RF = 180Ω, RG = 20Ω, RL = 500Ω Unless Otherwise Specified.
Description
Conditions
Min
Typ
Max
Unit
0.2
2
mV
3
mV
DC PERFORMANCE
VOS
Input Offset Voltage (SO8)
Input Offset Voltage (SOT23-5)
TCVOS
Offset Voltage Temperature
Coefficient
IB
Input Bias Current
IOS
Input Bias Current Offset
0.06
TCIB
Input Bias Current Temperature
Coefficient
0.013
µA/°C
CIN
Input Capacitance
2.2
pF
AVOL
Open Loop Gain
80
87
dB
PSRR
Power Supply Rejection Ratio
(Note 1)
80
100
dB
CMRR
Common Mode Rejection Ratio
75
106
dB
CMIR
Common Mode Input Range
VOUTH
Positive Output Voltage Swing
No load, RF = 1kΩ
VOUTL
Negative Output Voltage Swing
No load, RF = 1kΩ
VOUTH2
Positive Output Voltage Swing
RL = 100Ω
VOUTL2
Negative Output Voltage Swing
RL = 100Ω
IOUT
Output Short Circuit Current
(Note 2)
ISY
Supply Current
-10
VO = -2.5V to +2.5V
at CMIR
17
µV/°C
-7
µA
-4.6
3.8
3.8
3.8
-4
3.2
-3.9
V
V
V
-3.2
100
4.7
µA
V
3.45
-3.5
80
0.6
V
mA
5.5
mA
AC PERFORMANCE - RG = 20Ω, CL = 3pF
BW
-3dB Bandwidth, RL = 500Ω
100
MHz
BW ±0.1dB
±0.1dB Bandwidth, RL = 500Ω
17
MHz
BW ±1dB
±1dB Bandwidth, RL = 500Ω
80
MHz
Peaking
Peaking, RL = 500Ω
0.6
dB
SR
Slew Rate
VOUT = 2VP-P, measured at 20% to 80%
110
V/µs
OS
Overshoot, 4VP-P Output Square
Wave
Positive
2.8
%
Negative
-7
%
51
ns
tS
Settling Time to 0.1% of ±1V Pulse
3
80
FN7046.4
May 2, 2007
EL2126
Electrical Specifications
Parameter
VS+ = +5V, VS- = -5V, TA = +25°C, RF = 180Ω, RG = 20Ω, RL = 500Ω Unless Otherwise Specified.
Description
Conditions
Min
Typ
Max
Unit
VN
Voltage Noise Spectral Density
1.3
nV/√Hz
IN
Current Noise Spectral Density
1.2
pA/√Hz
HD2
2nd Harmonic Distortion (Note 3)
-70
dBc
HD3
3rd Harmonic Distortion (Note 3)
-70
dBc
NOTES:
1. Measured by moving the supplies from ±4V to ±6V
2. Pulse test only and using a 10Ω load
3. Frequency = 1MHz, VOUT = 2VP-P, into 500Ω and 5pF load
VS+ = +15V, VS- = -15V, TA = 25°C, RF = 180Ω, RG = 20Ω, RL = 500Ω unless otherwise specified.
Electrical Specifications
Parameter
Description
Conditions
Min
Typ
Max
Unit
0.5
3
mV
3
mV
DC PERFORMANCE
VOS
Input Offset Voltage (SO8)
Input Offset Voltage (SOT23-5)
TCVOS
Offset Voltage Temperature
Coefficient
IB
Input Bias Current
IOS
Input Bias Current Offset
0.12
TCIB
Input Bias Current Temperature
Coefficient
0.016
µA/°C
CIN
Input Capacitance
2.2
pF
AVOL
Open Loop Gain
80
90
dB
PSRR
Power Supply Rejection Ratio
(Note 4)
65
80
dB
CMRR
Common Mode Rejection Ratio
70
85
dB
CMIR
Common Mode Input Range
VOUTH
Positive Output Voltage Swing
No load, RF = 1kΩ
VOUTL
Negative Output Voltage Swing
No load, RF = 1kΩ
VOUTH2
Positive Output Voltage Swing
RL = 100Ω, RF = 1kΩ
VOUTL2
Negative Output Voltage Swing
RL = 100Ω, RF = 1kΩ
IOUT
Output Short Circuit Current
(Note 5)
ISY
Supply Current
-10
at CMIR
4.5
µV/°C
-7
µA
-14.6
13.6
13.8
13.7
-13.8
10.2
-13.7
V
V
V
-9.5
220
5
µA
V
11.2
-10.3
140
0.7
V
mA
6
mA
AC PERFORMANCE - RG = 20Ω, CL = 3pF
BW
-3dB Bandwidth, RL = 500Ω
135
MHz
BW ±0.1dB
±0.1dB Bandwidth, RL = 500Ω
26
MHz
BW ±1dB
±1dB Bandwidth, RL = 500Ω
60
MHz
Peaking
Peaking, RL = 500Ω
2.1
dB
SR
Slew Rate (±2.5V Square Wave,
Measured 25%-75%)
150
V/µS
OS
Overshoot, 4VP-P Output Square
Wave
Positive
1.6
%
Negative
-4.4
%
48
ns
TS
Settling Time to 0.1% of ±1V Pulse
4
130
FN7046.4
May 2, 2007
EL2126
VS+ = +15V, VS- = -15V, TA = 25°C, RF = 180Ω, RG = 20Ω, RL = 500Ω unless otherwise specified. (Continued)
Electrical Specifications
Parameter
Description
Conditions
Min
Typ
Max
Unit
VN
Voltage Noise Spectral Density
1.4
nV/√Hz
IN
Current Noise Spectral Density
1.1
pA/√Hz
HD2
2nd Harmonic Distortion (Note 6)
-72
dBc
HD3
3rd Harmonic Distortion (Note 6)
-73
dBc
NOTES:
4. Measured by moving the supplies from ±13.5V to ±16.5V
5. Pulse test only and using a 10Ω load
6. Frequency = 1MHz, VOUT = 2VP-P, into 500Ω and 5pF load
Typical Performance Curves
10
VS = ±5V
AV = 10
CL = 5pF
RL = 500Ω
6
RF = 1kΩ
RF = 500Ω
2
-2
RF = 180Ω
-6
RF = 100Ω
-10
1M
10M
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
10
6
VS = ±15V
AV = 10
CL = 5pF
RL = 500Ω
-2
RF = 180Ω
RF = 100Ω
-6
10M
FREQUENCY (Hz)
FIGURE 2. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
8
8
VS = ±5V
AV = -10
CL = 5pF
RL = 500Ω
RF = 500Ω
RF = 1kΩ
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
100M
FREQUENCY (Hz)
FIGURE 1. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
4
RF = 500Ω
2
-10
1M
100M
RF = 1kΩ
RF = 350Ω
0
-4
RF = 200Ω
RF = 100Ω
-8
-12
1M
10M
100M
FREQUENCY (Hz)
FIGURE 3. INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
5
4
VS = ±15V
AV = -10
CL = 5pF
RL = 500Ω
RF = 1kΩ
RF = 500Ω
RF = 350Ω
0
-4
RF = 200Ω
RF = 100Ω
-8
-12
1M
10M
100M
FREQUENCY (Hz)
FIGURE 4. INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
FN7046.4
May 2, 2007
EL2126
Typical Performance Curves (Continued)
10
VS = ±5V
RG = 20Ω
RL = 500Ω
CL = 5pF
6
2
AV = 10
AV = 20
-2
AV = 50
-6
-10
1M
10M
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
10
6
VS = ±15V
RG = 20Ω
RL = 500Ω
CL = 5pF
AV = 10
2
AV = 20
-2
AV = 50
-6
-10
1M
100M
10M
FREQUENCY (Hz)
FIGURE 5. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS GAIN
FIGURE 6. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS GAIN
8
VS = ±5V
CL = 5pF
RG = 35Ω
4
0
AV = -10
-4
AV = -50
AV = -20
-8
-12
1M
10M
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
8
VS = ±15V
CL = 5pF
RG = 20Ω
4
0
AV = -10
-4
AV = -50
-12
1M
100M
10M
100M
FREQUENCY (Hz)
FIGURE 7. INVERTING FREQUENCY RESPONSE FOR
VARIOUS GAIN
FIGURE 8. INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
10
VS = ±5V
CL = 5pF
RL = 500Ω
RF = 180Ω
AV = 10
0
-4
-8
-12
1M
VO = 500mVPP
VO = 30mVPP
VO = 5VPP
VO = 2.5VPP
VO = 1VPP
10M
100M
FREQUENCY (Hz)
FIGURE 9. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS OUTPUT SIGNAL LEVELS
6
NORMALIZED GAIN (dB)
8
NORMALIZED GAIN (dB)
AV = -20
-8
FREQUENCY (Hz)
4
100M
FREQUENCY (Hz)
6
VS = ±15V
CL = 5pF
RL = 500Ω
RF = 180Ω
AV = 10
VO = 30mVPP
VO = 500mVPP
2
-2
-6
-10
1M
VO = 1VPP
VO = 10VPP
VO = 5VPP
VO = 2.5VPP
10M
100M
FREQUENCY (Hz)
FIGURE 10. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS OUTPUT SIGNAL LEVELS
FN7046.4
May 2, 2007
EL2126
Typical Performance Curves (Continued)
4
8
VS = ±5V
CL = 5pF
RL = 500Ω
RF = 350Ω
AV = 10
VO = 500mVPP
VO = 30mVPP
VO = 1VPP
0
VO = 3.4VPP
-4
VO = 2.5VPP
-8
-12
1M
10M
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
8
4
VS = ±15V
CL = 5pF
RL = 500Ω
RF = 200Ω
AV = 10
VO = 3.4VPP
-4
VOV=O2.5V
=2.5V
PPP
-8
10M
FREQUENCY (Hz)
FIGURE 12. INVERTING FREQUENCY RESPONSE FOR
VARIOUS OUTPUT SIGNAL LEVELS
10
VS = ±5V
RF = 150Ω
AV = 10
RL = 500Ω
6
CL = 28pF
CL = 11pF
2
CL = 16pF
CL = 5pF
-2
CL = 1pF
-6
-10
1M
10M
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
10
6
VS = ±15V
RF = 180Ω
AV = 10
RL = 500Ω
CL = 11pF
CL = 16pF
CL = 5pF
-2
CL = 1.2pF
-6
-10
1M
100M
CL = 28pF
2
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 13. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS CL
FIGURE 14. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS CL
8
8
VS = ±5V
RF = 350Ω
RL = 500Ω
AV = -10
CL = 28pF
CL = 16pF
0
CL = 11pF
-4
CL = 5pF
CL = 1.2pF
-8
-12
1M
10M
100M
FREQUENCY (Hz)
FIGURE 15. INVERTING FREQUENCY RESPONSE FOR
VARIOUS CL
7
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
100M
FREQUENCY (Hz)
FIGURE 11. INVERTING FREQUENCY RESPONSE FOR
VARIOUS OUTPUT SIGNAL LEVELS
4
VO = 30mVPP
VO = 1VPP
0
-12
1M
100M
VO = 500mVPP
4
VS = ±15V
RF = 200Ω
RL = 500Ω
AV = -10
CL = 28pF
CL = 16pF
0
CLC=L=11p
11pF
-4
CL = 5pF
CL = 1.2pF
-8
-12
1M
10M
100M
FREQUENCY (Hz)
FIGURE 16. INVERTING FREQUENCY RESPONSE FOR
VARIOUS CL
FN7046.4
May 2, 2007
EL2126
Typical Performance Curves (Continued)
100
250
OPEN LOOP GAIN (dB)
PHASE
60
50
40
-50
20
-150
VS=±5V
0
10k
100k
1M
10M
SUPPLY CURRENT (mA)
150
80
OPEN LOOP PHASE (°)
GAIN
0.6/DIV
-250
1G
100M
0
0
1.5/DIV
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
FIGURE 17. OPEN LOOP GAIN AND OPEN LOOP PHASE
FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE
3.0
160
VS = ±5V
RG = 20Ω
RL = 500Ω
CL = 5pF
120
AV = -10
AV = 10
100
80
AV = -20
60
40
AV = -20
AV = -50
20
AV = 50
0
0
2
4
6
8
10
VS = ±5V
RG = 20Ω
RL = 500Ω
CL = 5pF
2.5
PEAKING (dB)
-3dB BANDWIDTH
140
12
14
2.0
AV = 10
1.5
1.0
0.5
AV = -10
0
16
0
4
6
8
10
12
14
16
FIGURE 20. PEAKING vs Vs
FIGURE 19. BANDWIDTH vs Vs
RF = 180Ω
RG = 20Ω
2
±SUPPLY VOLTAGE (V)
±VS (V)
VS = ±5V
VO = 2VPP
0.5V/DIV
20mV/DIV
RF = 180Ω
RG = 20Ω
VS = ±5V
VO = 100mVPP
10ns/DIV
FIGURE 21. LARGE SIGNAL STEP RESPONSE
8
10ns/DIV
FIGURE 22. SMALL SIGNAL STEP RESPONSE
FN7046.4
May 2, 2007
EL2126
Typical Performance Curves (Continued)
-30
VS = ±5V
VO = 2VP-P
RF = 180Ω
AV = 10
RL = 500Ω
-50
-60
HARMONIC DISTORTION (dBc)
HARUMONIC DISTORTION (dBc)
-40
2nd HD
-70
-80
3rd HD
-90
-100
VS = ±5V
VO = 2VP-P
RF = 180Ω
AV = 10
RL = 500Ω
-40
-50
-60
-70
3rd HD
-80
-90
-100
0
1
2
3
4
5
6
7
8
0
5
10
VOUT (VP-P)
20
25
FIGURE 24. 1MHz HARMONIC DISTORTION vs OUTPUT
SWING
-20
10
VS = ±5V
VO = 2VP-P
IN (pA/√Hz), VN (nV/√Hz)
-30
15
VOUT (VP-P)
FIGURE 23. 1MHz HARMONIC DISTORTION vs OUTPUT
SWING
-40
THD (dBc)
2nd HD
-50
-60
-70
IN, VS = ±5V
VN, VS = ±15V
VN, VS = ±5V
-80
-90
1k
10k
100k
1M
10M
1
10
100M
IN, VS = ±15V
100
FREQUENCY (Hz)
FIGURE 25. TOTAL HARMONIC DISTORTION vs FREQUENCY
40
30
20
100k
16
VS =
±5 V
,V
VS =
±15
V, V
VS =
±5V
,V
VS =
±15V
,V
12
O=5
VP
-P
GROUP DELAY (ns)
SETTLING TIME (ns)
50
10k
FIGURE 26. NOISE vs FREQUENCY
70
60
1k
FREQUENCY (Hz)
O=5
VP
-P
O=2
VP
-P
O=2
VP
-P
VS = ±5V
RL = 500Ω
AV = 10
8
4
AV = -10
0
10
0
0.1
1.0
10.0
ACCURACY (%)
FIGURE 27. SETTLING TIME vs ACCURACY
9
-4
1M
10M
100M
400M
FREQUENCY (Hz)
FIGURE 28. GROUP DELAY vs FREQUENCY
FN7046.4
May 2, 2007
EL2126
Typical Performance Curves (Continued)
-10
110
VS=±5V
90
PSRR (dB)
-50
-70
PSRR-
70
50
-90
PSRR+
30
-110
10
100
1k
10k
100k
1M
10M
10
10k
100M
100k
FREQUENCY (Hz)
FIGURE 29. CMRR vs FREQUENCY
CLOSED LOOP OUTPUT IMPEDANCE (Ω)
1M
10M
200M
FREQUENCY (Hz)
FIGURE 30. PSRR vs FREQUENCY
3.5
120
100
VS = ±5V
VS = ±5V
3
100
2.5
BANDWIDTH (MHz)
10
1
0.1
80
BANDWIDTH
2
1.5
60
1
40
PEAKING
0.5
20
0.01
10k
1M
100k
0
0
-40
100M
10M
FREQUENCY (Hz)
-0.5
0
40
80
120
160
TEMPERATURE (°C)
FIGURE 31. CLOSED LOOP OUTPUT IMPEDANCE vs
FREQUENCY
FIGURE 32. BANDWIDTH AND PEAKING vs TEMPERATURE
5.2
220
15VSR-
200
VS=±15V
5.1
180
160
15VSR+
IS (mA)
SLEW RATE (V/µs)
PEAKING (dB)
CMRR (dB)
-30
140
120
5
VS=±5V
5VSR-
100
4.9
5VSR+
80
60
-1
1
3
5
7
9
11
13
VOUT SWING (VPP)
FIGURE 33. SLEW RATE vs SWING
10
15
4.8
-50
0
50
100
150
DIE TEMPERATURE (°C)
FIGURE 34. SUPPLY CURRENT vs TEMPERATURE
FN7046.4
May 2, 2007
EL2126
Typical Performance Curves (Continued)
1
120
VS = ±5V
110
CMRR (dB)
VOS (mV)
0
VS = ±15V
VS = ±5V
100
-1
90
-2
-50
0
50
100
80
-50
150
DIE TEMPERATURE (°C)
0
50
100
150
DIE TEMPERATURE (°C)
FIGURE 35. OFFSET VOLTAGE vs TEMPERATURE
FIGURE 36. CMRR vs TEMPERATURE
110
4.05
106
4
VS = ±5V
VOUTH (V)
PSRR (dB)
102
98
94
3.95
VS = ±5V
3.9
90
VS = ±15V
3.85
86
82
-50
0
50
100
3.8
-50
150
DIE TEMPERATURE (°C)
0
50
100
150
DIE TEMPERATURE (°C)
FIGURE 37. PSRR vs TEMPERATURE
FIGURE 38. POSITIVE OUTPUT SWING vs TEMPERATURE
13.85
-3.9
-3.95
13.8
VOUTL (V)
VOUTH (V)
-4
VS = ±15V
13.75
13.7
VS = ±5V
-4.05
-4.1
-4.15
13.65
-4.2
13.6
-50
0
50
100
150
DIE TEMPERATURE (°C)
FIGURE 39. POSITIVE OUTPUT SWING vs TEMPERATURE
11
-4.25
-50
0
50
100
150
DIE TEMPERATURE (°C)
FIGURE 40. NEGATIVE OUTPUT SWING vs TEMPERATURE
FN7046.4
May 2, 2007
EL2126
Typical Performance Curves (Continued)
-13.76
102
SLEW RATE (V/µs)
100
VOUTL (V)
-13.78
VS = ±15V
-13.8
VS = ±5V
98
96
94
92
90
-13.82
-50
0
50
100
88
-50
150
DIE TEMPERATURE (°C)
150
3.5
VS = ±15V
VOUTH2 (V)
SR (V/µs)
3.52
145
140
150
VS = ±5V
3.48
3.46
VO = 2VPP
0
50
100
3.44
-50
150
DIE TEMPERATURE (°C)
0
50
100
150
DIE TEMPERATURE (°C)
FIGURE 43. SLEW RATE vs TEMPERATURE
FIGURE 44. POSITIVE LOADED OUTPUT SWING vs
TEMPERATURE
11.8
-3.35
11.6
-3.4
VS = ±15V
VOUTL2 (V)
11.4
SR (V/µs)
100
FIGURE 42. SLEW RATE vs TEMPERATURE
155
11.2
11
-3.45
-3.5
VS = ±5V
3.55
10.8
10.6
-50
50
DIE TEMPERATURE (°C)
FIGURE 41. NEGATIVE OUTPUT SWING vs TEMPERATURE
135
-50
0
0
50
100
150
DIE TEMPERATURE (°C)
FIGURE 45. POSITIVE LOADED OUTPUT SWING vs
TEMPERATURE
12
-3.6
-50
0
50
100
150
DIE TEMPERATURE (°C)
FIGURE 46. NEGATIVE LOADED OUTPUT SWING vs
TEMPERATURE
FN7046.4
May 2, 2007
EL2126
Typical Performance Curves (Continued)
-9.4
VOUTL2 (V)
-9.6
-9.8
VS=±15V
-10
-10.2
-10.4
-10.6
-50
0
50
100
150
Die Temperature (°C)
FIGURE 47. NEGATIVE LOADED OUTPUT SWING vs TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.8
1.6
1
POWER DISSIPATION (W)
POWER DISSIPATION (W)
1.2
781mW
0.8
θJ
A=
+1
0.6
488mW
0.4
0.2
SO
8
60
°C
/W
SO
T23
θJ
-5
A=+
256
°C/W
1.4
1.2 1.136W
θJ
1
0.6 543mW
0.4
0.2
0
0
25
50
75 85 100
125
150
AMBIENT Temperature (°C)
FIGURE 48. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
13
SO
A=
+1
0.8
8
10
°C
/W
SOT
23-5
θJ
A = +2
30°C
/W
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 49. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7046.4
May 2, 2007
EL2126
Pin Descriptions
EL2126CW
(5 Ld SOT-23)
EL2126CS
( 8 Ld SOIC)
PIN NAME
PIN FUNCTION
1
6
VOUT
Output
EQUIVALENT CIRCUIT
VS+
VOUT
Circuit 1
2
4
VS-
Supply
3
3
VINA+
Input
VS+
VIN+
VIN-
VSCircuit 2
4
2
VINA-
Input
5
7
VS+
Supply
14
Reference Circuit 2
FN7046.4
May 2, 2007
EL2126
Applications Information
Noise Calculations
Product Description
The EL2126 is an ultra-low noise, wideband monolithic
operational amplifier built on Elantec's proprietary high
speed complementary bipolar process. It features 1.3nV/√Hz
input voltage noise, 200µV typical offset voltage, and 73dB
THD. It is intended for use in systems such as ultrasound
imaging where very small signals are needed to be
amplified. The EL2126 also has excellent DC specifications:
200µV VOS, 22µA IB, 0.4µA IOS, and 106dB CMRR. These
specifications allow the EL2126 to be used in DC-sensitive
applications such as difference amplifiers.
The primary application for the EL2126 is to amplify very
small signals. To maintain the proper signal-to-noise ratio, it
is essential to minimize noise contribution from the amplifier.
Figure 51 shows all the noise sources for all the components
around the amplifier.
VIN
R3
VR3
VR1
IN-
VON
R1
VR2
R2
The EL2126 has a gain-bandwidth product of 650MHz at
±5V. For gains less than 20, higher-order poles in the
amplifier's transfer function contribute to even higher closedloop bandwidths. For example, the EL2126 has a -3dB
bandwidth of 100MHz at a gain of 10 and decreases to
33MHz at gain of 20. It is important to note that the extra
bandwidth at lower gain does not come at the expenses of
stability. Even though the EL2126 is designed for gain ≥ 10.
With external compensation, the device can also operate at
lower gain settings. The RC network shown in Figure 50
reduces the feedback gain at high frequency and thus
maintains the amplifier stability. R values must be less than
RF divided by 9 and 1 divided by 2πRC must be less than
200MHz.
RF
FIGURE 51.
VN is the amplifier input voltage noise
IN+ is the amplifier positive input current noise
IN- is the amplifier negative input current noise
VRX is the thermal noise associated with each resistor:
V RX =
4kTRx
(EQ. 1)
where:
k is Boltzmann's constant = 1.380658 x 10-23
T is temperature in degrees Kelvin (273 + °C)
R
+
+
-
IN+
Gain-Bandwidth Product
C
VN
VOUT
The total noise due to the amplifier seen at the output of the
amplifier can be calculated by using the Equation 2.
VIN
FIGURE 50.
Choice of Feedback Resistor, RF
The feedback resistor forms a pole with the input
capacitance. As this pole becomes larger, phase margin is
reduced. This increases ringing in the time domain and
peaking in the frequency domain. Therefore, RF has some
maximum value which should not be exceeded for optimum
performance. If a large value of RF must be used, a small
capacitor in the few pF range in parallel with RF can help to
reduce this ringing and peaking at the expense of reducing
the bandwidth. Frequency response curves for various RF
values are shown in the typical performance curves section
of this data sheet.
V ON =
As the equation shows, to keep noise at a minimum, small
resistor values should be used. At higher amplifier gain
configuration where R2 is reduced, the noise due to IN-, R2,
and R1 decreases and the noise caused by IN+, VN, and R3
starts to dominate. Because noise is summed in a rootmean-squares method, noise sources smaller than 25% of
the largest noise source can be ignored. This can greatly
simplify the formula and make noise calculation much easier
to calculate.
R 1⎞ 2
R 1⎞ 2
R 1⎞ 2⎞
⎛ R 1⎞ 2
⎛
⎛
2
2 ⎛
2 ⎛
2
2
BW × ⎜ VN × ⎜ 1 + -------⎟ + IN- × R 1 + IN+ × R 3 × ⎜ 1 + -------⎟ + 4 × K × T × R 1 + 4 × K × T × R 2 × ⎜ -------⎟ + 4 × K × T × R 3 × ⎜ 1 + -------⎟ ⎟
R 2⎠
R 2⎠
R 2⎠ ⎠
⎝ R 2⎠
⎝
⎝
⎝
⎝
(EQ. 2)
15
FN7046.4
May 2, 2007
EL2126
Output Drive Capability
The EL2126 is designed to drive low impedance load. It can
easily drive 6VP-P signal into a 100Ω load. This high output
drive capability makes the EL2126 an ideal choice for RF, IF,
and video applications. Furthermore, the EL2126 is
current-limited at the output, allowing it to withstand
momentary short to ground. However, the power dissipation
with output-shorted cannot exceed the power dissipation
capability of the package.
Driving Cables and Capacitive Loads
Although the EL2126 is designed to drive low impedance
load, capacitive loads will decreases the amplifier's phase
margin. As shown in the performance curves, capacitive
load can result in peaking, overshoot and possible
oscillation. For optimum AC performance, capacitive loads
should be reduced as much as possible or isolated with a
series resistor between 5Ω to 20Ω. When driving coaxial
cables, double termination is always recommended for
reflection-free performance. When properly terminated, the
capacitance of the coaxial cable will not add to the capacitive
load seen by the amplifier.
Power Supply Bypassing And Printed Circuit
Board Layout
As with any high frequency devices, good printed circuit
board layout is essential for optimum performance. Ground
plane construction is highly recommended. Lead lengths
should be kept as short as possible. The power supply pins
must be closely bypassed to reduce the risk of oscillation.
The combination of a 4.7µF tantalum capacitor in parallel
16
with 0.1µF ceramic capacitor has been proven to work well
when placed at each supply pin. For single supply operation,
where pin 4 (VS-) is connected to the ground plane, a single
4.7µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor across pins 7 (VS+) and pin 4 (VS-) will suffice.
For good AC performance, parasitic capacitance should be
kept to a minimum. Ground plane construction again should
be used. Small chip resistors are recommended to minimize
series inductance. Use of sockets should be avoided since
they add parasitic inductance and capacitance which will
result in additional peaking and overshoot.
Supply Voltage Range and Single Supply
Operation
The EL2126 has been designed to operate with supply
voltage range of ±2.5V to ±15V. With a single supply, the
EL2126 will operate from +5V to +30V. Pins 4 and 7 are the
power supply pins. The positive power supply is connected
to pin 7. When used in single supply mode, pin 4 is
connected to ground. When used in dual supply mode, the
negative power supply is connected to pin 4.
As the power supply voltage decreases from +30V to +5V, it
becomes necessary to pay special attention to the input
voltage range. The EL2126 has an input voltage range of
0.4V from the negative supply to 1.2V from the positive
supply. So, for example, on a single +5V supply, the EL2126
has an input voltage range which spans from 0.4V to 3.8V.
The output range of the EL2126 is also quite large, on a +5V
supply, it swings from 0.4V to 3.8V.
FN7046.4
May 2, 2007
EL2126
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
17
FN7046.4
May 2, 2007
EL2126
Small Outline Transistor Plastic Packages (SOT23-5)
P5.064
D
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
VIEW C
e1
INCHES
5
SYMBOL
4
E
CL
1
2
CL
3
e
E1
b
CL
α
0.20 (0.008) M
C
C
CL
A
A2
SEATING
PLANE
A1
-C-
WITH
b
PLATING
b1
c
c1
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.036
0.057
0.90
1.45
-
A1
0.000
0.0059
0.00
0.15
-
A2
0.036
0.051
0.90
1.30
-
b
0.012
0.020
0.30
0.50
-
b1
0.012
0.018
0.30
0.45
c
0.003
0.009
0.08
0.22
6
c1
0.003
0.008
0.08
0.20
6
D
0.111
0.118
2.80
3.00
3
E
0.103
0.118
2.60
3.00
-
E1
0.060
0.067
1.50
1.70
3
e
0.0374 Ref
0.95 Ref
-
e1
0.0748 Ref
1.90 Ref
-
L
0.10 (0.004) C
MIN
0.014
0.022
0.35
0.55
L1
0.024 Ref.
0.60 Ref.
L2
0.010 Ref.
0.25 Ref.
N
5
5
4
5
R
0.004
-
0.10
-
R1
0.004
0.010
0.10
0.25
α
0o
8o
0o
8o
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC-74 and JEDEC MO178AA.
4X θ1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
GAUGE PLANE
SEATING
PLANE
L
C
L1
α
L2
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
4X θ1
VIEW C
18
FN7046.4
May 2, 2007
EL2126
SOT-23 Package Family
MDP0038
e1
SOT-23 PACKAGE FAMILY
D
A
MILLIMETERS
6
N
SYMBOL
4
E1
2
E
3
0.15 C D
1
2X
2
3
0.20 C
5
2X
e
0.20 M C A-B D
B
b
NX
0.15 C A-B
1
3
SOT23-5
SOT23-6
TOLERANCE
A
1.45
1.45
MAX
A1
0.10
0.10
±0.05
A2
1.14
1.14
±0.15
b
0.40
0.40
±0.05
c
0.14
0.14
±0.06
D
2.90
2.90
Basic
E
2.80
2.80
Basic
E1
1.60
1.60
Basic
e
0.95
0.95
Basic
e1
1.90
1.90
Basic
L
0.45
0.45
±0.10
L1
0.60
0.60
Reference
N
5
6
Reference
Rev. F 2/07
D
2X
NOTES:
C
A2
SEATING
PLANE
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
A1
0.10 C
3. This dimension is measured at Datum Plane “H”.
NX
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
(L1)
6. SOT23-5 version has no center lead (shown as a dashed line).
H
A
GAUGE
PLANE
c
L
0.25
0° +3°
-0°
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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19
FN7046.4
May 2, 2007
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