ESIGNS NEW D R O F D DE T PART CEMEN OMME N A C L E P R E T DR NO MENDE L5172 Data Sheet RECOM E EL2142 ® February 11, 2005 Differential Line Receiver Features The EL2142 is a very high bandwidth amplifier designed to extract the difference signal from noisy environments, and is thus primarily targeted for applications such as receiving signals from twisted pair lines, or any application where common mode noise injection is likely to occur. • Differential input range ±2.3V The EL2142 is stable for a gain of one, and requires two external resistors to set the voltage gain. • 50mA minimum output current The output common mode level is set by the reference pin (VREF), which has a -3dB bandwidth of over 100MHz. Generally, this pin is grounded, but it can be tied to any voltage reference. • Low power-11mA typical supply current The output can deliver a minimum of ±50mA and is short circuit protected to withstand a temporary overload condition. • 150MHz 3dB bandwidth • 400V/µs slewrate • ±5V supplies or single supply • Output swing (100Ω load) to within 1.5V of supplies • Pb-free available (RoHS compliant) Applications • Twisted pair receiver • Differential line receiver • VGA over twisted pair Ordering Information PART NUMBER FN7049.1 • ADSL/HDSL receiver PACKAGE TAPE & REEL PKG. DWG. # EL2142CS 8-pin SOIC - MDP0027 • Reception of analog signals in a noisy environment. EL2142CS-T7 8-pin SOIC 7” MDP0027 EL2142CS-T13 8-pin SOIC 13” MDP0027 Pinout EL2142CSZ (See Note) 8-pin SOIC (Pb-free) - MDP0027 EL2142CSZ-T7 (See Note) 8-pin SOIC (Pb-free) 7” MDP0027 EL2142CSZT13 (See Note) 8-pin SOIC (Pb-free) 13” MDP0027 • Differential to single ended amplification. EL2142 (8-PIN SOIC) TOP VIEW NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1998, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL2142 Absolute Maximum Ratings (TA = 25°C) Supply Voltage (VCC–VEE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6V Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Recommended Operating Temperature . . . . . . . . . . . -40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications VCC = +5V, VEE = -5V, TEE = 25°C, VIN= 0V, RL = 100, unless otherwise specified PARAMETER DESCRIPTION MIN TYP MAX UNITS ±3.0 ±5.0 ±6.3 V 11 14 mA VSUPPLY Supply Operating Range (VCC-VEE) IS Power Supply Current (no load) VOS Input Referred Offset Voltage -25 10 40 mV IIN Input Bias Current (VIN, VINB, VREF) -20 6 20 µA ZIN Differential Input Resistance CIN Differential Input Capacitance VDIFF Differential Input Range AVOL Open Loop Voltage Gain VIN Input Common Mode Voltage Range -2.6 VOUT Output Voltage Swing (50Ω load to GND) ±2.9 ±3.1 V IOUT(min) Minimum Output Current 50 60 mA VN Input Referred Voltage Noise 36 nV/√Hz VREF Output Voltage Control Range -2.5 PSRR Power Supply Rejection Ratio 60 70 dB CMRR2 Input Common Mode Rejection Ratio (VIN= ±2V) 60 70 dB CMRR1 Input Common Mode Rejection Ratio (full VIN range) 50 60 dB AC Electrical Specifications ±2.0 400 kΩ 1 pF ±2.3 V 75 dB +4.0 +3.3 V V VCC = +5V, VEE = -5V, TA = 25C, VIN = 0V, RLOAD = 100, unless otherwise specified PARAMETER DESCRIPTION MIN TYP MAX UNITS BW(-3dB) -3dB Bandwidth (Gain =1) 150 MHz SR Slewrate 400 V/µs TSTL Settling time to 1% 15 ns GBWP Gain bandwidth product 200 MHz VREFBW(-3dB) VREF -3dB Bandwidth 130 MHz VREFSR VREF Slewrate 100 V/µsec dG Differential gain at 3.58MHz 0.2 % dθ Differential phase at 3.58MHz 0.2 ° 2 FN7049.1 February 11, 2005 EL2142 Pin Descriptions PIN NUMBER PIN NAME FUNCTION 1 VFB Feedback input 2 VIN Non-inverting input 3 VINB Inverting input 4 VREF Sets output voltage level to VREF when VIN=VINB 5 NC 6 VCC Positive supply voltage 7 VEE Negative supply voltage 8 VOUT Output voltage Typical Performance Curves IS vs Supply Voltage Frequency Response vs Resistor R1 (Gain = 4) VREF Frequency Response 3 Frequency Response (Gain = 1) CMRR vs Frequency Distortion vs Frequency (Gain = 3, RLOAD = 100Ω) VIN = 2VPK-PK FN7049.1 February 11, 2005 EL2142 Applications Information one, there is little to be gained from choosing resistor R1 value below 200Ω, for it would only result in increased power dissipation and potential signal distortion. Above 200Ω, the bandwidth response will develop some peaking (for a gain of one), but substantially higher R1 values may be used for higher voltage gains, such as up to 1kΩ at a gain of four before peaking will develop. Capacitance Considerations As with many high bandwidth amplifiers, the EL2142 prefers not to drive highly capacitive loads. It is best if the capacitance on VOUT is kept below 10pF if the user does not want gain peaking to develop. The VFB node forms a potential pole in the feedback loop, so capacitance should be minimized on this node for maximum bandwidth. Gain Equation VOUT = ((R2+R1)/R1) x (VIN-VINB+VREF) when R1 tied to GND VOUT = ((R2+R1)/R1) x (VIN-VINB) when R1 tied to VREF The amount of capacitance tolerated on any of these nodes in an actual application will also be dependent on the gain setting and the resistor values in the feedback network. Choice of Feedback Resistor For a gain of one, VOUT may be shorted back to VFB, but 100Ω-200Ω improves the bandwidth. For gains greater than Typical Applications Circuits 100Ω 50Ω VFB VIN EL2142 VOUT VINB 50Ω VREF FIGURE 1. TYPICAL TWISTED PAIR APPLICATION FIGURE 2. COAXIAL CABLE DRIVER PAIR APPLICATION 4 FN7049.1 February 11, 2005 EL2142 FIGURE 3. SINGLE SUPPLY RECEIVER R3 R1 R2 C1 50Ω Z0 = 100Ω VFB VIN EL2142 VOUT VINB 50Ω VREF FIGURE 4. COMPENSATED LINE RECEIVER FIGURE 5. TWO CHANNEL MULTIPLEXER 5 FN7049.1 February 11, 2005 EL2142 SOIC Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at <http://www.intersil.com/design/packages/index.asp> All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6 FN7049.1 February 11, 2005