DATASHEET

EL5221
®
Data Sheet
July 25, 2007
Dual 12MHz Rail-to-Rail Input-Output
Buffer
Features
• 12MHz -3dB bandwidth
The EL5221 is a dual, low power, high voltage rail-to-rail
input-output buffer. Operating on supplies ranging from 5V to
15V, while consuming only 500µA per channel, the EL5221
has a bandwidth of 12MHz -(-3dB). The EL5221 also
provides rail-to-rail input and output ability, giving the
maximum dynamic range at any supply voltage.
The EL5221 also features fast slewing and settling times, as
well as a high output drive capability of 30mA (sink and
source). These features make the EL5221 ideal for use as
voltage reference buffers in Thin Film Transistor Liquid
Crystal Displays (TFT-LCD). Other applications include
battery power, portable devices, and anywhere low power
consumption is important.
• Unity gain buffer
• Supply voltage = 4.5V to 16.5V
• Low supply current (per buffer) = 500µA
• High slew rate = 10V/µs
• Rail-to-rail operation
• Pb-Free plus anneal available (RoHS compliant)
Applications
• TFT-LCD drive circuits
• Electronics notebooks
The EL5221 is available in space-saving 6 Ld SOT-23 and
8 Ld MSOP packages and operates over a temperature
range of -40°C to +85°C.
• Electronics games
Ordering Information
• Portable instrumentation
PART
NUMBER
PART
MARKING
PACKAGE
PKG.
DWG. #
EL5221CW-T7*
M
6 Ld SOT-23
MDP0038
EL5221CW-T7A*
M
6 Ld SOT-23
MDP0038
EL5221CWZ-T7*
(Note)
BBEA
6 Ld SOT-23
(Pb-free)
MDP0038
EL5221CWZ-T7A* BBEA
(Note)
6 Ld SOT-23
(Pb-free)
MDP0038
EL5221CY
K
8 Ld MSOP
MDP0043
EL5221CY-T7*
K
8 Ld MSOP
MDP0043
EL5221CY-T13*
K
8 Ld MSOP
MDP0043
EL5221CYZ
(Note)
BAAAJ
8 Ld MSOP
(Pb-free)
MDP0043
EL5221CYZ-T7*
(Note)
BAAAJ
8 Ld MSOP
(Pb-free)
MDP0043
EL5221CYZ-T13*
(Note)
BAAAJ
8 Ld MSOP
(Pb-free)
MDP0043
• Personal communication devices
• Personal Digital Assistants (PDA)
• Wireless LANs
• Office automation
• Active filters
• ADC/DAC buffer
Pinouts
EL5221
(6 LD SOT-23)
TOP VIEW
VINA 1
6 VOUTA
VS- 2
5 VS+
VINB 3
*Please refer to TB347 for details on reel specifications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
4 VOUTB
EL5221
(8 LD MSOP)
TOP VIEW
VOUTA 1
NC 2
VINA 3
VS- 4
1
FN7187.2
8 VS+
7 VOUTB
6 NC
5 VINB
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2005, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5221
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS+ +0.5V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
ESD Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 10kΩ and CL = 10pF to 0V, TA = +25°C unless otherwise specified.
DESCRIPTION
CONDITION
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
12
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 0V
2
TCVOS
Average Offset Voltage Drift
(Note 1)
5
IB
Input Bias Current
VCM = 0V
2
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
1.35
pF
AV
Voltage Gain
-4.5V ≤ VOUT ≤ 4.5V
0.995
µV/°C
50
nA
1.005
V/V
-4.85
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = 5mA
ISC
Short Circuit Current
Short to GND
-4.92
4.85
4.92
V
±120
mA
80
dB
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS is moved from ±2.25V to ±7.75V
IS
Supply Current (Per Buffer)
No load
60
500
750
µA
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 2)
-4.0V ≤ VOUT ≤ 4.0V, 20% to 80%
tS
Settling to +0.1%
BW
CS
10
V/µs
VO = 2V step
500
ns
-3dB Bandwidth
RL = 10kΩ, CL = 10pF
12
MHz
Channel Separation
f = 5MHz
75
dB
2
7
FN7187.2
July 25, 2007
EL5221
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = 0V, RL = 10kΩ and CL = 10pF to 2.5V, TA = +25°C unless otherwise specified.
DESCRIPTION
CONDITION
MIN
(NOTE 3)
TYP
MAX
(NOTE 3)
UNIT
10
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 2.5V
2
TCVOS
Average Offset Voltage Drift
(Note 1)
5
IB
Input Bias Current
VCM = 2.5V
2
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
1.35
pF
AV
Voltage Gain
0.5 ≤ VOUT ≤ 4.5V
0.995
µV/°C
50
nA
1.005
V/V
150
mV
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = 5mA
ISC
Short Circuit Current
Short to GND
80
4.85
4.92
V
±120
mA
80
dB
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS is moved from 4.5V to 15.5V
IS
Supply Current (Per Buffer)
No Load
60
500
750
µA
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 2)
1V ≤ VOUT ≤4V, 20% to 80%
tS
Settling to +0.1%
BW
CS
10
V/µs
VO = 2V Step
500
ns
-3dB Bandwidth
RL = 10kΩ, CL = 10pF
12
MHz
Channel Separation
f = 5MHz
75
dB
3
7
FN7187.2
July 25, 2007
EL5221
Electrical Specifications
PARAMETER
VS+ = +15V, VS- = 0V, RL = 10kΩ and CL = 10pF to 7.5V, TA = +25°C unless otherwise specified.
DESCRIPTION
CONDITION
MIN
(NOTE 3)
TYP
MAX
(NOTE 3)
UNIT
14
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 7.5V
2
TCVOS
Average Offset Voltage Drift
(Note 1)
5
IB
Input Bias Current
VCM = 7.5V
2
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
1.35
pF
AV
Voltage Gain
0.5 ≤ VOUT ≤ 14.5V
0.995
µV/°C
50
nA
1.005
V/V
150
mV
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = 5mA
ISC
Short Circuit Current
Short to GND
80
14.85
14.92
V
±120
mA
80
dB
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS is moved from 4.5V to 15.5V
IS
Supply Current (Per Buffer)
No Load
60
500
750
µA
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 2)
1V ≤ VOUT ≤14V, 20% to 80%
tS
Settling to +0.1%
BW
CS
7
10
V/µs
VO = 2V Step
500
ns
-3dB Bandwidth
RL = 10kΩ, CL = 10pF
12
MHz
Channel Separation
f = 5MHz
75
dB
NOTES:
1. Measured over the operating temperature range.
2. Slew rate is measured on rising and falling edges.
3. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
4
FN7187.2
July 25, 2007
EL5221
Typical Performance Curves
Input Offset Voltage Distribution
Input Offset Voltage Drift
35
2000
VS=±5V
TA=25°C
VS=±5V
TA=25°C
30
Quantity (Buffers)
1200
800
400
20
15
10
5
19
17
15
13
11
9
7
1
8
10
6
4
2
0
-2
-4
-6
-8
-10
-12
12
Input Offset Voltage, TCVOS (µV/°C)
Input Offset Voltage (mV)
Input Offset Voltage vs Temperature
Input Bias Current vs Temperature
4
5
Input Bias Current (nA)
10
Input Offset Voltage (mV)
5
0
0
VS=±5V
0
-5
-10
-50
0
50
Temperature (°C)
100
2
VS=±5V
0
-2
-4
-50
150
0
50
100
150
Temperature (°C)
Output Low Voltage vs Temperature
Output High Voltage vs Temperature
-4.91
4.97
VS=±5V
IOUT=5mA
-4.92
Output Low Voltage (V)
Output High Voltage (V)
Typical
Production
Distribution
25
3
Quantity (Buffers)
1600
Typical
Production
Distribution
4.96
4.95
4.94
VS=±5V
IOUT=-5mA
-4.93
-4.94
-4.95
-4.96
4.93
-50
0
50
Temperature (°C)
5
100
150
-4.97
-50
0
50
Temperature (°C)
100
150
FN7187.2
July 25, 2007
EL5221
Typical Performance Curves
(Continued)
Slew Rate vs Temperature
Voltage Gain vs Temperature
13
1.001
12.5
VS=±5V
Slew Rate (V/µS)
Voltage Gain (V/V)
1.0005
1.0000
0.9995
VS=±5V
12
11.5
11
10.5
0.999
-50
0
50
Temperature (°C)
100
10
-50
150
Supply Current per Channel vs Temperature
150
Supply Current per Channel vs Supply Voltage
Supply Current (µA)
VS=±5V
0.45
0.4
-50
0
50
100
550
TA=25°C
450
350
250
150
5
0
Temperature (°C)
10
Supply Voltage (V)
20
15
Frequency Response for Various CL
Frequency Response for Various RL
20
5
10kΩ
0
Magnitude (Normalized) (dB)
Magnitude (Normalized) (dB)
100
650
0.5
-5
50
Temperature (°C)
0.55
Supply Current (mA)
0
1kΩ
560Ω
CL=10pF
VS=±5V
150Ω
-10
-15
100k
1M
10M
Frequency (Hz)
6
100M
10
RL=10kΩ
VS=±5V
12pF
0
50pF
-10
100pF
-20
1000pF
-30
100k
1M
10M
Frequency (Hz)
100M
FN7187.2
July 25, 2007
EL5221
Typical Performance Curves
(Continued)
Maximum Output Swing vs Frequency
Output Impedance vs Frequency
12
Maximum Output Swing (VP-P)
Output Impedance (Ω)
200
VS=±5V
TA=25°C
160
120
80
40
0
10k
100k
1M
Frequency (Hz)
10
8
4
2
0
10k
10M
PSRR vs Frequency
80
Voltage Noise (nV/√Hz)
PSRR (dB)
40
VS=±5V
TA=25°C
0
100
1k
10k
100k
Frequency (Hz)
1M
100
10
1
100
10M
Total Harmonic Distortion + Noise vs Frequency
-60
0.009
-80
X-Talk (dB)
THD+ N (%)
0.008
0.007
0.006
0.005
0.003
VS=±5V
RL=10kΩ
VIN=1VRMS
1k
10k
100k
1M
Frequency (Hz)
10M
100M
Channel Separation vs Frequency Response
0.010
0.004
10M
Input Voltage Noise Spectral Density vs Frequency
PSRR-
20
100k
1M
Frequency (Hz)
600
PSRR+
60
VS=±5V
TA=25°C
RL=10kΩ
CL=12pF
Distortion <1%
6
-100
Dual measured Channel A to B
Quad measured Channel A to D or B to C
Other combinations yield improved
rejection.
VS=±5V
RL=10kΩ
VIN=220mVRMS
-120
0.002
0.001
1k
10k
Frequency (Hz)
7
100k
-140
1k
10k
100k
1M
6M
Frequency (Hz)
FN7187.2
July 25, 2007
EL5221
Typical Performance Curves
(Continued)
Small-Signal Overshoot vs Load Capacitance
Settling Time vs Step Size
100
5
3
2
Step Size (V)
Overshoot (%)
60
VS=±5V
RL=10kΩ
CL=12pF
TA=25°C
4
VS=±5V
RL=10kΩ
VIN=±50mV
TA=25°C
80
40
0.1%
1
0
-1
-2
0.1%
-3
20
-4
0
10
-5
100
1000
0
200
Load Capacitance (pF)
Large Signal Transient Response
1V
1µS
400
Settling Time (nS)
600
800
Small Signal Transient Response
50mV
200ns
VS=±5V
TA=25°C
RL=10kΩ
CL=12pF
VS=±5V
TA=25°C
RL=10kΩ
CL=12pF
8
FN7187.2
July 25, 2007
EL5221
Pin Descriptions
6 LD SOT-23 8 LD MSOP PIN NAME
1
3
VINA
FUNCTION
EQUIVALENT CIRCUIT
Buffer A Input
VS+
VSCircuit 1
2
4
VS-
3
5
VINB
4
7
VOUTB
Negative Supply Voltage
Buffer B Input
(Reference Circuit 1)
Buffer B Output
VS+
VSGND
Circuit 2
VS+
6
1
VOUTA
Positive Supply Voltage
Buffer A Output
Applications Information
Product Description
(Reference Circuit 2)
.
5V
The EL5221 unity gain buffer is fabricated using a high
voltage CMOS process. It exhibits rail-to-rail input and
output capability and has low power consumption (500µA
per buffer). These features make the EL5221 ideal for a wide
range of general-purpose applications. When driving a load
of 10kΩ and 12pF, the EL5221 has a -3dB bandwidth of
12MHz and exhibits 10V/µs slew rate.
Operating Voltage, Input, and Output
The EL5221 is specified with a single nominal supply voltage
from 5V to 15V or a split supply with its total range from 5V
to 15V. Correct operation is guaranteed for a supply range of
4.5V to 16.5V. Most EL5221 specifications are stable over
both the full supply range and operating temperatures of
-40°C to +85°C. Parameter variations with operating voltage
and/or temperature are shown in the typical performance
curves.
The output swings of the EL5221 typically extend to within
80mV of positive and negative supply rails with load currents
of 5mA. Decreasing load currents will extend the output
voltage range even closer to the supply rails. Figure 1 shows
the input and output waveforms for the device. Operation is
from ±5V supply with a 10kΩ load connected to GND. The
input is a 10VP-P sinusoid. The output voltage is
approximately 9.985VP-P.
9
10µS
VS=±5V
TA=25°C
VIN=10VP-P
5V
Input
8
Output
5
FIGURE 1. OPERATION WITH RAIL-TO-RAIL INPUT AND
OUTPUT
Short Circuit Current Limit
The EL5221 will limit the short circuit current to ±120mA if
the output is directly shorted to the positive or the negative
supply. If an output is shorted indefinitely, the power
dissipation could easily increase such that the device may
be damaged. Maximum reliability is maintained if the output
continuous current never exceeds ±30mA. This limit is set by
the design of the internal metal interconnects.
Output Phase Reversal
The EL5221 is immune to phase reversal as long as the
input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 2
shows a photo of the output of the device with the input
voltage driven beyond the supply rails. Although the device's
output will not change phase, the input's overvoltage should
be avoided. If an input voltage exceeds supply voltage by
FN7187.2
July 25, 2007
EL5221
more than 0.6V, electrostatic protection diodes placed in the
input stage of the device begin to conduct and overvoltage
damage could occur.
where:
i = 1 to 2 for dual buffer
VS = Total supply voltage
1V
10µS
ISMAX = Maximum supply current per channel
VOUTi = Maximum output voltage of the application
ILOADi = Load current
1V
FIGURE 2. OPERATION WITH BEYOND-THE-RAILS INPUT
Power Dissipation
With the high-output drive capability of the EL5221 buffer, it
is possible to exceed the +125°C “absolute-maximum
junction temperature” under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for the application to determine if load
conditions need to be modified for the buffer to remain in the
safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
T JMAX - T AMAX
P DMAX = --------------------------------------------Θ JA
(EQ. 1)
If we set the two PDMAX equations equal to each other, we
can solve for RLOADi to avoid device overheat. Figure 3 and
Figure 4 provide a convenient way to see if the device will
overheat. The maximum safe power dissipation can be
found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
simple matter to see if PDMAX exceeds the device's power
derating curves. To ensure proper operation, it is important
to observe the recommended derating curves shown in
Figure 3 and Figure 4.
Package Mounted on a JEDEC JESD51-7 High
Effective Thermal Conductivity Test Board
1
870mW
MAX TJ=125°C
0.8
Power Dissipation (W)
VS=±2.5V
TA=25°C
VIN=6VP-P
M
0.6
SO
P8
435mW
0.4
SO
T2
3-6
0.2
11
5°
C
/W
23
0°C
/W
0
where:
0
25
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
50
75 85 100
Ambient Temperature (°C)
125
150
FIGURE 3. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
ΘJA = Thermal resistance of the Package
PDMAX = Maximum power dissipation in the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
(EQ. 2)
when sourcing, and:
P DMAX = Σi [ V S × I SMAX + ( V OUT i - V S - ) × I LOAD i ]
Package Mounted on a JEDEC JESD51-3 Low
Effective Thermal Conductivity Test Board
MAX TJ=125°C
486mW
0.5
Power Dissipation (W)
P DMAX = Σi [ V S × I SMAX + ( V S + - V OUT i ) × I LOAD i ]
0.6
391mW
0.4
M
SO
P8
SO
T2
36
0.3
0.2
20
6°
C/
W
25
6°
C/
W
0.1
(EQ. 3)
0
0
25
50
75 85 100
125
150
Ambient Temperature (°C)
when sinking.
FIGURE 4. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
10
FN7187.2
July 25, 2007
EL5221
Unused Buffers
It is recommended that any unused buffer have the input tied
to the ground plane.
Driving Capacitive Loads
The EL5221 can drive a wide range of capacitive loads. As
load capacitance increases, however, the -3dB bandwidth of
the device will decrease and the peaking increase. The
buffers drive 10pF loads in parallel with 10kΩ with just 1.5dB
of peaking, and 100pF with 6.4dB of peaking. If less peaking
is desired in these applications, a small series resistor
(usually between 5Ω and 50Ω) can be placed in series with
the output. However, this will obviously reduce the gain
slightly. Another method of reducing peaking is to add a
"snubber" circuit at the output. A snubber is a shunt load
consisting of a resistor in series with a capacitor. Values of
150Ω and 10nF are typical. The advantage of a snubber is
that it does not draw any DC load current or reduce the gain
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5221 can provide gain at high frequency. As with any
high frequency device, good printed circuit board layout is
necessary for optimum performance. Ground plane
construction is highly recommended, lead lengths should be
as short as possible, and the power supply pins must be well
bypassed to reduce the risk of oscillation. For normal single
supply operation, where the VS- pin is connected to ground,
a 0.1µF ceramic capacitor should be placed from VS+ to pin
to VS- pin. A 4.7µF tantalum capacitor should then be
connected in parallel, placed in the region of the buffer. One
4.7µF capacitor may be used for multiple devices. This same
capacitor combination should be placed at each supply pin
to ground if split supplies are to be used.
11
FN7187.2
July 25, 2007
EL5221
SOT-23 Package Family
MDP0038
e1
D
SOT-23 PACKAGE FAMILY
A
MILLIMETERS
6
N
SYMBOL
4
E1
2
E
3
0.15 C D
1
2X
2
3
0.20 C
5
2X
e
0.20 M C A-B D
B
b
NX
0.15 C A-B
1
3
SOT23-5
SOT23-6
A
1.45
1.45
MAX
A1
0.10
0.10
±0.05
A2
1.14
1.14
±0.15
b
0.40
0.40
±0.05
c
0.14
0.14
±0.06
D
2.90
2.90
Basic
E
2.80
2.80
Basic
E1
1.60
1.60
Basic
e
0.95
0.95
Basic
e1
1.90
1.90
Basic
L
0.45
0.45
±0.10
L1
0.60
0.60
Reference
N
5
6
Reference
D
2X
TOLERANCE
Rev. F 2/07
NOTES:
C
A2
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
SEATING
PLANE
A1
0.10 C
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
NX
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
(L1)
6. SOT23-5 version has no center lead (shown as a dashed line).
H
A
GAUGE
PLANE
c
L
12
0.25
0° +3°
-0°
FN7187.2
July 25, 2007
EL5221
Mini SO Package Family (MSOP)
0.25 M C A B
D
MINI SO PACKAGE FAMILY
(N/2)+1
N
E
MDP0043
A
E1
MILLIMETERS
PIN #1
I.D.
1
B
(N/2)
e
H
C
SEATING
PLANE
0.10 C
N LEADS
SYMBOL
MSOP8
MSOP10
TOLERANCE
NOTES
A
1.10
1.10
Max.
-
A1
0.10
0.10
±0.05
-
A2
0.86
0.86
±0.09
-
b
0.33
0.23
+0.07/-0.08
-
c
0.18
0.18
±0.05
-
D
3.00
3.00
±0.10
1, 3
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
-
0.08 M C A B
b
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
L
A1
0.25
3° ±3°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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13
FN7187.2
July 25, 2007
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