LTM4676 - Dual 13A or Single 26A μModule Regulator with Digital Power System Management

LTM4676
Dual 13A or Single 26A
µModule Regulator with Digital
Power System Management
Description
Features
Dual, Fast, Analog Loops with Digital Interface
for
Control and Monitoring
n Wide Input Voltage Range: 4.5V to 26.5V
n Output Voltage Range: 0.5V to 5.4V (4V on V
OUT0)
n±1% Maximum DC Output Error Over Temperature
n±2.5% Current Readback Accuracy at 10A Load
n400kHz PMBus-Compliant I2C Serial Interface
n Integrated 16-Bit ∆Σ ADC
n Constant Frequency Current Mode Control
n Parallel and Current Share Multiple Modules
n16 Slave Addresses; Rail/Global Addressing
n16mm × 16mm × 5.01mm BGA Package
Readable Data:
n Input and Output Voltages, Currents, and Temperatures
n Running Peak Values, Uptime, Faults and Warnings
n Onboard EEPROM Fault Log Record
Writable Data and Configurable Parameters:
n Output Voltage, Voltage Sequencing and Margining
n Digital Soft-Start/Stop Ramp
n OV/UV/OT, UVLO, Frequency and Phasing
The LTM®4676 is a dual 13A or single 26A step-down
µModule® (micromodule) DC/DC regulator featuring remote configurability and telemetry-monitoring of power
management parameters over PMBus— an open standard
I2C-based digital interface protocol . The LTM4676 is
comprised of fast analog control loops, precision mixedsignal circuitry, EEPROM, power MOSFETs, inductors and
supporting components.
n
The LTM4676’s 2-wire serial interface allows outputs to be
margined, tuned and ramped up and down at programmable
slew rates with sequencing delay times. Input and output
currents and voltages, output power, temperatures, uptime
and peak values are readable. Custom configuration of
the EEPROM contents is not required. At start-up, output
voltages, switching frequency, and channel phase angle
assignments can be set by pin-strapping resistors. The
LTpowerPlay™ GUI and DC1613 USB-to-PMBus converter
and demo kits are available.
The LTM4676 is offered in a 16mm × 16mm × 5.01mm
BGA package available with SnPb or RoHS compliant
terminal finish.
Applications
L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule, Burst Mode and PolyPhase
are registered trademarks and LTpowerPlay is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 7420359,
8163643. Licensed under U.S. Patent 7000125 and other related patents worldwide.
System Optimization, Characterization and Data Mining in Prototype, Production and Field Environments
n Telecom, Datacom, and Storage Systems
n
Click to view associated Video Design Idea.
Typical Application
Using PMBus and LTpowerPlay to Monitor Telemetry and Margin
VOUT0/VOUT1 During Load Pattern Tests. 10Hz Polling Rate. 12VIN
Dual 13A µModule Regulator with Digital
Interface for Control and Monitoring*
VOSNS0–
LTM4676
GPIO0
GPIO1
WP
VOUT1
LOAD1
GND
SGND
SCL
SDA
ALERT
4676 TA01a
*FOR COMPLETE CIRCUIT, SEE FIGURE 44
VOUT1,
ADJUSTABLE
UP TO 13A
VOSNS1
SYNC
SHARE_CLK
100µF
×7
2C/SMBus I/F WITH
I
PMBus COMMAND SET
TO/FROM IPMI OR OTHER
BOARD MANAGEMENT
CONTROLLER
0.9
1.7
0.8
0
3
6
TIME (SEC)
9
10
5
5
0
3
6
TIME (SEC)
0.5
0.8
0
1.6
12
10
0
1.6
0
3
4677 TA01b
Output Current Readback, Varying Load Pattern
15
15
9
0
12
4676 TA01c
2.4
1.0
IIN0 (A)
VOUT0 (V)
100µF
×7
CHANNEL 0 TEMP (°C)
REGISTER WRITE
PROTECTION
RUN0
RUN1
LOAD0
IOUT1 (A)
PWM CLOCK AND
TIME-BASE
SYNCHRONIZATION
SVIN
1.8
Input Current Readback
60
6
TIME (SEC)
9
0
12
4676 TA01d
Power Stage Temperature Readback
60
57
57
54
54
51
0
3
6
TIME (SEC)
9
51
12
CHANNEL 1 TEMP (°C)
FAULT INTERRUPTS,
POWER SEQUENCING
VOSNS0+
1.0
IOUT0 (A)
ON/OFF CONTROL
VOUT0,
ADJUSTABLE
UP TO 13A
VOUT0
1.5
IIN1 (A)
22µF
×3
VIN0
VIN1
VOUT1 (V)
VIN
5.75V TO 26.5V
Output Voltage Readback, VOUT Margined 7.5% Low
1.1
1.9
4676 TA01e
4676fd
For more information www.linear.com/LTM4676
1
LTM4676
Table of Contents
Features...................................................... 1
Applications................................................. 1
Typical Application ......................................... 1
Description.................................................. 1
Absolute Maximum Ratings............................... 3
Order Information........................................... 3
Pin Configuration........................................... 3
Electrical Characteristics.................................. 4
Typical Performance Characteristics................... 11
Pin Functions............................................... 14
Simplified Block Diagram................................ 19
Decoupling Requirements................................ 19
Functional Diagram....................................... 20
Test Circuits................................................ 21
Operation................................................... 22
Power Module Introduction.....................................22
Power Module Configurability and
Readback Data......................................................... 24
Time-Averaged and Peak Readback Data.................26
Power Module Overview..........................................29
EEPROM..................................................................33
Additional Information.............................................33
Applications Information................................. 34
LTM4676 Control IC Differences from LTC3880......34
VIN to VOUT Step-Down Ratios.................................45
Input Capacitors......................................................45
Output Capacitors....................................................45
Light Load Current Operation..................................45
Switching Frequency and Phase..............................46
Minimum On-Time Considerations..........................48
Variable Delay Time, Soft-Start and Output Voltage
Ramping..................................................................48
Digital Servo Mode.................................................. 49
Soft Off (Sequenced Off).........................................50
Undervoltage Lockout..............................................50
Fault Conditions....................................................... 51
Open-Drain Pins...................................................... 51
Phase-Locked Loop and Frequency
Synchronization....................................................... 52
RCONFIG Pin-Straps (External Resistor
Configuration Pins).................................................. 52
Voltage Selection..................................................... 52
Connecting the USB to the I2C/SMBus/PMBus
Controller to the LTM4676 In System......................53
LTpowerPlay: An Interactive GUI for Digital Power
System Management...............................................54
PMBus Communication and Command
Processing...............................................................56
Thermal Considerations and
Output Current Derating..........................................58
EMI Performance.....................................................66
Safety Considerations.............................................. 67
Layout Checklist/Example....................................... 67
Typical Applications....................................... 68
Package Description...................................... 74
Package Photograph...................................... 75
Package Description...................................... 76
Revision History........................................... 77
Typical Application........................................ 78
Design Resources......................................... 78
Related Parts............................................... 78
The LTC3880 data sheet is an essential reference document for this product.
To obtain it go to:
www.linear.com/LTC3880
2
4676fd
For more information www.linear.com/LTM4676
LTM4676
Absolute Maximum Ratings
Pin Configuration
(Note 1)
Terminal Voltages:
VINn (Note 4), SVIN...................................... –0.3V to 28V
VOUTn............................................................ –0.3V to 6V
VOSNS0+, VORB0+...................................... –0.3V to 4.25V
VOSNS1, VORB1, INTVCC, ISNSna+, ISNSnb+,
ISNSn a–, ISNSn b –............................................ –0.3V to 6V
RUNn, SDA, SCL, ALERT............................ –0.3V to 5.5V
FSWPHCFG, VOUTnCFG, V TRIMnCFG, ASEL... –0.3V to 2.75V
VDD33, GPIOn, SYNC, SHARE_CLK, WP, TSNSn a,
COMPna, COMPnb, VOSNS0 –, VORB0 –.......... –0.3V to 3.6V
SGND......................................................... –0.3V to 0.3V
Terminal Currents
INTVCC Peak Output Current.................................100mA
VDD25....................................................–1.5mA to 1.5mA
TSNSnb.....................................................–1mA to 10mA
Temperatures
Internal Operating Temperature Range
(Notes 2, 3)............................................. –40°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Package Body Temperature During Reflow... 245°C
1
2
3
4
5
TOP VIEW
6
7
8
9
10
11
12
A
B
C
GND
VOUT0
VIN0
GND
D
E
F
GND
G
GND
H
J
K
L
VOUT1
GND
VIN1
GND
M
BGA PACKAGE
144-LEAD (16mm × 16mm × 5.01mm)
TJMAX = 125°C, θJCtop = 8.8°C/W, θJCbottom = 0.8°C/W, θJB = 1.3°C/W, θJA = 10.3°C/W
θ VALUES DETERMINED PER JESD51-12
WEIGHT = 3.3 GRAMS
Order Information
PART NUMBER
PAD OR BALL FINISH
PART MARKING*
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(See Note 2)
LTM4676EY#PBF
SAC305 (RoHS)
LTM4676Y
e1
BGA
4
–40°C to 125°C
LTM4676IY#PBF
SAC305 (RoHS)
LTM4676Y
e1
BGA
4
–40°C to 125°C
LTM4676IY
SnPb (63/37)
LTM4676Y
e0
BGA
4
–40°C to 125°C
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• Terminal Finish Part Marking:
www.linear.com/leadfree
• LGA and BGA Package and Tray Drawings:
www.linear.com/packaging
4676fd
For more information www.linear.com/LTM4676
3
LTM4676
Electrical Characteristics
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V,
FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
VIN
PARAMETER
Input DC Voltage
CONDITIONS
Test Circuit 1
Test Circuit 2; VIN_OFF < VIN_ON = 4.25V
l
l
MIN
5.75
4.5
VOUT0
Range of Output Voltage
Regulation, Channel 0
VOUT0 Differentially Sensed on VOSNS0+/VOSNS0– Pin-Pair;
Commanded by Serial Bus or with Resistors Present at Start-Up on
VOUT0CFG and/or VTRIM0CFG
VOUT1
VOUTn(DC)
l
0.5
4.0
V
Range of Output Voltage
Regulation, Channel 1
VOUT1 Differentially Sensed on VOSNS1/SGND Pin-Pair; Commanded l
by Serial Bus or with Resistors Present at Start-Up on VOUT1CFG and/
or VTRIM1CFG
0.5
5.4
V
Output Voltage, Total
Variation with Line and
Load
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
VOUTn Commanded to 1.000V, VOUTn Low Range
(MFR_PWM_CONFIG[6-n] = 1b), FREQUENCY_SWITCH = 250kHz
(Note 5)
1.010
1.015
V
V
l
0.990
0.985
TYP
1.000
1.000
MAX
26.5
5.75
UNITS
V
V
Input Specifications
IINRUSH(VIN)
Input Inrush Current at
Test Circuit 1, VOUTn =1V, VIN = 12V; No Load Besides Capacitors;
Start-Up
TON_RISEn = 3ms
Input Supply Bias Current Forced Continuous Mode, MFR_PWM_MODEn[1:0] = 10b
IQ(SVIN)
RUNn = 5V, RUN1-n = 0V
Shutdown, RUN0 = RUN1 = 0V
Input Supply Current in
Burst Mode Operation, MFR_PWM_MODEn[1:0] = 01b,
IS(VINn,BURST)
Burst Mode® Operation
IOUTn = 100mA
Input Supply Current in
Pulse-Skipping Mode, MFR_PWM_MODEn[1:0] = 00b,
IS(VINn,PSM)
Pulse-Skipping Mode
IOUTn = 100mA
Operation
Input Supply Current in
Forced Continuous Mode, MFR_PWM_MODEn[1:0] = 10b
IS(VINn,FCM)
Forced-Continuous Mode
IOUTn = 100mA
Operation
IOUTn = 13A
Shutdown, RUNn = 0V
IS(VINn,SHUTDOWN) Input Supply Current in
Shutdown
Output Specifications
IOUTn
Output Continuous
Current Range
∆VOUTn(LINE)
VOUTn(AC)
Line Regulation Accuracy Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
l
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
SVIN and VINn Electrically Shorted Together and INTVCC Open Circuit;
IOUTn = 0A, 5.75V ≤ VIN ≤ 26.5V, VOUT Low Range
(MFR_PWM_CONFIG[6-n] = 1b) FREQUENCY_SWITCH = 250kHz
(Referenced to 12VIN) (Note 5)
Load Regulation
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
l
Accuracy
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
0A ≤ IOUTn ≤ 13A, VOUT Low Range, (MFR_PWM_CONFIG[6-n] = 1b)
FREQUENCY_SWITCH = 250kHz (Note 5)
Output Voltage Ripple
fS (Each Channel)
∆VOUTn(START)
VOUTn Ripple Frequency
Turn-On Overshoot
FREQUENCY_SWITCH Set to 500kHz (0xFBE8)
TON_RISEn = 3ms (Note 12)
l
tSTART
Turn-On Start-Up Time
Time from VIN Toggling from 0V to 12V to Rising Edge of GPIOn.
TON_DELAYn = 0ms, TON_RISEn = 3ms,
MFR_GPIO_PROPAGATEn = 0x0100,
MFR_GPIO_RESPONSEn = 0x0000
l
VOUTn
∆VOUTn(LOAD)
VOUTn
4
(Note 6)
400
mA
40
20
15
mA
mA
mA
20
mA
40
1.37
50
mA
A
µA
0
13
0.03
0.03
±0.2
%
%/V
0.03
0.2
0.5
%
%
10
462.5
A
mVP-P
500
8
537.5
kHz
mV
153
170
ms
4676fd
For more information www.linear.com/LTM4676
LTM4676
Electrical Characteristics
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V,
FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
tDELAY(0ms)
PARAMETER
Turn-On Delay Time
∆VOUTn(LS)
Peak Output Voltage
Deviation for Dynamic
Load Step
Settling Time for
Dynamic Load Step
Output Current Limit,
Peak
Output Current Limit,
Time Averaged
tSETTLE
IOUTn(OCL_PK)
IOUTn(OCL_AVG)
Control Section
VFBCM0
VFBCM1
VOUT0-RNG0
VOUT0-RNG1
VOUT1-RNG0
VOUT1-RNG1
RVSENSE0+
Channel 0 Feedback Input
Common Mode Range
Channel 1 Feedback Input
Common Mode Range
Channel 0 Full-Scale
Command Voltage,
Range 0
Channel 0 Full-Scale
Command Voltage,
Range 1
Channel 1 Full-Scale
Command Voltage,
Range 0
Channel 1 Full-Scale
Command Voltage,
Range 1
CONDITIONS
Time from First Rising Edge of RUNn to Rising Edge of GPIOn.
TON_DELAYn = 0ms, TON_RISEn = 3ms,
MFR_GPIO_PROPAGATEn = 0x0100,
MFR_GPIO_RESPONSEn = 0x0000.
VIN Having Been Established for at Least 170ms
Load: 0A to 6.5A and 6.5A to 0A at 6.5A/µs, Figure 44 Circuit,
VOUTn = 1V, VIN = 12V (Note 12)
l
MIN
2.75
Load: 0A to 6.5A and 6.5A to 0A at 6.5A/µs, Figure 44 Circuit,
VOUTn = 1V, VIN = 12V (Note 12)
Cycle-by-Cycle Inductor Peak Current Limit Inception
Time-Averaged Output Inductor Current Limit Inception Threshold,
Commanded by IOUT_OC_FAULT_LIMITn (Note 12)
VOSNS0– Valid Input Range (Referred to SGND)
VOSNS0+ Valid Input Range (Referred to SGND)
SGND Valid Input Range (Referred to GND)
VOSNS1 Valid Input Range (Referred to SGND)
(Notes 7, 15)
VOUT0 Commanded to 4.095V, MFR_PWM_CONFIG[6] = 0b
Resolution
LSB Step Size
(Notes 7, 15)
VOUT0 Commanded to 2.750V, MFR_PWM_CONFIG[6] = 1b
Resolution
LSB Step Size
(Notes 7, 15)
VOUT1 Commanded to 5.500V, MFR_PWM_CONFIG[5] = 0b
Resolution
LSB Step Size
(Notes 7, 15)
VOUT1 Commanded to 2.750V, MFR_PWM_CONFIG[5] = 1b
Resolution
LSB Step Size
0.05V ≤ VVOSNS0+ – VSGND ≤ 4.1V
TYP
3.1
MAX
3.5
UNITS
ms
50
mV
35
µs
22.5
A
15.6A; See IO-RB-ACC
Specification (Output Current
Readback Accuracy)
l
l
–0.1
l
l
–0.3
4.015
2.711
5.422
2.711
12
1.375
12
0.6875
12
1.375
12
0.6875
41
0.3
4.25
0.3
5.5
V
V
V
V
4.176
V
Bits
mV
2.788
V
Bits
mV
5.576
V
Bits
mV
2.788
V
Bits
mV
kΩ
VOSNS0+ Impedance to
SGND
VOSNS1 Impedance to
0.05V ≤ VVOSNS1 – VSGND ≤ 5.5V
37
kΩ
RVSENSE1
SGND
Minimum On-Time
(Note 8 )
90
ns
tON(MIN)
Analog OV/UV (Overvoltage/Undervoltage) Output Voltage Supervisor Comparators (VOUT_OV/UV_FAULT_LIMIT and VOUT_OV/UV_WARN_LIMIT Monitors)
NOV/UV_COMP
Resolution, Output
(Note 15)
8
Bits
Voltage Supervisors,
Channels 0 and 1
Output Voltage
(Note 15)
V0OU-RNG
Comparator Threshold
High Range Scale, MFR_PWM_CONFIG[6] = 0b
1
4.095
V
Detection Range,
0.5
2.7
V
Low Range Scale, MFR_PWM_CONFIG[6] = 1b
Channel 0
4676fd
For more information www.linear.com/LTM4676
5
LTM4676
Electrical Characteristics
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V,
FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
V0OU-STP
V0OU-ACC
V1OU-RNG
V1OU-STP
V1OU-ACC
tPROP-OV
PARAMETER
Output Voltage
Comparator Threshold
Programming LSB Step
Size, Channel 0
Output Voltage
Comparator Threshold
Accuracy, Channel 0
Output Voltage
Comparator Threshold
Detection Range,
Channel 1
Output Voltage
Comparator Threshold
Programming LSB Step
Size, Channel 1
Output Voltage
Comparator Threshold
Accuracy, Channel 1
CONDITIONS
(Note 15)
High Range Scale, MFR_PWM_CONFIG[6] = 0b
Low Range Scale, MFR_PWM_CONFIG[6] = 1b
(See Note 14)
2V ≤ VVOSNS0+ – VVOSNS0– ≤ 4.095V, MFR_PWM_CONFIG[6] = 0b
1V ≤ VVOSNS0+ – VVOSNS0– ≤ 2.7V, MFR_PWM_CONFIG[6] = 1b
0.5V ≤ VVOSNS0+ – VVOSNS0– < 1V, MFR_PWM_CONFIG[6] = 1b
(Note 15)
High Range Scale, MFR_PWM_CONFIG[5] = 0b
Low Range Scale, MFR_PWM_CONFIG[5] = 1b
(See Note 14)
2V ≤ VVOSNS1 – VSGND ≤ 5.5V, MFR_PWM_CONFIG[5] = 0b
1.5V ≤ VVOSNS1 – VSGND ≤ 2.7V, MFR_PWM_CONFIG[5] = 1b
0.5V ≤ VVOSNS1 – VSGND < 1.5V, MFR_PWM_CONFIG[5] = 1b
Overdrive to 10% Above Programmed Threshold
TYP
MAX
22
11
l
l
l
1
0.5
(Note 15)
High Range Scale, MFR_PWM_CONFIG[5] = 0b
Low Range Scale, MFR_PWM_CONFIG[5] = 1b
Output OV Comparator
Response Times,
Channels 0 and 1
Output UV Comparator
Underdrive to 10% Below Programmed Threshold
tPROP-UV
Response Times,
Channels 0 and 1
Analog OV/UV SVIN Input Voltage Supervisor Comparators (Threshold Detectors for VIN_ON and VIN_OFF)
NSVIN-OV/UV-COMP SVIN OV/UV Comparator (Note 15)
Threshold-Programming
Resolution
SVIN OV/UV Comparator
SVIN-OU-RANGE
Threshold-Programming
Range
SVIN OV/UV Comparator (Note 15)
SVIN-OU-STP
Threshold-Programming
LSB Step Size
SVIN OV/UV Comparator 9V < SVIN ≤ 20V
SVIN-OU-ACC
Threshold Accuracy
4.5V ≤ SVIN ≤ 9V
tPROP-SVIN-HIGH-VIN SVIN OV/UV Comparator Test Circuit 1, and:
Response Time, High VIN
VIN_ON = 9V; SVIN Driven from 8.775V to 9.225V
Operating Configuration
VIN_OFF = 9V; SVIN Driven from 9.225V to 8.775V
tPROP-SVIN-LOW-VIN SVIN OV/UV Comparator Test Circuit 2, and:
Response Time, Low VIN
VIN_ON = 4.5V; SVIN Driven from 4.225V to 4.725V
Operating Configuration
VIN_OFF = 4.5V; SVIN Driven from 4.725V to 4.225V
Channels 0 and 1 Output Voltage Readback (READ_VOUTn)
Output Voltage Readback (Note 15)
NVO-RB
Resolution and LSB Step
Size
VO-F/S
Output Voltage Full-Scale VRUNn = 0V (Notes 7, 15)
Digitizable Range
6
MIN
mV
mV
±2
±2
±20
%
%
mV
5.5
2.7
V
V
22
11
l
l
l
mV
mV
±2
±2
±30
35
%
%
mV
µs
50
µs
8
l
4.5
UNITS
Bits
20
82
V
mV
l
l
±2.5
±225
%
mV
l
l
35
35
µs
µs
l
l
35
35
µs
µs
16
244
8
Bits
µV
V
4676fd
For more information www.linear.com/LTM4676
LTM4676
Electrical Characteristics
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V,
FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
VO-RB-ACC
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
l
Output Voltage Readback Channel 0: 0.6V ≤ VVOSNS0+ – VVOSNS0– ≤ 4V
Within ±1% of Reading
l
Accuracy
Channel 1: 0.6V ≤ VVOSNS1 – VSGND ≤ 5.4V
Within ±1% of Reading
tCONVERT-VO-RB
Output Voltage Readback (Notes 9, 15)
100
ms
Update Rate
Input Voltage (SVIN) Readback (READ_VIN)
Input Voltage Readback (Notes 10, 15)
10
Bits
NSVIN-RB
Resolution and LSB Step
15.625
mV
Size
Input Voltage Full-Scale (Notes 11, 15)
38.91
V
SVIN-F/S
Digitizable Range
l
Input Voltage Readback READ_VIN, 4.5V ≤ SVIN ≤ 26.5V
Within ±2% of Reading
SVIN-RB-ACC
Accuracy
Input Voltage Readback (Notes 9, 15)
100
ms
tCONVERT-SVIN-RB
Update Rate
Channels 0 and 1 Output Current (READ_IOUTn), Duty Cycle (READ_DUTY_CYCLEn), and Computed Input Current (MFR_READ_IINn) Readback
Output Current Readback (Notes 10, 12)
10
Bits
NIO-RB
Resolution and LSB Step
15.6
mA
Size
Output Current Full-Scale (Note 12)
±40
A
IO-F/S, II-F/S
Digitizable Range and
Input Current Range of
Calculation
l
IO-RB-ACC
Output Current, Readback READ_IOUTn, Channels 0 and 1, 0 ≤ IOUTn ≤ 10A,
Within 250mA of Reading
Accuracy
Forced-Continuous Mode, MFR_PWM_MODEn[1:0] = 10b
Full Load Output Current IOUTn = 13A (Note 12). See Histograms in Typical Performance
13.1
A
IO-RB(13A)
Readback
Characteristics
Computed Input Current, (Notes 10, 12)
10
Bits
NII-RB
Readback Resolution and
1.95
mA
LSB Step Size
l
Computed Input Current, MFR_READ_IINn, Channels 0 and 1, 0 ≤ IOUTn ≤ 10A,
Within 150mA of Reading
II-RB-ACC
Readback Accuracy,
Forced-Continuous Mode, MFR_PWM_MODEn[1:0] = 10b,
Neglecting ISVIN
MFR_IIN_OFFSETn = 0mA
tCONVERT-IO-RB
Output Current Readback (Notes 9, 15)
100
ms
Update Rate
Computed Input Current, (Notes 9, 15)
100
ms
tCONVERT-II-RB
Readback Update Rate
Resolution, Duty Cycle
(Notes 10, 15)
10
Bits
NDUTY-RB
Readback
Duty Cycle TUE
READ_DUTY_CYCLEn, 16.3% Duty Cycle (Note 15)
±3
%
DRB-ACC
(Notes 9, 15)
100
ms
tCONVERT-DUTY-RB Duty Cycle Readback
Update Rate
Temperature Readback for Channel 0, Channel 1, and Controller (Respectively: READ_TEMPERATURE_10, READ_TEMPERATURE_11,
and READ_TEMPERATURE_2)
Temperature Readback
Channel 0, Channel 1, and Controller (Note 15)
0.0625
°C
TRES-RB
Resolution
l
Channels 0 and 1, PWM Inactive, RUNn = 0V,
Within ±3°C of Reading
TRB-CH-ACC(72mV) Channel Temperature
TUE, Switching Action Off ∆VTSNSna = 72mV
Channel Temperature
READ_TEMPERATURE_1n, Channels 0 and 1,
Within ±3°C of Reading
TRB-CH-ACC(ON)
TUE, Switching Action On PWM Active, RUNn = 5V (Note 12)
4676fd
For more information www.linear.com/LTM4676
7
LTM4676
Electrical Characteristics
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V,
FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
TRB-CTRL-ACC(ON)
tCONVERT-TEMP-RB
PARAMETER
Control IC Die
Temperature TUE,
Switching Action On
Temperature Readback
Update Rate
INTVCC Regulator
Internal VCC Voltage No
VINTVCC
Load
∆VINTVCC(LOAD)
INTVCC Load Regulation
VINTVCC
VDD33 Regulator
VVDD33
ILIM(VDD33)
VVDD33_OV
VVDD33_UV
Internal VDD33 Voltage
VDD33 Current Limit
VDD33 Overvoltage
Threshold
VDD33 Undervoltage
Threshold
VDD25 Regulator
Internal VDD25 Voltage
VVDD25
VDD25 Current Limit
ILIM(VDD25)
Oscillator and Phase-Locked Loop (PLL)
Oscillator Frequency
fOSC
Accuracy
PLL SYNC Capture Range
fSYNC
VTH,SYNC
SYNC Input Threshold
VOL,SYNC
SYNC Low Output
Voltage
SYNC Leakage Current in
Frequency Slave Mode
SYNC-to-Channel 0
Phase Relationship, Lag
from Falling Edge of Sync
to Rising Edge of Top
MOSFET (MT0) Gate
SYNC-to-Channel 1
Phase Relationship, Lag
from Falling Edge of Sync
to Rising Edge of Top
MOSFET (MT1) Gate
ISYNC
θSYNC-θ0
θSYNC-θ1
EEPROM Characteristics
Endurance
(Note 13)
Retention
(Note 13)
Mass_Write
Mass Write Operation
Time
CONDITIONS
READ_TEMPERATURE_2, PWM Active, RUN0 = RUN1 = 5V
(Note 12)
MIN
TYP
MAX UNITS
Within ±1°C of Reading
(Notes 9, 15)
6V ≤ VIN ≤ 26.5V
100
5
5.2
V
0.5
±2
%
3.3
70
3.5
3.4
VDD33 Electrically Short-Circuited to GND
(Note 15)
V
mA
V
(Note 15)
3.1
l
4.8
ms
0mA ≤ IINTVCC ≤ 50mA
l
l
3.2
2.25
VDD25 Electrically Short-Circuited to GND
FREQUENCY_SWITCH = 500kHz (0xFBE8)
250kHz ≤ FREQUENCY_SWITCH ≤ 1MHz (Note 15)
FREQUENCY_SWITCH Set to Frequency Slave Mode (0x0000);
SYNC Driven by External Clock; 3.3VOUT
VSYNC Rising (Note 15)
VSYNC Falling (Note 15)
ISYNC = 3mA
l
0V ≤ VSYNC ≤ 3.6V
FREQUENCY_SWITCH Set to Slave Mode (0x0000)
(Note 15)
MFR_PWM_CONFIG[2:0] = 000b, 01Xb
MFR_PWM_CONFIG[2:0] = 101b
MFR_PWM_CONFIG[2:0] = 001b
MFR_PWM_CONFIG[2:0] = 1X0b
(Note 15)
MFR_PWM_CONFIG[2:0] = 011b
MFR_PWM_CONFIG[2:0] = 000b
MFR_PWM_CONFIG[2:0] = 010b, 10Xb
MFR_PWM_CONFIG[2:0] = 001b
MFR_PWM_CONFIG[2:0] = 110b
l
0°C ≤ TJ ≤ 85°C During EEPROM Write Operations (Note 3)
TJ < TJ(MAX), with Most Recent EEPROM Write Operation Having
Occurred at 0°C ≤ TJ ≤ 85°C (Note 3)
Execution of STORE_USER_ALL Command, 0°C ≤ TJ ≤ 85°C
(ATE-Tested at TJ = 25°C) (Notes 3, 13)
l 10,000
l
225
1.5
1
0.3
l
l
2.5
50
V
2.75
V
mA
±7.5
±7.5
1100
%
%
kHz
0.4
V
V
V
±5
µA
0
60
90
120
Deg
Deg
Deg
Deg
120
180
240
270
300
Deg
Deg
Deg
Deg
Deg
Cycles
Years
10
440
4100
ms
Digital I/Os
8
4676fd
For more information www.linear.com/LTM4676
LTM4676
Electrical Characteristics
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V,
FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
VIH
VHYST
VOL
PARAMETER
Input High Threshold
Voltage
Input Low Threshold
Voltage
Input Hysteresis
Output Low Voltage
IOL
Input Leakage Current
tFILTER
Input Digital Filtering
VIL
Input Capacitance
CPIN
PMBus Interface Timing Characteristics
Serial Bus Operating
fSMB
Frequency
Bus Free Time Between
tBUF
Stop and Start
Hold Time After Repeated
tHD,STA
Start Condition
Repeated Start Condition
tSU,STA
Setup Time
Stop Condition Setup
tSU,STO
Time
Data Hold Time
tHD,DAT
tSU,DAT
tTIMEOUT_SMB
Data Setup Time
Stuck PMBus Timer
Timeout
tLOW
tHIGH
Serial Clock Low Period
Serial Clock High Period
CONDITIONS
SCL, SDA, RUNn, GPIOn (Note 15)
SHARE_CLK, WP (Note 15)
SCL, SDA, RUNn, GPIOn (Note 15)
SHARE_CLK, WP (Note 15)
SCL, SDA (Note 15)
SCL, SDA, ALERT, RUNn, GPIOn, SHARE_CLK:
ISINK = 3mA
SDA, SCL, ALERT, RUNn: 0V ≤ VPIN ≤ 5.5V
GPIOn and SHARE_CLK: 0V ≤ VPIN ≤ 3.6V
RUNn (Note 15)
GPIOn (Note 15)
SCL, SDA, RUNn, GPIOn, SHARE_CLK, WP (Note 15)
MIN
2.0
1.8
TYP
MAX
1.4
0.6
80
0.3
l
l
l
0.4
±5
±2
UNITS
V
V
V
V
mV
10
V
µA
µA
µs
µs
pF
400
kHz
10
3
(Note 15)
10
(Note 15)
1.3
µs
Time Period After Which First Clock Is Generated (Note 15)
0.6
µs
(Note 15)
0.6
µs
(Note 15)
0.6
µs
Receiving Data (Note 15)
Transmitting Data (Note 15)
Receiving Data (Note 15)
Measured from the Last PMBus Start Event:
Block Reads (Note 15)
Non-Block Reads (Note 15)
(Note 15)
(Note 15)
0
0.3
0.1
0.9
150
32
1.3
0.6
10000
µs
µs
µs
ms
ms
µs
µs
4676fd
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9
LTM4676
Electrical Characteristics
Note 1: Stresses beyond those listing under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating conditions for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4676 is tested under pulsed-load conditions such that
TJ ≈ TA. The LTM4676E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4676I is guaranteed to meet specifications over the
full –40°C to 125°C internal operating temperature range. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal resistance and other environmental
factors.
Note 3: The LTM4676’s EEPROM temperature range for valid write
commands is 0°C to 85°C. To achieve guaranteed EEPROM data retention,
execution of the “STORE_USER_ALL” command—i.e., uploading RAM
contents to NVM—outside this temperature range is not recommended.
However, as long as the LTM4676’s EEPROM temperature is less than
130°C, the LTM4676 will obey the STORE_USER_ALL command. Only
when EEPROM temperature exceeds 130°C, the LTM4676 will not act
on any STORE_USER_ALL transactions: instead, the LTM4676 NACKs
the serial command and asserts its relevant CML (communications,
memory, logic) fault bits. EEPROM temperature can be queried prior
to commanding STORE_USER_ALL; see the Applications Information
section.
Note 4: The two power inputs—VIN0 and VIN1—and their respective power
outputs—VOUT0 and VOUT1—are tested independently in production. A
shorthand notation is used in this document that allows these parameters
to be referred to by “VINn” and “VOUTn”, where n is permitted to take on
a value of 0 or 1. This italicized, subscripted “n ” notation and convention
is extended to encompass all such pin names, as well as register names
with channel-specific, i.e., paged data. For example, VOUT_COMMANDn
refers to the VOUT_COMMAND command code data located in Pages 0
and 1, which in turn relate to Channels 0 (VOUT0) and Channel 1 (VOUT1).
Registers containing non-page-specific data, i.e., whose data is “global” to
the module or applies to both of the module's Channels lack the italicized,
subscripted “n ”, e.g., FREQUENCY_SWITCH.
Note 5: VOUTn (DC) and line and load regulation tests are performed in
production with digital servo disengaged (MFR_PWM_MODEn[6] = 0b)
and low VOUTn range selected (MFR_PWM_CONFIG[6-n ] = 1b. The
digital servo control loop is exercised in production (setting MFR_PWM_
MODEn[6] = 1b), but convergence of the output voltage to its final settling
value is not necessarily observed in final test—due to potentially long
time constants involved—and is instead guaranteed by the output voltage
readback accuracy specification. Evaluation in application demonstrates
capability; see the Typical Performance Characteristics section.
Note 6: See output current derating curves for different VIN, VOUT, and TA,
located in the Applications Information section.
10
Note 7: Even though VOUT0 and VOUT1 and their associated currentsensing pins (ISNSn[a/b][+/–]) are specified for 6V absolute maximum
and recommended for not more than 5.5V continuous, the maximum
recommended command voltage to regulate output channels 0 and 1
is: 4.0V and 5.4V, respectively, when the VOUT range setting for those
channels—MFR_PWM_CONFIG’s bits 6 and 5, respectively—are set to
“high range”, i.e., 0b; and 2.5V for any channel whose respective
MFR_PWM_CONFIG VOUT range-setting bit is set to “low range”, i.e., 1b.
Note 8: Minimum on-time is tested at wafer sort.
Note 9: Data conversion is performed in round-robin (cyclic) fashion. All
telemetry signals are continuously digitized, and reported data is based on
measurements not older than 100ms, typical.
Note 10: The following telemetry parameters are formatted in PMBusdefined “Linear Data Format”, in which each register contains a word
comprised of 5 most significant bits—representing a signed exponent, to
be raised to the power of 2—and 11 least significant bits—representing
a signed mantissa: input voltage (on SVIN), accessed via the READ_VIN
command code; output currents (IOUTn), accessed via the READ_IOUTn
command codes; module input current (IVIN0 + IVIN1 + ISVIN), accessed via
the READ_IIN command code; channel input currents (IVINn + 1/2 • ISVIN),
accessed via the MFR_READ_IINn command codes;and duty cycles of
channel 0 and channel 1 switching power stages, accessed via the
READ_DUTY_CYCLEn command codes. This data format limits the
resolution of telemetry readback data to 10 bits even though the internal
ADC is 16 bits and the LTM4676’s internal calculations use 32-bit words.
Note 11: The absolute maximum rating for the SVIN pin is 28V. Input
voltage telemetry (READ_VIN) is obtained by digitizing a voltage scaled
down from the SVIN pin.
Note 12: These typical parameters are based on bench measurements and
are not production tested.
Note 13: EEPROM endurance and retention are guaranteed by wafer-level
testing for data retention. The minimum retention specification applies
for devices whose EEPROM has been cycled less than the minimum
endurance specification, and whose EEPROM data was written to at
0°C ≤ TJ ≤ 85°C. Downloading NVM contents to RAM by executing the
MFR_RESET command is valid over the entire operating temperature
range and does not influence EEPROM characteristics.
Note 14: V0OU-ACC OV/UV comparator threshold accuracy for
MFR_PWM_CONFIG[6] = 1b tested in ATE at VVOSNS0+ – VVOSNS0– =
0.5V and 2.7V. 1V condition tested at IC-Level, only. V1OU-ACC OV/UV
comparator threshold accuracy for MFR_PWM_CONFIG[5] = 1b tested
in ATE with VVOSNS1-VSGND = 0.5V and 2.7V. 1.5V condition tested at
IC-level, only.
Note 15: Tested at IC-level ATE.
4676fd
For more information www.linear.com/LTM4676
LTM4676
Typical Performance Characteristics
Efficiency vs Output Current,
8VIN, VOUT0 and VOUT1 Paralleled,
VIN = SVIN = VINn, INTVCC Open,
MFR_PWM_MODEn [1:0] = 10b
Efficiency vs Output Current,
12VIN, VOUT0 and VOUT1 Paralleled,
VIN = SVIN = VINn, INTVCC Open,
MFR_PWM_MODEn [1:0] = 10b
100
100
95
95
95
90
90
90
85
80
3.3VOUT, 425kHz
2.5VOUT, 425kHz
1.8VOUT, 425kHz
1.5VOUT, 350kHz
1.2VOUT, 350kHz
1.0VOUT, 350kHz
0.9VOUT, 350kHz
70
65
60
80
75
70
65
60
0 2 4 6 8 10 12 14 16 18 20 22 24 26
OUTPUT CURRENT (A)
4676 G01
90
75
60
0 2 4 6 8 10 12 14 16 18 20 22 24 26
OUTPUT CURRENT (A)
4676 G03
Single Phase Single Output
Burst Mode Efficiency,
VIN = SVIN = VINn, INTVCC Open,
MFR_PWM_MODEn [1:0] = 01b
80
80
75
65
65
4676 G04
0 2 4 6 8 10 12 14 16 18 20 22 24 26
OUTPUT CURRENT (A)
90
85
70
0 2 4 6 8 10 12 14 16 18 20 22 24 26
OUTPUT CURRENT (A)
3.3VOUT, 650kHz
2.5VOUT, 575kHz
1.8VOUT, 500kHz
1.5VOUT, 425kHz
1.2VOUT, 350kHz
1.0VOUT, 350kHz
0.9VOUT, 350kHz
95
70
60
65
90
80
75
70
100
1.2VOUT, 350kHz
1.0VOUT, 250kHz
0.9VOUT, 250kHz
85
80
Efficiency vs Output Current,
VOUT1 = 5V, VOUT0 = OFF,
VIN = SVIN = VINn, INTVCC Open,
MFR_PWM_MODEn [1:0] = 10b
EFFICIENCY (%)
95
3.3VOUT, 750kHz
2.5VOUT, 650kHz
1.8VOUT, 500kHz
1.5VOUT, 425kHz
85
4676 G02
Efficiency vs Output Current,
24VIN, VOUT0 and VOUT1 Paralleled,
VIN = SVIN = VINn, INTVCC Open,
MFR_PWM_MODEn [1:0] = 10b
100
3.3VOUT, 575kHz
2.5VOUT, 500kHz
1.8VOUT, 425kHz
1.5VOUT, 350kHz
1.2VOUT, 350kHz
1.0VOUT, 350kHz
0.9VOUT, 350kHz
EFFICIENCY (%)
75
85
EFFICIENCY (%)
100
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs Output Current, 5VIN,
VOUT0 and VOUT1 Paralleled,
VIN = SVIN = VINn = INTVCC,
MFR_PWM_MODEn [1:0] = 10b
EFFICIENCY (%)
TA = 25°C, 12VIN to 1VOUT, unless otherwise noted.
60
8VIN, 500kHz
12VIN, 750kHz
24VOUT, 1MHz
0 1 2 3 4 5 6 7 8 9 10 11 12 13
OUTPUT CURRENT (A)
4676 G05
70
60
50
40
24VIN TO 5VOUT, 1MHz
12VIN TO 1.5VOUT, 425kHz
0 1 2 3 4 5 6 7 8 9 10 11 12 13
OUTPUT CURRENT (A)
4676 G06
4676fd
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11
LTM4676
Typical Performance Characteristics
Single Phase Single Output
Pulse-Skipping (Discontinuous)
Mode Efficiency,
VIN = SVIN = VINn, INTVCC Open,
MFR_PWM_MODEn [1:0] = 00b
TA = 25°C, 12VIN to 1VOUT, unless otherwise noted.
Dual Phase Single Output Load
Transient Response,12VIN to 1VOUT
Single Phase Single Output Load
Transient Response,12VIN to 1VOUT
90
EFFICIENCY (%)
80
VOUT
50mV/DIV
AC-COUPLED
VOUT0
50mV/DIV
AC-COUPLED
IOUT
8A/DIV
IOUT
4A/DIV
70
60
4676 G08
40µs/DIV
FIGURE 35 CIRCUIT AT 12VIN, INTVCC PIN
OPEN CIRCUIT AND VOUT_COMMANDn SET
TO 1.000V. 0A TO 20A LOAD STEP AT 20A/µs
50
40
24VIN TO 5VOUT, 1MHz
12VIN TO 1.5VOUT, 425kHz
40µs/DIV
FIGURE 44 CIRCUIT AT 12VIN
0A TO 10A LOAD STEP AT 10A/µs
4676 G09
0 1 2 3 4 5 6 7 8 9 10 11 12 13
OUTPUT CURRENT (A)
Single Phase Single Output Load
Transient Response,
24VIN to 3.3VOUT
4676 G07
Dual Phase Single Output Load
Transient Response, 5VIN to 1VOUT
Single Phase Single Output Load
Transient Response, 24VIN to 1VOUT
VOUT
50mV/DIV
AC-COUPLED
VOUT0
50mV/DIV
AC-COUPLED
VOUT0
50mV/DIV
AC-COUPLED
IOUT
8A/DIV
IOUT
4A/DIV
IOUT
4A/DIV
40µs/DIV
FIGURE 35 CIRCUIT AT 5VIN,
VOUT_COMMANDn SET TO 1.000V.
0A TO 20A LOAD STEP AT 20A/µs
4676 G10
40µs/DIV
FIGURE 44 CIRCUIT AT 24VIN
0A TO 10A LOAD STEP AT 10A/µs
Dual Output Concurrent Rail
Start-Up/Shutdown
Dual Output Start-Up/Shutdown
with a Pre-Biased Load
VOUT0, VOUT1
500mV/DIV
VOUT0, VOUT1
500mV/DIV
IOUT0
5A/DIV
IDIODE
1mA/DIV
RUN0, RUN1
5V/DIV
RUN0, RUN1
5V/DIV
4676 G13
2ms/DIV
FIGURE 44 CIRCUIT AT 12VIN, 77mΩ LOAD ON
VOUT0, NO LOAD ON VOUT1. TON_RISE0 = 3ms,
TON_RISE1 = 5.297ms, TOFF_DELAY1 = 0ms,
TOFF_DELAY0 = 2.43ms, TOFF_FALL1 = 5.328ms,
TOFF_FALL0 = 3ms, ON_OFF_CONFIGn = 0x1E
12
4676 G12
40µs/DIV
FIGURE 44 CIRCUIT AT 24VIN, COUT0 = 5× 100µF
AND VOUT0 COMMANDED TO 3.300V.
0A TO 10A LOAD STEP AT 10A/µs
4676 G11
Single Phase Single Output Short-Circuit Protection at No Load
VOUT0
200mV/DIV
IIN0
1A/DIV
4676 G14
2ms/DIV
FIGURE 44 CIRCUIT AT 12VIN, 77mΩ LOAD ON
VOUT0, 500Ω ON VOUT1. VOUT1 PRE-BIASED
THROUGH A DIODE. TON_RISE0 = 3ms,
TON_RISE1 = 5.297ms, TOFF_DELAY1 = 0ms,
TOFF_DELAY0 = 2.43ms, TOFF_FALL1 = 5.328ms,
TOFF_FALL0 = 3ms, ON_OFF_CONFIG1 = 0x1F
ON_OFF_CONFIG0 = 0x1E
4676 G15
10µs/DIV
FIGURE 44 CIRCUIT AT 12VIN,
NO LOAD ON VOUT0 PRIOR TO APPLICATION
OF SHORT CIRCUIT
4676fd
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LTM4676
Typical Performance Characteristics
TA = 25°C, 12VIN to 1VOUT, unless otherwise noted.
READ_VOUTn (Output Voltage
Readback) Error vs VOUTn
IOUTn = No Load, RUN1-n = 0V
Single Phase Single Output ShortCircuit Protection at Full Load
READ_IOUTn (Output Current
Readback) Error vs IOUTn
60
300
IIN0
1A/DIV
4676 G16
10µs/DIV
FIGURE 44 CIRCUIT AT 12VIN,
77mΩ LOAD ON VOUT0 PRIOR TO APPLICATION
OF SHORT CIRCUIT
SPECIFIED UPPER LIMIT
40
MEASUREMENT ERROR (mA)
VOUT0
200mV/DIV
MEASUREMENT ERROR (mV)
50
30
20
CHANNEL 0
10
0
CHANNEL 1
–10
–20
–30
–40
SPECIFIED LOWER LIMIT
–50
200
100
0
CHANNEL 0
–100
CHANNEL 1
–200
–300
–60
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VOUT (V)
SPECIFIED UPPER LIMIT
SPECIFIED LOWER LIMIT
3.25
0
6.50
IOUT (A)
9.75
4676 G17
600
0.6
MEASUREMENT ERROR (mV)
MEASUREMENT ERROR (°C)
0.8
0.4
0.2
0
–0.2
–0.4
–0.6
4676 G19
MFR_READ_IINn (Input Current
Readback) Error vs (IVINn + ISVIN),
MFR_PWM_MODEn[1:0]=10b,
IOUTn Swept from 0A to 13A, One
Channel at a Time, RUN1-n = 0V
READ_VIN (Input Voltage
Readback Telemetry) Error vs
SVIN, RUNn = 0V
200
SPECIFIED UPPER LIMIT
SPECIFIED UPPER LIMIT
400
200
0
–200
100
CHANNEL 1
0
CHANNEL 0
–100
–400
–600
SPECIFIED LOWER LIMIT
SPECIFIED LOWER LIMIT
–0.8
–1.0
–45 –25 –5 15 35 55 75 95 115
ACTUAL TEMPERATURE (°C)
4676 G18
MEASUREMENT ERROR (mA)
1.0
READ_TEMPERATURE_2
(Control IC Temperature Error) vs
Junction Temperature, RUNn = 0V
13.00
4
10
16
SVIN (V)
22
28
4676 G20
–200
0
0.2
0.4
0.6 0.8 1.0
IINn + ISVIN (A)
1.2
1.4
4676 G21
4676fd
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13
LTM4676
READ_OUT of 20 LTM4676s
(DC1811A) 12VIN, 1VOUT,
TJ = 25°C, IOUTn = 13A, System
Having Reached Thermally
Steady-State Condition, No Airflow
READ_OUT of 20 LTM4676s
(DC1811A) 12VIN, 1VOUT,
TJ = 125°C, IOUTn = 13A, System
Having Reached Thermally
Steady-State Condition, No Airflow
12
10
10
10
READ_IOUT CHANNEL READBACK (A) 4676 G22
READ_IOUT CHANNEL READBACK (A) 4676 G23
13.21875
13.18750
12.96875
13.25000
13.21875
13.18750
13.15625
13.12500
13.09375
13.06250
13.03125
13.00000
13.37500
13.34375
13.31250
0
13.28125
0
13.25000
0
13.21875
2
13.18750
2
13.15625
2
13.15625
4
13.12500
4
6
13.09375
4
6
8
13.06250
6
8
13.03125
8
NUMBER OF CHANNELS
12
NUMBER OF CHANNELS
12
13.12500
NUMBER OF CHANNELS
READ_OUT of 20 LTM4676s
(DC1811A) 12VIN, 1VOUT,
TJ = –40°C, IOUTn = 13A, System
Having Reached Thermally
Steady-State Condition, No Airflow
TA = 25°C, 12VIN to 1VOUT, unless otherwise noted.
13.00000
Typical Performance Characteristics
READ_IOUT CHANNEL READBACK (A) 4676 G24
Pin Functions
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
GND (A4, A6-10, B4-B9, C4, C6-C9, D4, D7, E3, F3,
F10, G3, G10-12, H3, H10, J4, J10, K4, K7-9, L4-9, M4,
M6-10): Power Ground of the LTM4676. Power return for
VOUT0 and VOUT1.
VOUT0 (A1-3, B1-3, C1-3, D1-3): Channel 0 Output Voltage.
VOSNS0+ (D9): Channel 0 Positive Differential Voltage Sense
Input. Together, VOSNS0+ and VOSNS0– serve to kelvin-sense
the VOUT0 output voltage at VOUT0’s point of load (POL)
and provide the differential feedback signal directly to
Channel 0’s control loop and voltage supervisor circuits.
VOUT0 can regulate up to 4.0V output. Command VOUT0’s
target regulation voltage by serial bus. Its initial command
value at SVIN power-up is dictated by NVM (non-volatile
memory) contents (factory default: 1.000V)—or, optionally, may be set by configuration resistors; see VOUT0CFG,
VTRIM0CFG and the Applications Information section.
VOSNS0– (E9): Channel 0 Negative Differential Voltage
Sense Input. See VOSNS0+.
14
VORB0+ (D10): Channel 0 Positive Readback Pin. Shorted
to VOSNS0+ internal to the LTM4676. If desired, place a test
point on this node and measure its impedance to VOUT0
on one’s hardware (e.g., motherboard, during in circuit
test (ICT) post-assembly process) to provide a means of
verifying the integrity of the feedback signal connection
between VOSNS0+ and VOUT0.
VORB0– (E10): Channel 0 Negative Readback Pin. Shorted
to VOSNS0– internal to the LTM4676. If desired, place a
test point on this node and measure its impedance to
GND on one’s hardware (e.g., motherboard, during ICT
post-assembly process) to provide a means of verifying
the integrity of the feedback signal connection between
VOSNS0– and GND (VOUT0 power return).
VOUT1 (J1-3, K1-3, L1-3, M1-3): Channel 1 Output Voltage.
VOSNS1 (H9): Channel 1 Positive Voltage Sense Input.
Connect VOSNS1 to VOUT1 at the POL. This provides the
feedback signal for channel 1's control loop and voltage
supervisor circuits. VOUT1 can regulate up to 5.4V output.
Command VOUT1’s target regulation voltage by serial bus.
Its initial command value at SVIN power-up is dictated by
NVM (non-volatile memory) contents (factory default:
4676fd
For more information www.linear.com/LTM4676
LTM4676
Pin Functions
1.000V)—or, optionally, may be set by configuration
resistors; see VOUT1CFG, VTRIM1CFG and the Applications
Information section.
action of Channel 0, if desired, but do not route near any
sensitive signals; otherwise, leave electrically isolated
(open).
SGND (F7-8, G7-8): Channel 1 Negative Voltage Sense
Input. See VOSNS1. Additionally, SGND is the signal ground
return path of the LTM4676. If desired, one may place a
test point on one of the four SGND pins and measure its
impedance to GND on one’s hardware (e.g., motherboard,
during ICT post-assembly process) to provide a means
of verifying the integrity of the feedback signal connection between the other three SGND pins and GND (VOUT1
power return). SGND is not electrically connected to GND
internal to the LTM4676. Connect SGND to GND local to
the LTM4676.
SW1 (L10): Switching Node of Channel 1 Step-Down
Converter Stage. Used for test purposes or EMI-snubbing
heavier than that supported by SNUB1. May be routed a
short distance to a local test point to monitor switching
action of Channel 1, if desired, but do not route near any
sensitive signals; otherwise, leave open.
VORB1 (J9): Channel 1 Positive Readback Pin. Shorted to
VOSNS1 internal to the LTM4676. At one’s option, place
a test point on this node and measure its impedance to
VOUT1 on one’s hardware (e.g., motherboard, during ICT
post-assembly process) to provide a means of verifying
the integrity of the feedback signal connection between
VOUT1 and VOSNS1.
SNUB1 (M5): Access to Channel 1 Switching Stage Snubber
Capacitor. Connecting an optional resistor from SNUB0 to
GND can reduce radiated EMI, with only a minor penalty
towards power conversion efficiency. See the Applications
Information section. Pin should otherwise be left open.
VIN0 (A11-12, B11-12, C11-12, D11-12, E12): Positive
Power Input to Channel 0 Switching Stage. Provide sufficient decoupling capacitance in the form of multilayer
ceramic capacitors (MLCCs) and low ESR electrolytic (or
equivalent) to handle reflected input current ripple from the
step-down switching stage. MLCCs should be placed as
close to the LTM4676 as physically possible. See Layout
Recommendations in the Applications Information section.
VIN1 (H12, J11-12, K11-12, L11-12, M11-12): Positive
Power Input to Channel 1 Switching Stage. Provide sufficient decoupling capacitance in the form of MLCCs and
low ESR electrolytic (or equivalent) to handle reflected
input current ripple from the step-down switching stage.
MLCCs should be placed as close to the LTM4676 as
physically possible. See Layout Recommendations in the
Applications Information section.
SW0 (B10): Switching Node of Channel 0 Step-Down
Converter Stage. Used for test purposes or EMI-snubbing
heavier than that supported by SNUB0. May be routed a
short distance to a local test point to monitor switching
SNUB0 (A5): Access to Channel 0 Switching Stage Snubber
Capacitor. Connecting an optional resistor from SNUB0 to
GND can reduce radiated EMI, with only a minor penalty
towards power conversion efficiency. See the Applications
Information section. Pin should otherwise be left open.
SVIN (F11-12): Input Supply for LTM4676’s Internal Control
IC. In most applications, SVIN connects to VIN0 and/or VIN1,
in which case no external decoupling beyond that already
allocated for VIN0/VIN1 is required. If SVIN is operated from
an auxiliary supply separate from VIN0/VIN1, decouple this
pin to GND with a capacitor (0.1µF to 1µF).
INTVCC (F9, G9): Internal Regulator, 5V Output. When
operating the LTM4676 from 5.75V ≤ SVIN ≤ 26.5V, an
LDO generates INTVCC from SVIN to bias internal control
circuits and the MOSFET drivers of the LTM4676. No external decoupling is required. INTVCC is regulated regardless
of the RUNn pin state. When operating the LTM4676 with
4.5V ≤ SVIN < 5.75V, INTVCC must be electrically shorted
to SVIN.
VDD33 (J7): Internally Generated 3.3V Power Supply Output
Pin. This pin should only be used to provide external current
for the pull-up resistors required for GPIOn, SHARE_CLK,
and SYNC, and may be used to provide external current
for pull-up resistors on RUNn, SDA, SCL and ALERT. No
external decoupling is required.
4676fd
For more information www.linear.com/LTM4676
15
LTM4676
Pin Functions
VDD25 (J6): Internally Generated 2.5V Power Supply Output
Pin. Do not load this pin with external current; it is used
strictly to bias internal logic and provides current for the
internal pull-up resistors connected to the configurationprogramming pins. No external decoupling is required.
ASEL (G4): Serial Bus Address Configuration Pin. On any
given I2C/SMBus serial bus segment, every device must
have its own unique slave address. If this pin is left open,
the LTM4676 powers up to its default slave address of
0x4F (hexadecimal), i.e., 1001111b (industry standard
convention is used throughout this document: 7-bit slave
addressing). The lower four bits of the LTM4676’s slave
address can be altered from this default value by connecting
a resistor from this pin to SGND—hence configuring the
7-bit slave address of the LTM4676 to one of 16 supported
values. Minimize capacitance—especially when the pin is
left open—to assure accurate detection of the pin state.
FSWPHCFG (H4): Switching Frequency, Channel PhaseInterleaving Angle and Phase Relationship to SYNC Configuration Pin. If this pin is left open—or, if the LTM4676
is configured to ignore pin-strap (RCONFIG) resistors,
i.e., MFR_CONFIG_ALL[6] = 1b—then the LTM4676’s
switching frequency (FREQUENCY_SWITCH) and channel phase relationships (with respect to the SYNC clock;
MFR_PWM_CONFIG[2:0]) are dictated at SVIN power-up
according to the LTM4676’s NVM contents. Default factory
values are: 500kHz operation; Channel 0 at 0°; and Channel 1 at 180°C (convention throughout this document: a
phase angle of 0° means the channel’s switch node rises
coincident with the falling edge of the SYNC pulse). Connecting a resistor from this pin to SGND (and using the
factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b)
allows a convenient way to configure multiple LTM4676s
with identical NVM contents for different switching frequencies of operation and phase interleaving angle settings of
intra- and extra-module-paralleled channels—all, without
GUI intervention or the need to “custom pre-program”
module NVM contents. (See the Applications Information
section.) Minimize capacitance—especially when the pin
is left open—to assure accurate detection of the pin state.
VOUT0CFG (G5): Output Voltage Select Pin for VOUT0,
Coarse Setting. If the VOUT0CFG and VTRIM0CFG pins are
both left open—or, if the LTM4676 is configured to ignore
16
pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6]
= 1b—then the LTM4676’s target VOUT0 output voltage
setting (VOUT_COMMAND0) and associated powergood and OV/UV warning and fault thresholds are dictated at SVIN power-up according to the LTM4676’s
NVM contents. A resistor connected from this pin to
SGND—in combination with resistor pin settings on
VTRIM0CFG, and using the factory-default NVM setting
of MFR_CONFIG_ALL[6] = 0b—can be used to configure the LTM4676’s Channel 0 output to power-up to a
VOUT_COMMAND value (and associated output voltage
monitoring and protection/fault-detection thresholds) different from those of NVM contents. (See the Applications
Information section.) Connecting resistor(s) from VOUT0CFG
to SGND and/or VTRIM0CFG to SGND in this manner allows a convenient way to configure multiple LTM4676s
with identical NVM contents for different output voltage
settings—all without GUI intervention or the need to
“custom-pre-program” module NVM contents. Minimize
capacitance—especially when the pin is left open—to
assure accurate detection of the pin state. Note that use
of RCONFIGs on VOUT0CFG/VTRIM0CFG can affect the VOUT0
range setting (MFR_PWM_CONFIG[6]) and loop gain.
VTRIM0CFG (H5): Output Voltage Select Pin for VOUT0, Fine
Setting. Works in combination with VOUT0CFG to affect
the VOUT_COMMAND (and associated output voltage
monitoring and protection/fault-detection thresholds)
of Channel 0, at SVIN power-up. (See VOUT0CFG and the
Applications Information section.) Minimize capacitance—
especially when the pin is left open—to assure accurate
detection of the pin state. Note that use of RCONFIGs on
VOUT0CFG/VTRIM0CFG can affect the VOUT0 range setting
(MFR_PWM_CONFIG[6]) and loop gain.
VOUT1CFG (G6): Output Voltage Select Pin for VOUT1, Coarse
Setting. If the VOUT1CFG and VTRIM1CFG pins are both left
open—or, if the LTM4676 is configured to ignore pin-strap
(RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6] = 1b—
then the LTM4676’s target VOUT1 output voltage setting
(VOUT_COMMAND1) and associated power good and
OV/UV warning and fault thresholds are dictated at SVIN
power-up according to the LTM4676’s NVM contents, in
precisely the same fashion that the VOUT0CFG and VTRIM0CFG
pins affect the respective settings of VOUT0/Channel 0. (See
VOUT0CFG, VTRIM0CFG and the Applications Information
4676fd
For more information www.linear.com/LTM4676
LTM4676
Pin Functions
section.) Minimize capacitance—especially when the pin
is left open—to assure accurate detection of the pin state.
Note that use of RCONFIGs on VOUT1CFG/VTRIM1CFG can
affect the VOUT1 range setting (MFR_PWM_CONFIG[5])
and loop gain.
is required, the user’s SMBus master(s) need to implement
clock stretching support to assure solid serial bus communications, and only then should MFR_CONFIG_ALL[1] be
set to 1b. When clock stretching is enabled, SCL becomes
a bidirectional, open-drain output pin on LTM4676.
VTRIM1CFG (H6): Output Voltage Select Pin for VOUT1, Fine
Setting. Works in combination with VOUT1CFG to affect
the VOUT_COMMAND (and associated output voltage
monitoring and protection/fault-detection thresholds)
of Channel 1, at SVIN power-up. (See VOUT1CFG and the
Applications Information section.) Minimize capacitance—
especially when the pin is left open—to assure accurate
detection of the pin state. Note that use of RCONFIGs on
VOUT1CFG/VTRIM1CFG can affect the VOUT1 range setting
(MFR_PWM_CONFIG[5]) and loop gain.
SDA (D6): Serial Bus Data Open-Drain Input and Output.
A pull-up resistor to 3.3V is required in the application.
SYNC (E7): PWM Clock Synchronization Input and OpenDrain Output Pin. The setting of the FREQUENCY_SWITCH
register dictates whether the LTM4676 is a “sync master”
or “sync slave” module. When the LTM4676 is a sync
master, FREQUENCY_SWITCH contains the commanded
switching frequency of Channels 0 and 1—in PMBus linear
data format—and it drives its SYNC pin low for 500ns
at a time, at this commanded rate. In contrast, a sync
slave uses FREQUENCY_SWITCH=0x0000 and does not
pull its SYNC pin low. The LTM4676’s PLL synchronizes
the LTM4676’s PWM clock to the waveform present on
the SYNC pin—and therefore, a resistor pull-up to 3.3V
is required in the application, regardless of whether the
LTM4676 is a sync master or slave. EXCEPTION: driving
the SYNC pin with an external clock is permissible; see
the Applications Information section for details.
SCL (E6): Serial Bus Clock Open-Drain Input (Can Be an
Input and Output, if Clock Stretching is Enabled). A pull-up
resistor to 3.3V is required in the application for digital communication to the SMBus master(s) that nominally drive
this clock. The LTM4676 will never encounter scenarios
where it would need to engage clock stretching unless SCL
communication speeds exceed 100kHz—and even then,
LTM4676 will not clock stretch unless clock stretching
is enabled by means of setting MFR_CONFIG_ALL[1] =
1b. The factory-default NVM configuration setting has
MFR_CONFIG_ALL[1] = 0b: clock stretching disabled. If
communication on the bus at clock speeds above 100kHz
ALERT (E5): Open-Drain Digital Output. A pull-up resistor
to 3.3V is required in the application only if SMBALERT
interrupt detection is implemented in one’s SMBus system.
SHARE_CLK (H7): Share Clock, Bidirectional Open-Drain
Clock Sharing Pin. Nominally 100kHz. Used for synchronizing the time base between multiple LTM4676s (and
any other Linear Technology devices with a SHARE_CLK
pin)—to realize well-defined rail sequencing and rail tracking. Tie the SHARE_CLK pins of all such devices together;
all devices with a SHARE_CLK pin will synchronize to the
fastest clock. A pull-up resistor to 3.3V is required when
synchronizing the time base between multiple devices. If
synchronizing the time base between multiple devices is
not needed and MFR_CHAN_CONFIGn[2] = 0b, only then
is a pull-up resistor not required.
GPIO 0, GPIO 1 (E4 and F4, Respectively): Digital,
Programmable General Purpose Inputs and Outputs.
Open-drain outputs and/or high impedance inputs.
The LTM4676’s factory-default NVM configurations for
MFR_GPIO_PROPAGATEn—0x6893—and MFR_GPIO_
RESPONSEn—0xC0—are such that: (1) when a channelspecific fault condition is detected—such as channel OT
(overtemperature) or output UV/OV—the respective GPIOn
pin pulls logic low; (2) when a non-channel specific fault
condition is detected—such as input OV or control IC
OT—both GPIOn pins pull logic low; (3) the LTM4676
ceases switching action on Channel 0 and 1 when its
respective GPIOn pin is logic low. Most significantly, this
default configuration provides for graceful integration and
interoperation of LTM4676 with paralleled channel(s) of
other LTM4676(s)—in terms of properly coordinating efforts in starting, ceasing, and resuming switching action
and output voltage regulation, in unison—all without GUI
intervention or the need to “custom-preprogram” module
NVM contents. Pull-up resistors from GPIOn to 3.3V are
required for proper operation in the vast majority of ap4676fd
For more information www.linear.com/LTM4676
17
LTM4676
Pin Functions
plications. (Only if the LTM4676’s MFR_GPIO_RESPONSEn
value were set to 0x00 might pull-ups be unnecessary. See
the Applications Information section for details.)
ISNS0a+, ISNS0b+ (F2 and F1, Respectively): Channel 0
Positive Current Sense and Kelvin Sense Pins, Respectively.
Connect ISNS0a+ to ISNS0b+.
WP (K6): Write Protect Pin, Active High. An internal
10µA current source pulls this pin to VDD33. If WP is
open circuit or logic high, only I2C writes to PAGE, OPERATION, CLEAR_FAULTS, MFR_CLEAR_PEAKS and
MFR_EE_UNLOCK are supported. Additionally, individual
faults can be cleared by writing 1b’s to bits of interest in
registers prefixed with “STATUS”. If WP is low, I2C writes
are unrestricted.
ISNS1a+, ISNS1b+ (H2 and H1, Respectively): Channel 1
Positive Current Sense and Kelvin Sense Pins, Respectively.
Connect ISNS1a+ to ISNS1b+.
RUN0, RUN1 (F5 and F6, Respectively): Enable Run Input
for Channels 0 and 1, Respectively. Open-drain input and
output. Logic high on these pins enables the respective
outputs of the LTM4676. These open-drain output pins
hold the pin low until the LTM4676 is out of reset and
SVIN is detected to exceed VIN_ON. A pull-up resistor to
3.3V is required in the application. Do not pull RUN logic
high with a low impedance source.
TSNS0a, TSNS0b (D5 and C5, Respectively): Channel 0
Temperature Excitation/Measurement and Thermal Sensor
Pins, Respectively. Connect TSNS0a to TSNS0b. This allows
the LTM4676 to monitor the power stage temperature of
channel 0.
TSNS1a, TSNS1b (J5 and K5, Respectively): Channel 1
Temperature Excitation/Measurement and Thermal Sensor
Pins, Respectively. In most applications, connect TSNS1a
to TSNS1b. This allows the LTM4676 to monitor the power
stage temperature of channel 1. See the Applications Information section for information on how to use TSNS1a
to monitor a temperature sensor external to the module,
e.g., a PN junction on the die of a microprocessor.
ISNS0a–, ISNS0b– (E2 and E1, Respectively): Channel 0
Negative Current Sense and Kelvin Sense Pins, Respectively. Connect ISNS0a– to ISNS0b–.
ISNS1a–, ISNS1b– (G2 and G1, Respectively): Channel 1
Negative Current Sense and Kelvin Sense Pins, Respectively. Connect ISNS1a– to ISNS1b–.
COMP0a, COMP1a (E8 and H8, Respectively): Current
Control Threshold and Error Amplifier Compensation Nodes
for Channels 0 and 1, Respectively. The trip threshold of
each channel’s current comparator increases with a respective rise in COMPna voltage. Small filter capacitors (22pF)
internal to the LTM4676 on these COMP pins (terminated
to SGND) introduce high frequency roll off of the erroramplifier response, yielding good noise rejection in the
control loop. See COMP0b/COMP1b.
COMP0b, COMP1b (D8 and J8, Respectively): Internal
Loop Compensation Networks for Channels 0 and 1, Respectively. For the vast majority of applications, the internal,
default loop compensation of the LTM4676 is suitable to
apply “as is”, and yields very satisfactory results: apply the
default loop compensation to the control loops of Channels 0 and 1 by simply connecting COMP0a to COMP0b
and COMP1a to COMP1b, respectively. In contrast, when
more specialized applications require a personal touch the
optimization of control loop response, this can be easily
accomplished by connecting (an) R-C network(s) from
COMP0a and/or COMP1a—terminated to SGND—and
leaving COMP0b and/or COMP1b open, as desired.
DNC (C10, E11, H11, K10): Do not connect these pins
to external circuitry. Solder these pins only to mounting
pads on the PC board for mechanical integrity. These pads
must remain electrically open circuit.
18
4676fd
For more information www.linear.com/LTM4676
LTM4676
Simplified Block Diagram
VIN
5.75V TO 26.5V
+
CINL
CINH
VIN0
SNUB0
VOUT0
ADJUSTABLE
UP TO 4.0V
UP TO 13A
2.2nF
+
COUT0LF
GND
2.2µF
ISNS0b–
VIN1
POWER CONTROL
ANALOG SECTION
600nH
THERMAL
SENSOR
2.2nF
1µF
MT0
VOUT0
INTVCC VDD33
1µF
SW0
COUT0HF
SVIN
MB0
SNUB1
MT1
600nH
VOUT1
2.2µF
THERMAL
SENSOR
MB1
ISNS1a–
TSNS0b
TSNS1b
TSNS0a
TSNS1a
VORB0+
VORB1[+]
VORB0–
+
x1
–
TO ERROR
AMPLIFIER
VOSNS1[+]
ANALOG
READBACK
SIGNALS
CONTROLLER SIGNAL GND
COMP1a
INTERNAL
COMP
ADC
COMP1b
INTERNAL
COMP
SCL
5V TOLERANT; PULL-UP
RESISTORS NOT SHOWN
3.3V TOLERANT; PULL-UP
RESISTOR NOT NEEDED
5V TOLERANT; PULL-UP
RESISTORS NOT SHOWN
3.3V TOLERANT; PULL-UP
RESISTORS NOT SHOWN
SYNC
SDA
3.3V TOLERANT; PULL-UP
RESISTOR NOT SHOWN
VDD25
SPI
SLAVE
ALERT
WP
RUN0
LOCAL
HIGH
LOAD1
FREQ
MLCCs
SGND [VOSNS1–]
COMP0a
COMP0b
COUT1HF
ISNS1a+
THERMAL
SENSOR
ISNS0a–
VOSNS0–
COUT1LF
ISNS1b+
ISNS0a+
VOSNS0+
+
GND
ISNS1b–
ISNS0b+
LOCAL
HIGH
LOAD0
FREQ
MLCCs
VOUT1
ADJUSTABLE
UP TO 5.4V
UP TO 13A
SW1
ASEL
POWER MANAGEMENT
DIGITAL SECTION
SPI
MASTER
RUN1
GPIO0
ROM
DIGITAL ENGINE
GPIO1
RAM
EEPROM
SYNC
DRIVER
FSWPHCFG
VOUT0CFG
CONFIGURATION
RESISTORS TERMINATING
TO SGND NOT SHOWN
VTRIM0CFG
OSC
(32MHz)
VOUT1CFG
VTRIM1CFG
SHARE_CLK
4676 F01
Figure 1. Simplified LTM4676 Block Diagram
Decoupling Requirements
TA = 25°C. Using Figure 1 configuration.
SYMBOL
PARAMETER
CONDITIONS
CINH
External High Frequency Input Capacitor Requirement
(5.75V ≤ VIN ≤ 26.5V, VOUTn Commanded to 1.000V)
IOUT0 = 13A, 3 × 22µF, or 4 × 10µF
IOUT1 = 13A, 3 × 22µF, or 4 × 10µF
COUTnHF
External High Frequency Output Capacitor Requirement
(5.75V ≤ VIN ≤ 26.5V, VOUTn Commanded to 1.000V)
IOUT0 = 13A
IOUT1 = 13A
MIN
TYP
MAX
UNITS
40
66
µF
400
400
µF
µF
4676fd
For more information www.linear.com/LTM4676
19
For more information www.linear.com/LTM4676
+
COUT0LF
LOCAL
HIGH
FREQ
MLCCs
3.3V Tolerant; Pull-Up
Resistors Not Shown
5V Tolerant; Pull-Up
Resistors Not Shown
3.3V Tolerant; Pull-Up
Resistor Not Needed
5V Tolerant; Pull-Up
Resistors Not Shown
(LOAD0 Power Consumption
Telemetry: READ_POUT0)
LOAD0
COUT0HF
RSNUB0
UP TO
2W
(VOUT0 Telemetry:
READ_VOUT0 and
MFR_VOUT_PEAK0)
VOUT0
ADJUSTABLE
UP TO 4.0V
UP TO 13A
Optional Snubber
Resistor for Moderate
Reduction in EMI
(Size: EIA0603 ~EIA2512)
CINL
–
R
R
VOSNS0–
SHARE_CLK
GPIO1
GPIO0
RUN1
RUN0
WP
ALERT
SDA
SCL
COMP0b
COMP0a
R
+
A=1
–
R
CHANNEL TIMING
MANAGEMENT
I
INTERFACE WITH PMBus
COMMAND SET
(10kHz TO 400kHz
COMPATIBLE)
2C-BASED SMBus
VDD33
ZCOMP0b
UVLO
TMUX
ROM
PROGRAM
16-BIT
ADC
VTSNS
30µA
RAM
22pF
MB1
EEPROM
ZISNS1a
ZISNS1b+
ZISNS1b–
+ –
VORB1[+]
TSNS1a
TSNS1b
ISNS1a–
ISNS1a+
ISNS1b+
ISNS1b–
GND
VOUT1
CONFIG
DETECT
SYNC
DRIVER
1nF + 20kΩ
ZCOMP1b
SW1
SNUB1
COMP1a
COMP1b
14.3k
×6
VTRIM1CFG
VOUT1CFG
VTRIM0CFG
VOUT0CFG
FSWPHCFG
ASEL
VDD25
(Switching Frequency Telemetry:
READ_FREQUENCY) SYNC
Channel 1 Internal Loop Compensation
Channel 1 Current Demand Signal
SGND [VOSNS1–]
VOSNS1[+]
Channel 1 (VOUT1) Voltage Feedback Signal
(Differential when Terminating SGND at LOAD1 as Shown)
Channel 1 Current Sense Signal, ∆ISNS1a
Channel 1 Thermal Sensor
(Telemetry: READ_TEMPERATURE_11
and MFR_TEMPERATURE_1_PEAK1)
(IOUT1 Telemetry: READ_IOUT1
and MFR_IOUT_PEAK1)
Controller Signal GND
OSC
(32MHz)
SINC3
SPI
MASTER
SPI
SLAVE
DACs, OV/UV
Comparators,
Other
8:1 MUX
DIGITAL ENGINE, MAIN CONTROL
VDD33
COMPARE
VDD33
1nF + 20kΩ
22pF
TO E/A
2µA
CURRENT MODE
PWM CTRL. LOOPS,
LIN. REGULATORS,
DACs ADC, UV/OV
COMPARATORS,
VCO AND PLL,
MOSFET DRIVERS
AND POWER
SWITCH LOGIC
MT1
(PWM1 Telemetry:
READ_DUTY_CYCLE1)
VDD33 VIN1
(Computed Channel 1 Input Current, IVIN1 + 1/2 • ISVIN: MFR_READ_IIN1)
POWER CONTROL
ANALOG SECTION
INT
FILTER
SVIN INTVCC
POWER MANAGEMENT
DIGITAL SECTION
DIGITAL ENGINE, INCLUDING:
ROM, RAM, NVM AND OSCILLATOR
10µA
Channel 0 Internal Loop Compensation
Channel 0 (VOUT0) Voltage Feedback Signal
Channel 0 Current Demand Signal
VORB0–
MB0
MT0
–
VIN0
Power Controller Thermal Sensor
(Telemetry: READ_TEMPERATURE_2)
∆ISNS0a, Channel 0 Current Sense Signal
Channel 0 Thermal Sensor
(Telemetry: READ_TEMPERATURE_10
and MFR_TEMPERATURE_1_PEAK0)
(IOUT0 Telemetry: READ_IOUT0
and MFR_IOUT_PEAK0)
∆VOSNS0, Differential Feedback Signal
ZISNS0a
ZISNS0b
+
ZISNS0b–
– +
VOSNS0+
VORB0+
TSNS0a
TSNS0b
ISNS0a–
ISNS0a
+
ISNS0b+
ISNS0b
GND
VOUT0
SW0
SNUB0
(PWM0 Telemetry:
READ_DUTY_CYCLE0)
(SVIN Telemetry:
READ_VIN and MFR_VIN_PEAK)
(Computed Total Input Current, IVINO + IVIN1 + ISVIN: READ_IIN)
+
CINH
(Computed Channel 0 Input Current, IVIN0 + 1/2 • ISVIN: MFR_READ_IIN0)
+
∆VOSNS0
VOSNS1
∆ISNS0a
∆ISNS1a
SVIN÷39
20
PWM0
PWM1
VIN
5.75V TO 26.5V
(LOAD1 Power Consumption
Telemetry: READ_POUT1)
LOCAL
HIGH
FREQ
MLCCs
Configuration
Resistors Terminating
to SGND Not Shown
4676 FD
LOAD1
COUT1HF
VOUT1
ADJUSTABLE
UP TO 5.4V
UP TO 13A
(VOUT1 Telemetry:
READ_VOUT1 and
MFR_VOUT_PEAK1)
COUT1LF
3.3V Tolerant; Pull-Up
Resistor Not Shown
+
RSNUB1
UP TO
2W
Optional Snubber
Resistor for Moderate
Reduction in Radiated EMI
(Size: EIA0603 ~EIA2512)
LTM4676
Functional Diagram
4676fd
LTM4676
Test Circuits
VIN
5.75V TO 26.5V
+
CINL
150µF
VIN0
VIN1
CINH
10µF
×6
INTVCC
VDD25
SW0
SW1
SNUB0
SNUB1
Test Circuit 1. LTM4676 ATE High VIN Operating Range Configuration, 5.75V ≤ VIN ≤ 26.5V
SVIN
VDD33
SMBus INTERFACE WITH
PMBus COMMAND SET
ON/OFF CONTROL,
FAULT MANAGEMENT AND
POWER SEQUENCING
PWM CLOCK SYNCH
TIME BASE SYNCH
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
WP
LTM4676
+
COUTL0
OPT*
COUTH0 VOUT0
100µF 1V ADJUSTABLE
×4
UP TO 13A
LOAD0
+
COUTL1
OPT*
COMP0a
COMP0b
COMP1a
COMP1b
ASEL
FSWPHCFG
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
GND
(PULL-UP RESISTORS ON DIGITAL
I/O PINS NOT SHOWN)
VOUT0
TSNS0a
TSNS0b
ISNS0a+
ISNS0b+
ISNS0a–
ISNS0b–
VORB0+
VOSNS0+
VOSNS0–
VORB0–
VORB1
VOUT1
TSNS1a
TSNS1b
ISNS1a+
ISNS1b+
ISNS1a–
ISNS1b–
VOSNS1
SGND
VOUT1
COUTH1
1V ADJUSTABLE
100µF
UP TO 13A
×4
LOAD1
4676 TC01
RTH0
30.1k
CTH0
470pF
RTH1
30.1k
CTH1
470pF
*COUTL0, COUTL1 NOT USED IN ATE TESTING
VIN
4.5V TO 5.75V
+
CINL
150µF
VIN0
VIN1
SVIN
VDD33
CINH
10µF
×6
SMBus INTERFACE WITH
PMBus COMMAND SET
ON/OFF CONTROL,
FAULT MANAGEMENT AND
POWER SEQUENCING
PWM CLOCK SYNCH
TIME BASE SYNCH
INTVCC
VDD25
SW0
SW1
SNUB0
SNUB1
Test Circuit 2. LTM4676 ATE Low VIN Operating Range Configuration, 4.5V ≤ VIN ≤ 5.75V
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
WP
LTM4676
COMP0a
COMP0b
COMP1a
COMP1b
ASEL
FSWPHCFG
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
GND
(PULL-UP RESISTORS ON DIGITAL
I/O PINS NOT SHOWN)
VOUT0
TSNS0a
TSNS0b
ISNS0a+
ISNS0b+
ISNS0a–
ISNS0b–
VORB0+
VOSNS0+
VOSNS0–
VORB0–
VORB1
VOUT1
TSNS1a
TSNS1b
ISNS1a+
ISNS1b+
ISNS1a–
ISNS1b–
VOSNS1
SGND
+
COUTL0
OPT*
COUTH0 VOUT0
100µF 1V ADJUSTABLE
×4
UP TO 13A
LOAD0
+
COUTL1
OPT*
VOUT1
COUTH1
1V ADJUSTABLE
100µF
UP TO 13A
×4
LOAD1
4676 TC02
RTH0
30.1k
CTH0
470pF
RTH1
30.1k
CTH1
470pF
*COUTL0, COUTL1 NOT USED IN ATE TESTING
4676fd
For more information www.linear.com/LTM4676
21
LTM4676
Operation
The LTC3880 data sheet is an essential reference document for this product. To obtain it go to:
www.linear.com/LTC3880
Power Module Introduction
The LTM4676 is a highly configurable dual 13A output
standalone nonisolated switching mode step-down
DC/DC power supply with built-in EEPROM NVM (nonvolatile memory) and I2C-based PMBus/SMBus 2-wire
serial communication interface capable of 400kHz SCL
bus speed. Two output voltages can be regulated (VOUT0,
VOUT1—collectively, VOUTn) with a few external input and
output capacitors and pull-up resistors. Readback telemetry
data of average input and output voltages and currents,
Channel PWM duty cycles, and module temperatures are
continually digitized cyclically by an integrated 16-bit ADC
(analog-to-digital converter). Many fault thresholds and
responses are customizable. Data can be autonomously
saved to EEPROM when a fault occurs, and the resulting
fault log can be retrieved over I2C at a later time, for analysis.
The LTM4676 provides precisely regulated output voltages
(±1%) between 0.6VDC to 4VDC (VOUT0) and between
0.6VDC to 5.4VDC (VOUT1). The target output voltage can
be set according to pin-strapping resistors (VOUTn CFG and/
or VTRIMn CFG pins), NVM/register settings, and/or can be
altered on the fly via the I2C interface. The output voltage can
be modified by the user at any time with a write to PMBus
VOUT_COMMAND. Executing this command has a typical
latency less than 10ms. Writes to PMBus OPERATION have
a typical latency less than 1ms. The NVM factory-default
switching frequency is 500kHz and the phase-interleaving
angle between its two channels is 180°. Channel switching
frequency, phase angle, and phase relationship with the
falling edge of the SYNC pin waveform can be configured
according to a pin-strap resistor (FSWPHCFG pin) and NVM/
register settings—though, not on the fly during regulation.
The 7-bit I2C slave address of the module defaults to 0x4F,
but the least significant four bits of the address can be
altered by the presence of the ASEL resistor—yielding 16
possible slave addresses. With the exception of the ASEL
pin, the module can be configured to ignore all pin-strap
resistors, if desired (see MFR_CONFIG_ALL[6]). The slave
address cannot be changed over I2C.
22
The LTM4676 control IC is a slightly modified version of
the LTC®3880; differences between the LTC3880 and the
LTM4676’s control IC are outlined in Table 1 of this data
sheet—in the Applications Information section.
An indexed list of supported PMBus (I2C) and manufacturer-specific transaction command codes, register
map documentation, register-by-register factory-default
settings and the corresponding communication protocols,
payload size and data formats for the LTM4676’s control
IC are provided in the LTC3880 data sheet—again, with
exceptions noted in Table 1 of this data sheet. Therefore,
the LTC3880 data sheet is an essential reference for all
LTM4676 users.
Major features of the LTM4676 strictly from a DC/DC
converter power delivery point of view are as follows:
Up to 13A Output Current Delivery from Each of Two
Integrated Power Stages (See Front Page Figure)—or
Up to 26A Output, Combined (See Figure 35).
n
Wide Input Voltage Range: DC/DC Step-Down Conversion from 5.75V to 26.5V Input (See Figure 44).
n
DC/DC Step-Down Conversion from 4.5V to 5.75V Input,
Connecting SVIN to INTVCC (See Figure 35).
n
DC/DC Step-Down Conversion Possible from Less Than
4.5V Input When an Auxiliary 5V Bias Supply Powers
SVIN and INTVCC (See Figure 37).
n
Output Voltage Range: 0.5V to 4V on VOUT0, 0.5V to
5.4V on VOUT1. (See Figure 42 for Dual Phase Single
5V Output Operation with Reduced Telemetry.)
n
Differential Remote Sensing of VOUT0 (VOSNS0+/
VOSNS0–).
n
Start-Up Into a Pre-Biased Load Without Sinking
Current.
n
Four LTM4676s Can Be Paralleled to Deliver Up to 100A
(See Figure 39).
n
One LTM4676 Can Be Paralleled with Three LTM4620A
or LTM4630 Modules to Deliver Up to 130A; Infer
Rail Status and Telemetry of Paralleled LTM4620A or
LTM4630 via the Sole LTM4676 (See Figure 40.)
n
4676fd
For more information www.linear.com/LTM4676
LTM4676
Operation
Discontinuous Mode and Burst Mode Operation Available for Higher Light-Load Efficiency (MFR_PWM_
MODEn [1:0]).
ing Standalone Operation, if Desired, and Also Enabling
In-Situ Changes to the LTM4676’s Configuration in
Embedded Designs.
n
Output Current Limit and Overvoltage Protection.
n
Three Integrated Temperature Sensors, Over/Undertemperature Protection.
n
Monitoring and Reporting of Telemetry Data: Average
Output and Input Currents and Voltages, Internal Temperatures, and Power Stage Duty Cycles—Continuously
Digitized Cyclically by a 16-Bit ADC.
n
Constant Frequency Peak Current Mode Control.
• Peak Observed Output Current and Voltage, Input
Voltage, and Module Temperatures Can Be Polled
and Cleared/Reset.
n
Configurable Switching Frequency, 250kHz to 1MHz;
Synchronizable to External Clock; Seven Configurable
Channel Phase Interleaving Settings.
n
• ADC Latency Not Greater Than 100ms, Nominal.
Internal Loop Compensation Provided; External Loop
Compensation Can Be Applied, if Preferred.
• Option to Monitor One External Temperature in Lieu of
Channel 1 (VOUT1) Module Power Stage Temperature.
n
Integrated Snubber Capacitors Enable EMI Reduction
by Placing External Snubber Resistors Adjacent to the
Module (see Figures 32 and 33).
n
Monitoring, Reporting, and Configurable Response
to Latching and Non-Latching Individual Fault and/or
Warning Status, Including but Not Limited to:
n
Low Profile (16mm × 16mm × 5.01mm) BGA Package
Power Solution Requires Only Input and Output Capacitors; at Most, Nine Pull-Up Resistors for Open-Drain
Digital Signals; at Most, Six Pull-Down Resistors to
Configure All Possible Pin-Strapping Options.
• Output Over/Undervoltages.
n
• Input (SVIN) Over/Undervoltages.
• Module Input and Power Stage Output Overcurrents.
• Module Power Stage Over/Undertemperatures.
Features of the LTM4676 that enable power system
management, rail sequencing, and fault monitoring and
reporting are as follows:
I2C-based PMBus/SMBus 2-Wire Serial Communication
Interface (SDA, SCL) with ALERT Interrupt Pin, SCL
Clock Capable of 400kHz Bus Communication Speeds
with Clock Low Extending—or 100kHz, Otherwise.
n
Configurable Output Voltage.
n
Configurable Input Undervoltage Comparators
(UVLO Rising, UVLO Falling).
n
Configurable Switching Frequency.
• Internal Control IC Overtemperature.
• Communication, Memory and Logic (CML) Faults.
Fault Logging Upon Detection of a Fault Condition. The
LTM4676 Can Be Configured to Automatically Upload a
Fault Log to Its NVM, Consisting of: an Uptime Counter,
Peak Observed Telemetry, Telemetry Gathered from the
Six Most Recent Rounds of Cyclical ADC Data Leading
Up to the Detection of the Fault That Triggered Fault Log
Writing, and Fault Status Associated with That ADC
History.
n
Two Configurable Open-Drain General Purpose Input/
Output Pins (GPIO0, GPIO1), Which Can Be Used for:
n
n
Configurable Current Limit.
n
Configurable Output Over/Undervoltage Comparators.
• Fault Reporting, e.g., as a System Interrupt Signal.
Configurable Turn-On and Turn-Off Delay Times.
• Coordinating Turn-On/Off of the LTM4676 in Multiphase/Multirail Systems.
n
n
Configurable Output Ramp Rise and Fall Times.
n
Non-Volatile Configuration Memory (NVM EEPROM) to
Configure Aforementioned Settings, and More—Yield-
n
• Propagating an Unfiltered Power Good Signal (Output
of a VOUTn Undervoltage Comparator) to Command
Turn-On/Off of a Downstream Rail.
4676fd
For more information www.linear.com/LTM4676
23
LTM4676
Operation
A Write Protect (WP) Pin and Configurable WRITE_
PROTECT Register to Protect the Internal Configuration
of RAM and NVM Against Unintended Changes via I2C.
n
Time-Base Interconnect (SHARE_CLK, 100kHz Heartbeat) for Synchronization in the Time Domain Between
Multiple LTM4676s.
n
Optional External Configuration Resistors (RCONFIGs)
for Setting Start-Up Output Voltages, Switching Frequency and Channel-to-Channel Phase Interleaving
Angle.
n
16 Supported Slave Addresses (0x4F Default), Configured by Resistor Pin Strapping the ASEL Pin.
n
Power Module Configurability and
Readback Data
This section of the data sheet describes in detail all the
configurable features and readable data of the LTM4676
accessible via I2C. The relevant command code name(s)
are indicated by use of all capital letters, e.g., “VIN_ON”.
Refer to the LTC3880 data sheet and Table 1 of this data
sheet in order to identify the associated command code,
payload size, data format and factory-default value for each
register name of interest. Specific register bits of some
registers are indicated with the use of brackets, i.e., “[”
and “]”. The least significant bit (LSB) of a register is bit
number zero, indicated by “[0]”. The most significant bit
of a byte-long (8-bit-long) register is bit number seven,
indicated by “[7]”. The most significant bit (MSB) of a
word-long (16-bit-long) register is bit number fifteen,
indicated by “[15]”. Multiple bits of a register can be
alluded to with the use of a colon, e.g., bits 2, 1 and
0 of the MFR_PWM_CONFIG register are indicated by
“MFR_PWM_CONFIG[2:0]”. Bits can take on values of 0b
or 1b. The subscripted “b” suffix indicates the number’s
value is in binary. Values in hexadecimal are indicated with
a “0x” prefix. For example, decimal value “89” is indicated
by 0x59 and 01011001b (8-bit-long values), as well as
0x0059 and 0000000001011001b (16-bit-long values).
24
One further shorthand notion the reader will notice is the
italicized “n” or “n”. “n” can take on a value of 0 or 1—and
provides an easy way to refer to registers which are paged
commands, i.e., register names which have the same command code value but can be configured independently (or
yield channel-specific telemetry) for Channel 0 (Page 0,
or 0x00) vs Channel 1 (Page 1, or 0x01). Registers lacking an “n” are therefore easily identified as being global
in nature, i.e., common to both Channels/Outputs. For
example, the switching frequency setting commanded
by register FREQUENCY_SWITCH is common to both
channels, and lacks “n”. Another example: the READ_VIN
register contains the digitized input voltage as seen at
the SVIN pin, and SVIN is unique, i.e., common to both
Channels. In contrast, the nominal commanded output
voltage is indicated by the register VOUT_COMMANDn.
The “n” indicates that VOUT_COMMAND can be set differently for Channel 0 vs Channel 1. Executing the PAGE
Command (Command Code 0x00) with payload 0x00 sets
the LTM4676 to write/read data pertaining to Channel 0 in
all subsequent I2C transactions until the Page is changed.
Executing the PAGE Command with payload 0x01 sets the
LTM4676 to write/read data pertaining to Channel 1 in all
subsequent I2C transactions until the Page is changed.
Executing the PAGE Command with payload 0xFF sets
the LTM4676 to write data pertaining to Channels 0 and 1
in all subsequent I2C write transactions until the Page is
changed. Reads from and writes to global registers do
not require setting the Page to 0xFF. Reads from channelspecific (i.e., non-global) registers when the Page is set to
0xFF result in the LTM4676 reporting the value on Page
0x00 (i.e., Channel 0-specific data).
The list below itemizes aspects of the LTM4676 relating to
power supply functions that are configurable by I2C communications—provided the state of the WP (write protect)
pin and the WRITE_PROTECT register value permit the I2C
writes—and by EEPROM settings:
4676fd
For more information www.linear.com/LTM4676
LTM4676
Operation
Output Start-Up Voltages (VOUT_COMMANDn), the Maximum Commandable Output Voltages (VOUT_MAXn),
Output Voltage Power Good “On” (VOUT_PGOOD_
ONn) and “Off” (POWER_GOOD_OFFn) Thresholds,
Output Margin High (VOUT_MARGIN_HIGHn) and
Margin Low (VOUT_MARGIN_LOW n) Command
Voltages, and Output Over/Undervoltage Warning
and Fault Thresholds (VOUT_OV_WARN_LIMITn,
VOUT_OV_FAULT_LIMITn, VOUT_UV_WARN_LIMITn,
and VOUT_UV_FAULT_LIMITn). Additionally, these
Values Can Be Configured at SVIN Power-Up According to Resistor-Pin Strapping of the VOUT0CFG,
VTRIM0CFG, VOUT1CFG and/or VTRIM1CFG Pins, Provided
MFR_CONFIG_ALL[6] = 0b.
n
Output Voltages, On the Fly, Including Transition Rate
(∆V/∆t), VOUT_TRANSITION_RATEn—Either by I2C
Writes to the VOUT_COMMANDn, VOUT_MARGIN_
HIGHn, or VOUT_MARGIN_LOWn Registers, and/or to the
OPERATIONn Register.
n
Input Undervoltage-Lockout, Rising (VIN_ON) and Input
Undervoltage Lockout, Falling (VIN_OFF), Based on the
SVIN Pin Voltage.
n
Switching Frequency (FREQUENCY_SWITCH) and Channel Phase-Interleaving Angle (MFR_PWM_CONFIG[2:0]).
However, these Parameters Can Be Changed via I2C
Communications Only When the LTM4676’s Channels
are Off, i.e., not Switching. Additionally, These Parameters Can Be Configured at SVIN Power-Up According
to Resistor-Pin Strapping of the FSWPHCFG Pin, Provided
MFR_CONFIG_ALL[6] = 0b.
n
Output Voltage Turn On and Turn Off Sequencing and
Associated Watchdog Timers, Namely:
n
• Output Voltage Turn-On Delay Time (the Time Delay
from the LTM4676 Being Commanded to Turn On,
e.g., by the RUNn Pin Toggling from Logic Low
to High, Before Switching Action Commences.
TON_DELAYn).
• The Amount of Time (TON_MAX_FAULT_LIMITn)
Permitted to Elapse After the LTM4676 is Commanded
to Turn On, e.g., by the RUNn Pin Toggling from Logic
Low to High, After Which, If the Output Voltage Fails
to Exceed the Output Undervoltage Fault Threshold
(VOUT_UV_FAULT_LIMITn), the LTM4676’s Output
(VOUTn) is Declared to Have Not Come Up in a Timely
Manner.
• The LTM4676’s Response to Any Such Aforementioned TON_MAX_FAULT_LIMIT n Event
(TON_MAX_FAULT_RESPONSEn).
• Output Voltage Soft-Stop Ramp-Down Time
(TOFF_FALLn).
• Output Voltage Turn-Off Delay Time (the Time Delay
from the LTM4676 Being Commanded to Turn Off,
e.g., by the RUNn Pin Toggling from Logic High to
Low, Before Switching Action Ceases. TOFF_DELAYn).
• When Commanded to Turn Off it Output—or, When
Turning Off its Output in Response to a Fault—
Configuring Whether the LTM4676's Output (VOUTn)
Becomes High Impedance (“High-Z” or “Three
State”—turning off both MTn and MBn in the Power
Stage). (“Immediate Off”, ON_OFF_CONFIGn[0]
= 1b vs Configuring the Output Voltage to Be
Ramped Down According to TOFF_FALLn and/or
TOFF_DELAYn Settings, ON_OFF_CONFIGn[0] = 0b).
• The Amount of Time (TOFF_MAX_WARN_LIMITn)
Permitted to Elapse After the LTM4676 is Supposed
to Have Turned Off its Output, i.e., at the End of the
Period Dictated by TOFF_FALLn, After Which, If the
Output Voltage Has Not Fallen Below 12.5% of the
Former Target Voltage of Regulation, the LTM4676’s
Output (VOUTn) is Declared to Have Not Powered
Down in a Timely Manner.
• Output Voltage Soft-Start Ramp-Up Time (TON_
RISEn).
4676fd
For more information www.linear.com/LTM4676
25
LTM4676
Operation
Configurable Output Voltage Restart Time. Subsequent
to the RUNn Pin Being Pulled Low, the LTM4676 Pulls
RUNn Logic Low, Itself, and the Output Cannot Be
Restarted Until a Minimum Time Has Elapsed—the
Restart Delay Time. This Delay Assures Proper Sequencing of All System Rails. The Minimum Restart
Delay Processed By the LTM4676 is the Longer of
(TOFF_DELAYn + TOFF_FALLn + 136ms) vs the Commanded MFR_RESTART_DELAYn Register Value. At
the End of This Delay, the LTM4676 Releases its RUNn
Pin.
n
Configurable Fault-Hiccup Retry Delay Time. When a
Fault Occurs in Which the LTM4676’s Fault Response
Behavior to That Fault Is to Reattempt Power-Up of its
Output Voltage After Said Fault Ceases to Be Present
(e.g., “Infinite Retry”), the Delay Time for the LTM4676
to Re-engage Switching Action Is the Longer of the
MFR_RETRY_DELAYn Time vs the Time Required for
the Output to Decay Below 12.5% of the Formerly Commanded Output Voltage Value (Unless This Lattermost
Criteria, i.e., Requiring the Output to Decay Below 12.5%
Is Negated By the Setting of MFR_CHAN_CONFIGn [0]
to “1b”—Which is the LTM4676’s Factory-NVM Default
Setting).
n
Output Over/Undervoltage Fault Responses (VOUT_OV_
FAULT_RESPONSEn, VOUT_UV_FAULT_RESPONSEn).
n
Time-Averaged Current Limit Warning and Instantaneous Peak (Cycle-by-Cycle) Fault Thresholds, and
Fault Response (IOUT_OC_WARN_LIMITn, IOUT_OC_
FAULT_LIMITn, IOUT_OC_FAULT_RESPONSEn).
n
Channel (VOUT0, VOUT1) Overtemperature Warning and
Fault Thresholds, and Fault Response (OT_WARN_
LIMITn, OT_FAULT_LIMITn, OT_FAULT_RESPONSEn).
n
Channel (V OUT0, VOUT1) Undertemperature Fault
Thresholds and Fault Response (UT_FAULT_LIMITn,
UT_FAULT_RESPONSEn).
n
Input Overvoltage Fault Threshold and Response
(VIN_OV_FAULT_LIMIT, VIN_OV_FAULT_RESPONSE),
Based on the SVIN Pin Voltage.
n
Input Undervoltage Warning Threshold (VIN_UV_
WARN_LIMIT) Based on the SVIN Pin Voltage.
n
26
Module Input Overcurrent Warning Threshold
(IIN_OC_WARN_LIMIT)
n
The control IC within the LTM4676 module ceases
switching action if control IC temperature exceeds 160°C
(Note 12). The control IC resumes operation after a 10°C
cool-down hysteresis. Note that these typical parameters
are based on measurements in a lab oven and are not
production tested. This overtemperature protection is
intended to protect the device during momentary overload
conditions. The maximum rated junction temperature will
be exceeded when this protection is active. Continuous
operation above the specified absolute maximum operating junction temperature may impair device reliability or
permanently damage the device.
Time-Averaged and Peak Readback Data
Time-averaged telemetry readback data accessible via I2C
communications follow:
Channel Output Current (READ_IOUTn) and Peak Observed Value of READ_IOUTn (MFR_IOUT_PEAKn).
n
Channel Output Voltage (READ_VOUTn) and Peak Observed Value of READ_VOUTn (MFR_VOUT_PEAKn).
n
Channel Output Power (READ_POUTn).
n
Channel Input Current (MFR_READ_IINn) and Module
Input Current (READ_IIN).
n
Channel Temperatures (READ_TEMPERATURE_1n) and
Peak Observed Values of READ_TEMPERATURE_1n
(MFR_TEMPERATURE_1_PEAKn).
n
Control IC Temperature (READ_TEMPERATURE_2) and
Peak Observed Value (MFR_TEMPERATURE_2_PEAK).
n
Input Voltage (READ_VIN), Based on the Voltage of
the SVIN Pin, and Peak Observed Value of READ_VIN
(MFR_VIN_PEAK).
n
Channel Topside Power MOSFET (MTn) Duty Cycle
(READ_DUTY_CYCLEn)
n
Peak observed values of telemetry readback data can
be cleared with the MFR_CLEAR_PEAKS I2C command,
provided the WRITE_PROTECT register value permits it.
(Executing MFR_CLEAR_PEAKS can be performed regardless of the state of the WP pin.)
4676fd
For more information www.linear.com/LTM4676
LTM4676
Operation
Details on the LTM4676’s Fault Log Feature follow:
Fault Logging is Enabled When MFR_CONFIG_ALL[7] = 1b.
n
A Fault Log is Present in NVM When STATUS_MFR_
SPECIFICn [3]Reports “1b”, Which Is Propagated to the
MFR Bit (Bit 12) of the STATUS_WORD Register.
n
Retrieving Fault Log Data, if Present, Is Performed with
the MFR_FAULT_LOG Command. 147 Bytes of Data
are Retrieved Using the PMBus-Defined Variant to the
SMBus Block Read Protocol.
n
The Fault Log Contents in NVM, if Present, Are Cleared
By Executing the MFR_FAULT_LOG_CLEAR Command.
n
The Fault Log Will Not Be Written if a Fault Log Is Already
Present in NVM.
n
The LTM4676 Can Be Forced to Write a Fault Log to
Its NVM by Executing the MFR_FAULT_LOG_STORE
Command; the LTM4676 Will Behave as if a Channel
Faulted Off. Note the command is NACKed and a CML
fault is reported if a Fault Log is already present at the
time of executing MFR_FAULT_LOG_STORE.
n
When an external stimulus pulls the LTM4676’s GPIOn
pin(s) logic low, the respective channel (VOUTn) either:
takes no action on it, i.e., ignores it completely—
if MFR_GPIO_RESPONSEn = 0x00; or, turns off immediately,
i.e., the power stage(s) become high impedance (“inhibited”)—
if MFR_GPIO_RESPONSEn = 0xC0.
The MFR_GPIO_PROPAGATEn register contents configure
which fault(s) cause the LTM4676 to pull its GPIOn pin(s)
logic low.
I2C communications are originated by the user’s (system’s)
I2C master device. Writes/reads to/from Channel 0 of the
LTM4676 (VOUT0: PAGE 0x00), to/from Channel 1 of the
LTM4676 (VOUT1: PAGE 0x01), or writes to both Channels
0 and 1 of the LTM4676 (VOUT0 and VOUT1: PAGE 0xFF)
are possible. The target channel(s) of interest are selected
by the I2C master by executing the PAGE command and
sending the appropriate argument (0x00, 0x01, 0xFF)
in the payload. The PAGE command is unrestricted, i.e.,
not affected by the WP pin or WRITE_PROTECT register
settings.
The LTM4676 always responds to its global slave addresses, 0x5A and 0x5B. Commands sent to the global
address 0x5A act the same as if the PAGE command were
set to 0xFF, i.e., received commands are written to both
channels simultaneously. Commands sent to the global
address 0x5B are applied to the PAGE active at the time of
the global address transaction, i.e., allows channel-specific
command of all LTM4676 devices on the bus.
I2C commands not listed above that relate to Fault Status
and EEPROM NVM Operations follow. Writing of the following is possible provided the state of the WP (write
protect) pin and the WRITE_PROTECT register value
permits the I²C writes:
Soliciting (Reading) Module Fault Status and
Clearing (Writing) Module Fault Status (CLEAR_
FAULTS, STATUS_BYTEn, STATUS_WORDn, STATUS_
VOUTn, STATUS_IOUTn, STATUS_INPUT, STATUS_
TEMPERATUREn, STATUS_CML [Communications,
Memory, and/or Logic], and STATUS_MFR_SPECIFICn
[Miscellaneous]).
n
Storing the LTM4676’s User-Writable RAM Register
Data to the EEPROM NVM (STORE_USER_ALL).
n
An Alternate Means to the STORE_USER_ALL Command
to Directly Erase and Write the LTM4676’s EEPROM
Contents, Protected by Unlock Keys, to Facilitate Programming of the LTM4676 EEPROM in Environments
Such as ICT (In-Circuit Test) and Bulk Programming
by, e.g., Embedded Hardware or by the LTpowerPlay
GUI. Also, a Means to Directly Read the LTM4676 EEPROM Contents (MFR_EE_UNLOCK, MFR_EE_ERASE,
MFR_EE_DATA).
n
Instigating a Soft Reset of the LTM4676 without PowerCycling SVIN Power (MFR_RESET). The MFR_RESET
Command Triggers the Download of EEPROM NVM Data
to RAM Registers, as if SVIN Power had been cycled.
n
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27
LTM4676
Operation
Other data that can be obtained from the LTM4676 via I2C
communications are as follows:
Soliciting the LTM4676 for its PMBus Capabilities, as
Defined by PMBus (CAPABILITY):
n
• PEC (Packet Error Checking). Note, the LTM4676
Requires Valid PEC in I2C Communications when
MFR_CONFIG_ALL[2] = 1b. The NVM Factory-Default
Configuration is MFR_CONFIG_ALL[2] = 0b, i.e., PEC
Not Required.
• I2C Communications Can Be Supported at Up to
400kHz SCL Bus Speed. Note, Clock Low Extending (Clock Stretching) Must Be Enabled On the
LTM4676 to Ensure Robust Communications Above
100kHz SCL Bus Speeds, i.e., MFR_CONFIG_ALL[1]
= 1b. The NVM Factory-Default Configuration is
MFR_CONFIG_ALL[1] = 0b, i.e. Clock Stretching is
Disabled.
• The LTM4676 Has an SMBALERT (ALERT) Pin and
Does Support the SMBus ARA (Alert Response Address) Protocol.
Soliciting the Module for the Maximum Output Voltage
It Can Be Commanded to Produce (MFR_VOUT_MAXn).
n
Soliciting the Device for the Data Format of Its Output
Voltage-Related Registers (VOUT_MODEn).
n
Soliciting the Device for the Revisions of PMBus Specifications That It Supports (Part I: Rev. 1.1; Part II: Rev 1.1).
n
Soliciting the Device for the Identification of the
Manufacturer of the LTM4676, “LTC” (MFR_ID) and
the Manufacturer Code Representing the LTM4676 and
Revision, 0x448X or 0x440X (MFR_SPECIAL_ID).
n
Soliciting the Device for Its Part Number, “LTM4676”
(MFR_MODEL).
n
Soliciting the Module for Its Serial Number
(MFR_SERIAL).
n
The Digital Status of the LTM4676’s I/O Pads and
Validity of the ADC (MFR_PADS) and WP Pin Status
(MFR_COMMON[0]).
n
28
The following list indicates other aspects of the LTM4676
relating to power system management and power sequencing that are configurable by I2C communications—
provided the state of the WP (write protect) pin and the
WRITE_PROTECT register value permit the I2C writes—and
by EEPROM settings:
Providing Multiple Means to Read/Write Data Directly
to a Particular Channel of the LTM4676 By Assigning Additional Slave Address for Channels 0 and 1
(MFR_CHANNEL_ADDRESSn, MFR_RAIL_ADDRESSn),
the Benefit of Which Is That It Reduces Page Command
Usage and Associated I2C Traffic. It Also Facilitates
Altering the Same Register of Multiple LTM4676 in
Unison without Invoking the PMBus Group Command
Protocol.
n
Configuring the Output Voltage to Be On or Off by
Means Other Than the RUNn Pin (ON_OFF_CONFIGn [3],
OPERATION commands)
n
Configuring Whether the LTM4676 Masks PLL (PhaseLocked Loop) Out-of-Lock Faults. (MFR_CONFIG_
ALL[3]).
n
Configuring Whether the LTM4676 Performs a
CLEAR_FAULTS Command Upon Itself When Either
RUNn Pin Toggles from Logic Low to Logic High.
(MFR_CONFIG_ALL[0]).
n
Configuring Whether the LTM4676 Pulls RUNn Logic
Low When the LTM4676 is Commanded Off By Other
Means (MFR_CHAN_CONFIGn[4]).
n
Configuring the Response of the LTM4676 When It Is
Commanded to Turn On Its Output Prior to the Completion
of Processing TOFF_DELAYn and TOFF_FALLn PowerDown Sequencing (MFR_CHAN_CONFIGn[3]).
n
Configuring Whether the LTM4676’s Output Is
Disabled When SHARE_CLK Is Held Low (MFR_CHAN_
CONFIGn[2]).
n
Configuring Whether the ALERT Pin is Pulled Low
When GPIOn Is Pulled Low by External Stimulus
(MFR_CHAN_CONFIGn[1]).
n
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LTM4676
Operation
Setting the Value of the MFR_IIN_OFFSETn Registers,
Representing an Estimate of the Current Drawn by the
SVIN Pin. The SVIN Pin Current Is Not Measured by
the LTM4676 but the MFR_IIN_OFFSETn Is Used in
Computing and Reporting Channel and Total Module
Input Currents (MFR_READ_IINn, READ_IIN).
n
Three Words (Six Bytes) of the LTM4676’s EEPROM That
Are Available for Storing User Data. (USER_DATA_03n,
USER_DATA_04).
n
n
Invoking or Releasing Several Levels of I2C Write Pro-
tection (WRITE_PROTECT).
Configuring Whether the LTM4676’s Current Limit
Range is Set to High Range vs Low Range. (MFR_PWM_
MODEn[7]. Not Recommended to Alter This Parameter
from its NVM-Factory Default Settings).
n
Remaining LTM4676 status that can be queried over I2C
communications follow:
Access to Three “Hand-Shaking” Status Bits
(MFR_COMMON[6:4]) to Ease Implementation of
PMBus Busy Protocols, i.e., Enabling Fast and Robust
System Level Communication Through Polling of These
Bits to Infer LTM4676’s Readiness to Act on Subsequent
I2C Writes. (See PMBus Communication and Command
Processing, in the Applications Information Section.)
n
Determining Whether the User-Editable RAM Register
Values Are Identical to the Contents of the User NVM
(MFR_COMPARE_USER_ALL).
n
Setting the Programmable Output Voltage Range of
VOUT to a Narrower Range (0.5V to 2.75V) in Order to
Achieve a Higher Resolution of VOUT Adjustment Than
Is Available by Default (MFR_PWM_CONFIG[6:5]).
MFR_PWM_CONFIG Cannot Be Changed On the Fly;
Switching Action Must Be Off. Note that Altering the
VOUT Range Alters the Gain of the Control Loop and May
Therefore Require Loop Compensation to Be Adjusted.
n
Altering the Temperature Coefficient of the LTM4676’s
Current Sensing Elements, if Needed (MFR_IOUT_CAL_
GAIN_TCn) (Uncommon to Alter This Parameter from
its NVM-Factory Default Setting).
n
Altering the Gain or Offset of the Power Stage Sensors
(MFR_TEMP_1_GAINn and MFR_TEMP_1_OFFSETn)—
or That of the External Temperature Sensor, When an
External Temperature Sensor Is Used On the TSNS1a
Pin. (Uncommon to Alter This Parameter from its NVMFactory Default Setting).
n
Configuring Whether the LTM4676 Pulls SHARE_CLK
Logic Low When SVIN Has Fallen Outside Its UVLO
Thresholds (MFR_PWM_CONFIG[4]). MFR_PWM_
CONFIG Cannot Be Changed On the Fly; Switching Action
Must Be Off (Uncommon to Alter This Parameter from
its NVM-Factory Default Setting).
n
Configuring Whether the LTM4676’s Output Voltage
Digital Servos Are Active vs Disengaged (MFR_PWM_
MODEn[6]. Uncommon to Alter This Parameter from
its NVM-Factory Default Settings).
n
Providing a Means to Determine Whether the LTM4676
NVM Download to RAM Has Occurred (“NVM Initialized”, MFR_COMMON[3]).
n
Providing a Means Other Than ARA Protocol to Determine Whether the LTM4676 is Pulling ALERT Low
(MFR_COMMON[7]).
n
D e t e c t i n g a S H A R E _ C L K Ti m e o u t E v e n t
(MFR_COMMON[1]).
n
Verifying the Slave Address of the LTM4676
(MFR_ADDRESS).
n
Power Module Overview
A dedicated remote-sense amplifier precisely kelvinsenses VOUT0’s load via the differential pin-pair formed
by VOSNS0+ and VOSNS0–. VOUT0 can be commanded to
between 0.5VDC and 4.0VDC. VOUT1 is sensed via the pinpair formed by VOSNS1 and signal ground of the module’s
internal control IC, SGND. VOUT1 can be commanded to
between 0.5VDC and 5.4VDC. Output voltage readback
telemetry is available over I2C (READ_VOUTn registers).
Peak output voltage readback telemetry is accessible
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29
LTM4676
Operation
in the MFR_READ_VOUT_PEAKn registers. If VOSNS0–
exceeds VOSNS+, no phase reversal of the differentiallysensed output voltage feedback signal occurs (Note 12).
Similarly, no phase reversal occurs when SGND exceeds
VOSNS1(Note 12).
The typical application schematic is shown in Figure 44
on the back page of this data sheet.
The LTM4676 can operate from input voltages between
5.75V and 26.5V (see front page figure). In this configuration, INTVCC MOSFET driver and control IC bias is
generated internally by an LDO fed from SVIN to produce
5V at up to 100mA peak output current. Additional internal LDOs—3.3V (VDD33), derived from INTVCC, and 2.5V
(VDD25), derived from VDD33—bias the LTM4676’s digital
circuitry. When INTVCC is connected to SVIN, the LTM4676
can operate from input voltages between 4.5V and 5.75V
(see Figure 35). Control IC bias (SVIN) is routed independent of the inputs to the power stages (VIN0, VIN1); this
enables step-down DC/DC conversion from less than 4.5V
input (see Figure 37), so long as auxiliary power (4.5V
~ 26.5V) is available to bias the control IC appropriately.
Furthermore, the inputs of the two power stages are not
connected together internal to the module; therefore, DC/
DC step-down conversion from two different source power
supplies can be performed.
NVM to implement settings not available by resistor-pin
strapping.) When a FSWPHCFG pin-strap resistor sets the
channel phase relationship of the LTM4676’s channels, the
SYNC clock is not driven by the module; instead, SYNC
becomes strictly a high impedance input and channel
switching frequency is then synchronized to SYNC provided
by an externally-generated clock or sibling LTM4676 with
pull-up resistor to VDD33. Switching frequency and phase
relationship can be altered via the I2C interface, but only
when switching action is off, i.e., when the module is not
regulating either output. See the Applications Information
section for details.
Per Note 6 of the Electrical Characteristics section, the
output current may require derating for some operating
scenarios. Detailed derating guidance is provided in the
Applications Information section.
Internal feedback loop compensation for Regulator 0 is
available by connecting COMP0a to COMP0b. (For Regulator 1, the connection is from COMP1a to COMP1b.) With
current mode control and internal feedback loop compensation, the LTM4676 module has sufficient stability
margins and good transient performance with a wide
range of output capacitors—even all-ceramic MLCCs.
Table 20 provides guidance on input and output capacitors
recommended for many common operating conditions.
The Linear Technology µModule Power Design Tool is
available for transient and stability analysis. Furthermore,
expert users who prefer to not make use of the module’s
internal feedback loop compensation—but instead, tailor
the feedback loop compensation specifically for his/her
application—may do so by not connecting COMPn a to
COMPn b: the personalized loop compensation network
can be applied externally, i.e., from COMPn a to SGND,
and leaving COMPn b open circuit.
The LTM4676 contains dual integrated constant frequency
current mode control buck regulators (Channel 0 and
Channel 1) whose built-in power MOSFETs are capable of
fast switching speed. The factory NVM-default switching
frequency clocks SYNC at 500kHz, to which the regulators synchronize their switching frequency. The default
phase-interleaving angle between the channels is 180°.
A pin-strapping resistor on FSWPHCFG configures the frequency of the SYNC clock (switching frequency) and the
channel phase relationship of the channels to each other
and with respect to the falling edge of the SYNC signal.
(Not all possible combinations of switching frequency
and phase-angle assignments are settable by resistor
pin programming; see Table 4. Configure the LTM4676’s
The LTM4676 has two general purpose input/output pins,
named GPIO0 and GPIO1. The behavior of these pins is
configurable via registers MFR_GPIO_PROPAGATEn
and MFR_GPIO_RESPONSEn. The GPIOn pins are high
impedance during NVM-download-to-RAM initialization.
These pins are intended to perform one of two primary
functions, or a hybrid of the two: behave as open- drain,
active low fault/warning indicators; and/or, behave as auxiliary RUN pins for their respective VOUTs. In the former
case, the pins can be configured as interrupt pins, pulling
active low when output under/overvoltage, input under/
overvoltage, input/output overcurrent, overtemperature,
and/or communication, memory or logic (CML) fault or
warning events are detected by the LTM4676. Factory
30
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LTM4676
Operation
NVM-default settings configure the LTM4676 for the latter
case, enabling the GPIOn to be bussed to paralleled siblings
(paralleled LTM4676 channels and/or modules), for purposes of coordinating orderly power-up and power-down,
i.e., in unison. The LTM4676 DC/DC regulator does not
feature a traditional “power good” (PGOOD) indicator pin
to indicate when the output voltage is within a few percent
of the target regulation point. However, the GPIOn pin can
be configured as a PGOOD indicator. If used for eventbased sequencing of downstream rails, configure GPIOn
as the unfiltered output of the VOUT_UV_FAULT_LIMITn
comparator, setting Bit 12 of MFR_GPIO_PROPAGATEn to
“1b”; do not set Bits 9 and 10 of MFR_GPIO_PROPAGATEn
for this purpose, since the propagation of power good in
those latter instances is subject to the ADC’s latency of up
to 100ms, nominal. If it is necessary to have the desired
PGOOD polarity appear on the GPIOn pin immediately
upon SVIN power-up—given that the pin will initially be
high impedance, until NVM contents have downloaded
to RAM—a pull-down Schottky diode is needed between
the RUNn pin of the LTM4676 and the respective GPIOn
pin. (See Figure 2.) If the GPIOn pin is configured as a
PGOOD indicator, the MFR_GPIO_RESPONSEn must be
set to “ignore” (0x00), or else the LTM4676 cannot start
up due to the latch-off conditions imposed.
Voltage Based Sequencing by Cascading GPIOn Pins Into RUNn Pins
(MFR_GPIO_PROPAGATE = XXX1X00XX00XXXXXb and MFR_GPIO_RESPONSE = 0x00)
*
START
GPIO0 = VOUT0_UVUF
RUN0
LTM4676
RUN1
GPIO1 = VOUT1_UVUF
*
*
RUN0
GPIO0 = VOUT0_UVUF
LTM4676
GPIO1 = VOUT1_UVUF
RUN1
*
4676 F02
TO NEXT CHANNEL
IN THE SEQUENCE
NOTE: RESISTOR OR RC PULL-UPS ON RUNn AND GPIOn PINS NOT SHOWN
*OPTIONAL SIGNAL SCHOTTKY DIODE. ONLY NEEDED WHEN ACCURATE PGOOD
(POWER GOOD) INDICATION IS REQURED BY THE SYSTEM/USER IMMEDIATELY
AT SVIN POWER UP
The RUNn pin is a bidirectional open-drain pin. This means
it should never be driven logic high from a low impedance
source. Instead, simply provide a 10k pull-up resistor from
the RUNn pins to VDD33. The LTM4676 pulls its RUNn pin
logic low during NVM-download-to-RAM initialization,
when SVIN is below the commanded undervoltage lockout voltage (VIN_ON, rising and VIN_OFF, falling), and
subsequent to external stimulus pulling RUN low—for
a minimum time dictated by MFR_RESTART_DELAYn.
Bussing the respective RUNn and GPIOn pins to sibling
LTM4676 modules enables coordinated power-up/powerdown to be well orchestrated, i.e., performing turn-on and
turn-off in a unified fashion.
When RUNn exceeds 2V, the LTM4676 initially idles for
a time dictated by the TON_DELAYn register. After the
TON_DELAYn time expires, the module begins ramping
up the respective control loop’s internal reference, starting
from 0V. In the absence of a pre-biased VOUTn condition,
the output voltage is ramped linearly from 0V to the commanded target voltage, with a ramp-up time dictated by the
TON_RISEn register. In the presence of a pre-biased VOUTn
condition, the output voltage is brought into regulation in
the same manner as aforementioned, with the exception
that inductor current is prevented from going negative (the
module’s controller is operated in discontinuous mode operation during start-up). In both cases, the output voltage
reaches regulation in a consistent time, as measured with
respect to RUNn toggling high. See start-up oscilloscope
shots in the Typical Performance Characteristics section.
Pulling the RUNn pin below 1.4V turns off the DC/DC converter, i.e., forces the respective regulator into a shutdown
state. Factory NVM-default settings configure the LTM4676
to turn off its power stage MOSFETs immediately, thereby
becoming high impedance. The output voltage then decays according to whatever output capacitance and load
impedance is present. Alternatively, NVM/register settings
can configure the LTM4676 to actively discharge VOUTn
when RUNn is pulled logic low, according to prescribed
TOFF_DELAYn delay and TOFF_FALLn ramp-down times.
See the Applications Information section for details. The
LTM4676 does not feature an explicit, analog TRACK pin.
Rail-to-rail tracking and sequencing is handled digitally,
as explained previously.
Figure 2. Event (Voltage) Based Sequencing
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31
LTM4676
Operation
Bussing the open-drain SHARE_CLK pins of all LTM4676s
(and providing a pull-up resistor to VDD33) provides a
means for all LTM4676s in the system to synchronize
their time-base (or “heartbeat”) to the fastest SHARE_CLK
clock. Sharing the heartbeat amongst all LTM4676 ensures
that all rails are sequenced according to expectations; it
negates timing errors that could otherwise materialize
due to SHARE_CLK (time-base) tolerance and part-topart variation.
Electrically connect adjacent pins ISNS0a+ to ISNS0b+; ISNS0a–
to ISNS0b–; ISNS1a+ to ISNS1b+; and ISNS1a– to ISNS01b–.
Current sense information is derived from across the
power inductors (ISNSnb+/ISNSn b– pin-pairs) internal to the
LTM4676 and made available to the internal control IC’s
current control loops and ADC sensors (ISNSn a+/ISNSn a–) by
the aforementioned connections. Output current readback
telemetry is available over I2C (READ_IOUTn registers).
Peak output current readback telemetry is available in the
MFR_READ_IOUT_PEAKn registers.
Output power readback is computed by the LTM4676
according to:
READ_POUTn = READ_VOUTn • READ_IOUTn
Alternating excitation currents of 2µA and 30µA are sourced
from each of the TSNS0a and TSNS1a pins. Connecting
TSNS0a to TSNS0b, and then TSNS1a to TSNS1b, temperature sensing of the Channel 0 and Channel 1 power
stages is realized by the LTM4676 digitizing the voltages
that appear at the PNP transistor temperature sensors
that reside at pins TSNS0b and TSNS1b, respectively.
The LTM4676 performs what is known in the industry
as delta VBE (∆VBE) computations and makes channel
(power stage) temperature telemetry available over I2C
(READ_TEMPERATURE_1n). The junction temperature
of the control IC within the LTM4676 is also available
over I2C (READ_TEMPERATURE_2). Observed peak
Channel temperatures can be read back in registers
READ_MFR_TEMPERATURE_1_PEAKn. Observed peak
temperature of the control IC can be read back in register
MFR_READ_TEMPERATURE_2_PEAK.
For a fixed load current, the amplitude of the current
sense information changes over temperature due to the
32
temperature coefficient of copper (inductor DCR), which is
approximately 3900ppm/°C. This would introduce significant current readback error over the operating range of the
module if not for the fact that the LTM4676’s temperature
readback information is used in conjunction with the perceived current sense signal to yield temperature-corrected
current readback data.
If desired, it is possible to use only the temperature
readback information derived from the TSNS0a/TSNS0b
pins to yield temperature-corrected current readback data
for both Channels 0 and 1. This frees up the Channel 1
temperature sensor to monitor a temperature sensor
external to the LTM4676. This is achieved by setting
MFR_PWM_MODE0[4] = 1b (the NVM-factory default
value is 0b). This degrades the current readback accuracy
of Channel 1—more so when Channel 0 and Channel
1 are not paralleled outputs. However, the TSNS1a pin
becomes available to be connected to an external diodeconnected small-signal PNP transistor (such as 2N3906)
and 10nF X7R capacitor, i.e., an external temperature
sensor, whose temperature readback data and peak
value are available over I2C (READ_TEMPERATURE_11,
MFR_READ_TEMPERATURE_1_PEAK1). Details on how
to connect an external temperature sensor and 10nF
capacitor to the TSNS1a pin are detailed in the LTC3880
data sheet (the TSNS1a pin of the LTM4676 is the TSNS1
pin of LTM4676’s internal control IC).
Power stage duty cycle readback telemetry is available over
I2C (READ_DUTY_CYCLEn registers). Computed channel
input current readback is computed by the LTM4676 as:
MFR_READ_IINn = READ_DUTY_CYCLEn • READ_IOUTn
+ MFR_IIN_OFFSETn
Computed module input current readback is computed
by the LTM4676 as:
READ_IIN = MFR _READ_IIN0 +MFR _READ_IIN1
where MFR_IIN_OFFSETn is a register value representing the SVIN input bias current. The SVIN current is not
digitized by the module. The factory NVM-default value of
MFR_IIN_OFFSETn is 30.5mA, representing the contribution of current drawn by each of the module’s channels
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LTM4676
Operation
on the SVIN pin, when the power stages are operating in
forced continuous mode at the factory-default switching
frequency of 500kHz. See Table 8 in the Applications Information section for recommended MFR_IIN_OFFSETn
setting vs Switching Frequency. The aforementioned
method by which input current is calculated yields an accurate current readback value even at light load currents,
but only as long as the module is configured for forced
continuous operation (NVM-factory default). SVIN and
peak SVIN readback telemetry is accessible via I2C in the
READ_VIN and MFR_VIN_PEAK registers, respectively.
The power stage switch nodes are brought out on the SWn
pin for functional operation monitoring and for optional
installation of a resistor-capacitor snubber circuit (terminated to GND) for reduced EMI. Internal 2.2nF snubber
capacitors connected directly to the switch nodes further
facilitate implementation of a snubber network, if desired.
See the Application Information section for details.
The LTM4676 features a write protect (WP) pin. If WP is
open circuit or logic high, I2C writes are severely restricted:
only I2C writes to the PAGE, OPERATION, CLEAR_FAULTS,
MFR_CLEAR_PEAKS, and MFR_EE_UNLOCK commands
are supported, with the exception that individual fault bits
can be cleared by writing a “1b” to the respective bits in the
STATUS_* registers. Register reads are never restricted.
Not to be confused with the WP pin, the LTM4676 features
a WRITE_PROTECT register, which is also used to restrict
I2C writes to register contents. Refer to the LTC3880 data
sheet for details. The WP pin and the WRITE_PROTECT
register provide a level of protection against accidental
changes to RAM and EEPROM contents.
The LTM4676 supports up to 16 possible slave addresses.
The factory NVM-default slave address is 0x4F. The lower
four bits of the LTM4676’s slave address can be altered
from this default value by connecting a resistor from this
pin to SGND. See Table 5 in the Applications Information
section for details.
Up to four LTM4676 modules (8 channels) can be paralleled, suitable for powering ~100A loads such as CPUs
and GPUs. (See Figure 39.) The LTM4676 can be paralleled with LTM4620A or LTM4630 modules, as well (see
Figures 40 and 41).
EEPROM
The LTM4676’s control IC contains an internal EEPROM
(non-volatile memory, NVM) to store configuration settings and fault log information. EEPROM endurance retention and mass write operation time are specified in the
Electrical Characteristics and Absolute Maximum Ratings
sections. Write operations at TJ < 0°C or at TJ > 85°C are
possible although the Electrical Characteristics are not
guaranteed and the EEPROM retention characteristics
may be degraded. Read operations performed at junction
temperatures between –40°C and 125°C do not degrade
the EEPROM. The fault logging function, which is useful
in debugging system problems that may occur at high
temperatures, only writes to fault log-specific EEPROM
locations (partitions). If occasional writes to these registers occur above 85°C junction, the slight degradation in
the data retention characteristics of the fault log does not
undermine the usefulness of the function.
It is recommended that the EEPROM not be written when
the control IC die temperature is greater than 85°C. If the
die temperature exceeds 130°C, the LTM4676’s control
IC disables all EEPROM write operations. EEPROM write
operations are subsequently re-enabled when the die
temperature drops below 125°C.
Additional Information
An even more detailed account of the operation of the
LTM4676’s internal control IC can be perused in the LTC3880
data sheet. Be reminded of the differences between the
LTM4676’s control IC and the LTC3880, per Table 1.
Operational topics discussed in the LTC3880 data sheet
not covered here—but are equally applicable to the
LTM4676—follow:
Bus Timeout Failure.
n
Similarities Between PMBus, SMBus, and I2C 2-Wire
Interface.
n
The PMBus Serial Digital Interface and Timing Diagrams.
n
PMBus Data Format Terminology.
n
Protocols for Reading/Writing to PMBus Registers of
the LTM4676/LTC3880 Control ICs, Over I2C/SMBus.
n
4676fd
For more information www.linear.com/LTM4676
33
LTM4676
Applications Information
The LTC3880 data sheet is an essential reference document for this product. To obtain it go to:
Note that up to nine pull-up resistors are required for
proper operation of the LTM4676:
www.linear.com/LTC3880
• Three for the SMBus/I2C interface (the SCL, SDA, and
ALERT pins); two, only if the system SMBus host does
not make use of the ALERT interrupt.
LTM4676 Control IC Differences from LTC3880
The LTM4676 control IC is a slightly modified version of
the LTC3880; differences between the LTC3880 and the
LTM4676’s control IC are summarized in Table 1. As such,
it should stand to reason that the LTC3880 data sheet is
a valuable reference document for the LTM4676 user, especially for newcomers to the PMBus suite of commands/
command codes (registers) and working with I2C/SMBus
2-wire interface.
Apart from exceptions noted in Table 1, the PMBus commands codes (registers) supported by the LTM4676 are
identical in scope and data format to that of the LTC3880’s.
Refer to LTC3880’s PMBus Command Summary and
PMBus Command Details data sheet sections for detailed
information on the supported command codes.
Note that the LTC3880 RCONFIG (resistor pin-strappable)
pins require resistor networks from VDD25 to SGND,
whereas the LTM4676 integrates the “top” resistors and
therefore only requires pull-down (termination) resistors
to SGND. As a result, the resistor pin-strap tables for
the LTM4676 differ from the LTC3880. Additionally, the
LTM4676’s FSWPHCFG pin-strap options have been slightly
modified compared to LTC3880’s FREQ_CFG pin-strap
options. Refer to Tables 2 to 5 in this data sheet for details.
The typical LTM4676 application circuit is shown in
Figure 44 on the back page of this data sheet.
External capacitor selection is primarily determined by
the maximum load current and output voltage. Refer to
Table 20 for specific external capacitor requirements for
particular applications.
34
• One each for the RUN0 and RUN1 pins (or, just one to
RUN0 and RUN1, if RUN0 and RUN1 are electrically
connected together).
• One each for GPIO0 and GPIO1 (or, just one to GPIO0 and
GPIO1, if GPIO0 and GPIO1 are electrically connected
together).
• One on SHARE_CLK, required, for the LTM4676 to
establish a heartbeat time base for timing-related operations and functions (output voltage ramp-up timing,
voltage margining transition timing, SYNC open-drain
drive frequency).
• One on SYNC, in order for the LTM4676 to phase lock
to the frequency generated by the open-drain output
of its digital engine. EXCEPTION: in some applications,
it is desirable to drive the LTM4676’s SYNC pin with
a hard-driven (low impedance) external clock. This is
the only scenario where the LTM4676 does not require
a pull-up resistor on SYNC. However, be aware that
the SYNC pin can be low impedance during NVM initialization, i.e., during download of EEPROM contents
to RAM (for ~50ms [Note 12] after SVIN power is applied). Therefore, the hard-driven clock signal should
only be applied to the LTM4676 SYNC pin through a
series resistor whose impedance limits current into the
SYNC pin during NVM initialization to less than 10mA.
Furthermore, any clock signal should be provided prior
to the RUNn pins toggle from logic low to logic high, or
else the switching frequency of the LTM4676 will start
off at the low end of its PLL-capture range (~225kHz)
until the SYNC clock becomes established.
4676fd
For more information www.linear.com/LTM4676
LTM4676
Applications Information
Table 1. Summary of Supported Commands and Differences Between the LTM4676’s Control IC and the LTC3880 (Items of Greatest
Significance Indicated by Gray-Shaded Cells; Common Commands, Values and Attributes Indicated by Non-Shaded, Merged Cells)
PMBus COMMAND
NAME, OR FEATURE
CMD CODE COMMAND OR FEATURE
(REGISTER) DESCRIPTION
LTC3880 NVM FACTORY-DEFAULT
VALUE AND/OR ATTRIBUTES
LTM4676 NVM FACTORY-DEFAULT
VALUE AND/OR ATTRIBUTES
FREQCFG (or
FSWPHCFG)
Pin-Strap Options
N/A
Switching frequency and phaseangle pin-strap table.
Look-up table for pin-strapping options on setting Channel phase angles and
power-up switching frequency is different. FREQCFG pin on the LTC3880;
FSWPHCFG pin on the LTM4676. See Table 4 of this data sheet.
PAGE
0x00
Channel or page currently targeted
for paged communications.
No difference: 0x00, read/write, non-paged, not stored in NVM.
OPERATIONn
0x01
Operating mode control. On/off,
margin high and margin low.
No difference: 0x80, read/write, paged, stored in user-editable NVM.
ON_OFF_CONFIGn
0x02
RUNn pin and On/Off Configuration.
0x1E, read/write, paged, stored in
user-editable NVM.
CLEAR_FAULTS
0x03
Clear any fault bits that have been
set.
No difference: default value not applicable, send byte only, non-paged, not
stored in NVM.
WRITE_PROTECT
0x10
Level of protection provided by the
device against accidental changes.
No difference: 0x00, read/write, non-paged, stored in user-editable NVM.
STORE_USER_ALL
0x15
Store user operating memory to
EEPROM (user-editable NVM).
No difference: default value not applicable, send byte only, non-paged, not
stored in NVM.
RESTORE_USER_
ALL
0x16
Restore user operating memory
from EEPROM.
Default value not applicable, send
byte only, non-paged, not stored in
NVM.
CAPABILITY
0x19
Summary of PMBus optional
No difference: 0xB0, read-only, non-paged, not stored in NVM.
communication protocols supported
by this device.
VOUT_MODEn
0x20
Output voltage format/exponent.
No difference: 0x14 (2–12), read-only, paged, not stored in NVM.
VOUT_COMMANDn
0x21
Nominal output voltage set point.
No difference: 0x1000 (1.000V), read/write, paged, stored in user-editable
NVM.
VOUT_MAXn
0x24
The upper limit on the commandable Page 0x00: 0x4189 (4.096V).
output voltage.
Page 0x01: 0x5800 (5.500V).
Read/write, paged, stored in usereditable NVM.
VOUT_MARGIN_
HIGHn
0x25
Margin high output voltage set point. No difference: 0x10CD (1.050V), read/write, paged, stored in user-editable
Must be greater than
NVM.
VOUT_COMMANDn.
VOUT_MARGIN_
LOWn
0x26
Margin low output voltage set point. No difference: 0x0F33 (0.950V), read/write, paged, stored in user-editable
Must be less than
NVM.
VOUT_COMMANDn.
VOUT_TRANSITION_
RATEn
0x27
The rate at which the output
voltage changes when VOUTn is
commanded to a new value via I2C.
0xAA00 (0.25V/ms), read/write,
paged, stored in user-editable NVM.
0x8042 (0.001V/ms). Read/write,
paged, stored in user-editable NVM.
FREQUENCY_
SWITCH
0x33
The switching frequency setting.
0xFABC (350kHz), read/write, nonpaged, stored in user-editable NVM.
0xFBE8 (500kHz), read/write, nonpaged, stored in user-editable NVM.
VIN_ON
0x35
The undervoltage lockout (UVLO)rising threshold.
0xCB40 (6.5V), as monitored on
the LTC3880’s “VIN” pin, read/write,
non-paged, stored in user-editable
NVM.
0xCAC0 (5.500V), as monitored on
the LTM4676’s “SVIN” pin, read/write,
non-paged, stored in user-editable
NVM.
0x1F, read/write, paged, stored in
user-editable NVM.
Reserved. Execute MFR_RESET
command (0xFD), instead.
Page 0x00: 0x4000 (4.000V).
Page 0x01: 0x5666 (5.400V).
Read/write, paged, stored in usereditable NVM.
4676fd
For more information www.linear.com/LTM4676
35
LTM4676
Applications Information
PMBus COMMAND
NAME, OR FEATURE
CMD CODE COMMAND OR FEATURE
(REGISTER) DESCRIPTION
LTC3880 NVM FACTORY-DEFAULT
VALUE AND/OR ATTRIBUTES
LTM4676 NVM FACTORY-DEFAULT
VALUE AND/OR ATTRIBUTES
0xCB00 (6.0V) , as monitored on
the LTC3880’s “VIN” pin, read/write,
non-paged, stored in user-editable
NVM.
0xCAA0 (5.250V) , as monitored on
the LTM4676’s “SVIN” pin, read/write,
non-paged, stored in user-editable
NVM.
VIN_OFF
0x36
The undervoltage lockout (UVLO)falling threshold.
IOUT_CAL_GAINn
0x38
The ratio of the voltage at the control 1.8mΩ, read/write, paged, stored in
IC’s current-sense pins to the sensed user-editable NVM.
current, in mΩ, at 25°C.
VOUT_OV_FAULT_
LIMITn
0x40
Output overvoltage fault limit.
No difference: 0x119A (1.100V), read/write, paged, stored in user-editable
NVM.
VOUT_OV_FAULT_
RESPONSEn
0x41
Action to be taken by the device
when an output overvoltage fault is
detected.
0xB8 (non-latching shutdown;
autonomous restart upon fault
removal), read/write, paged, stored
in user-editable NVM.
VOUT_OV_WARN_
LIMITn
0x42
Output overvoltage warning
threshold.
0x1133 (1.075V), read/write, paged, 0x111F (1.070V), read/write, paged,
stored in user-editable NVM.
stored in user-editable NVM.
VOUT_UV_WARN_
LIMITn
0x43
Output undervoltage warning
threshold.
0x0ECD (0.925V), read/write, paged, 0x0EE1 (0.930V), read/write, paged,
stored in user-editable NVM.
stored in user-editable NVM.
VOUT_UV_FAULT_
LIMITn
0x44
Output undervoltage fault limit.
No difference: 0x0E66 (0.900V), read/write, paged, stored in user-editable
NVM.
VOUT_UV_FAULT_
RESPONSEn
0x45
Action to be taken by the device
No difference: 0xB8 (non-latching shutdown; autonomous restart upon fault
when an output undervoltage fault is removal), read/write, paged, stored in user-editable NVM.
detected.
IOUT_OC_FAULT_
LIMITn
0x46
Output overcurrent fault threshold
(cycle-by-cycle inductor peak
current).
0xDBB8 (29.75A), read/write, paged, 0xDADB (22.84A), read/write, paged,
stored in user-editable NVM.
stored in user-editable NVM.
IOUT_OC_FAULT_
RESPONSEn
0x47
Action to be taken by the device
when an output overcurrent fault is
detected.
No difference: 0x00 (try to regulate through the fault condition/event;
limit the cycle-by-cycle peak of the inductor current to not exceed the
commanded IOUT_OC_FAULT_LIMIT), read/write, paged, stored in usereditable NVM.
IOUT_OC_WARN_
LIMITn
0x4A
Output overcurrent warning
threshold (time-averaged inductor
current).
0xDA80 (20.00A), read/write, paged, 0xD3E6 (15.59A), read/write, paged,
stored in user-editable NVM.
stored in user-editable NVM.
OT_FAULT_LIMITn
0x4F
Overtemperature fault threshold.
0xEB20 (100°C), read/write, paged,
stored in user-editable NVM.
OT_FAULT_
RESPONSEn
0x50
Action to be taken by the device
when an overtemperature fault is
detected via TSNSna (TSNSn).
No difference: 0xB8 (non-latching shutdown; autonomous restart upon fault
removal), read/write, paged, stored in user-editable NVM.
OT_WARN_LIMITn
0x51
Overtemperature warning threshold. 0xEAA8 (85°C), read/write, paged,
stored in user-editable NVM.
0xEBE8 (125°C), read/write, paged,
stored in user-editable NVM.
UT_FAULT_LIMITn
0x53
Undertemperature fault threshold.
0xE580 (–40°C), read/write, paged,
stored in user-editable NVM.
0xE530 (–45°C), read/write, paged,
stored in user-editable NVM.
UT_FAULT_
RESPONSEn
0x54
Response to undertemperature fault
events.
0xB8 (non-latching shutdown;
autonomous restart upon fault
removal), read/write, paged, stored
in user-editable NVM.
0x00 (ignore; continue without
interruption), read/write, paged,
stored in user-editable NVM, read/
write, paged, stored in user-editable
NVM.
VIN_OV_FAULT_
LIMIT
0x55
Input supply (SVIN) overvoltage fault 0xD3E0 (15.5V), read/write, nonlimit.
paged, stored in user-editable NVM.
0xDB60 (27.0V), read/write, nonpaged, stored in user-editable NVM.
36
Trimmed at ATE, read-only, stored in
factory-only NVM.
0x7A (non-latching shutdown;
autonomous restart upon fault
removal; 20µs glitch filter), read/write,
paged, stored in user-editable NVM.
0xF200 (128°C), read/write, paged,
stored in user-editable NVM.
4676fd
For more information www.linear.com/LTM4676
LTM4676
Applications Information
PMBus COMMAND
NAME, OR FEATURE
CMD CODE COMMAND OR FEATURE
(REGISTER) DESCRIPTION
LTC3880 NVM FACTORY-DEFAULT
VALUE AND/OR ATTRIBUTES
LTM4676 NVM FACTORY-DEFAULT
VALUE AND/OR ATTRIBUTES
VIN_OV_FAULT_
RESPONSEn
0x56
Response to input overvoltage fault
events.
0x80 (latched-off shutdown), read/
write, paged, stored in user-editable
NVM.
0xB8 (non-latching shutdown;
autonomous restart upon fault
removal), read/write, paged, stored in
user-editable NVM.
VIN_UV_WARN_
LIMIT
0x58
Input undervoltage warning
threshold.
0xCB26 (6.297V), read/write, nonpaged, stored in user-editable NVM.
0xCAA6 (5.297V), read/write, nonpaged, stored in user-editable NVM.
IIN_OC_WARN_
LIMIT
0x5D
Input supply overcurrent warning
threshold.
0xD280 (10A), read/write, nonpaged, stored in user-editable NVM.
0xD300 (12A), read/write, non-paged,
stored in user-editable NVM.
POWER_GOOD_ONn
0x5E
Output voltage at or above which a
power good should be asserted.
No difference: 0x0EE1 (0.9299V), read/write, paged, stored in user-editable
NVM.
POWER_GOOD_OFFn
0x5F
Output voltage at or below which a
power good should be de-asserted.
No difference: 0x0EB8 (0.9199V), read/write, paged, stored in user-editable
NVM.
TON_DELAYn
0x60
Time from RUNn and/or
OPERATIONn on to output rail
turn-on.
No difference: 0x8000 (0ms), read/write, paged, stored in user-editable NVM.
TON_RISEn
0x61
Time from when the output voltage
reference starts to rise until it
reaches its commanded setting.
0xD200 (8ms), read/write, paged,
stored in user-editable NVM.
0xC300 (3ms), read/write, paged,
stored in user-editable NVM.
TON_MAX_FAULT_
LIMITn
0x62
Turn-on watchdog timeout fault
threshold (time permitted for
VOUTn to reach or exceed VOUT_
UV_FAULT_LIMITn after turn-on
command is received).
0xD280 (10ms), read/write, paged,
stored in user-editable NVM.
0xCA80 (5ms), read/write, paged,
stored in user-editable NVM.
TON_MAX_FAULT_
RESPONSEn
0x63
Action to be taken by the device
when a TON_MAX_FAULTn event is
detected.
No difference: 0xB8 (non-latching shutdown; autonomous restart upon fault
removal), read/write, paged, stored in user-editable NVM.
TOFF_DELAYn
0x64
Time from RUN and/or Operation off No difference: 0x8000 (0ms), read/write, paged, stored in user-editable NVM.
to the start of TOFF_FALLn ramp.
TOFF_FALLn
0x65
Time from when the output voltage
reference starts to fall until it
reaches 0V.
TOFF_MAX_WARN_
LIMITn
0x66
Turn-off watchdog timeout fault
0xF258 (150ms), read/write, paged,
threshold (time permitted for VOUTn stored in user-editable NVM.
to decay to or below 12.5% of the
commanded VOUTn value at the time
of receiving a turn-off command).
STATUS_BYTEn
0x78
One byte summary of the unit’s fault No difference: default value not applicable, read/write, paged, not stored in
condition.
NVM.
STATUS_WORDn
0x79
Two byte summary of the unit’s fault No difference: default value not applicable, read/write, paged, not stored in
condition.
NVM.
STATUS_VOUTn
0x7A
Output voltage fault and warning
status.
No difference: default value not applicable, read/write, paged, not stored in
NVM.
STATUS_IOUTn
0x7B
Output current fault and warning
status.
No difference: default value not applicable, read/write, paged, not stored in
NVM.
STATUS_INPUT
0x7C
Input supply (SVIN) fault and
warning status.
No difference: default value not applicable, read/write, non-paged, not stored
in NVM.
0xD200 (8ms), read/write, paged,
stored in user-editable NVM.
0xC300 (3ms), read/write, paged,
stored in user-editable NVM.
0x8000 (no limit; warning is disabled),
read/write, paged, stored in usereditable NVM.
4676fd
For more information www.linear.com/LTM4676
37
LTM4676
Applications Information
PMBus COMMAND
NAME, OR FEATURE
CMD CODE COMMAND OR FEATURE
(REGISTER) DESCRIPTION
LTC3880 NVM FACTORY-DEFAULT
VALUE AND/OR ATTRIBUTES
LTM4676 NVM FACTORY-DEFAULT
VALUE AND/OR ATTRIBUTES
STATUS_
TEMPERATUREn
0x7D
TSNSna (TSNSn)-sensed
No difference: default value not applicable, read/write, paged, not stored in
temperature fault and warning status NVM.
for READ_TEMERATURE_1n .
STATUS_CML
0x7E
Communication and memory fault
and warning status.
STATUS_MFR_
SPECIFICn
0x80
Manufacturer specific fault and state No difference: default value not applicable, read/write, paged, not stored in
information.
NVM.
READ_VIN
0x88
Measured input supply (SVIN)
voltage.
READ_IIN
0x89
Calculated total input supply current. No difference: default value not applicable, read-only, non-paged, not stored
in NVM.
READ_VOUTn
0x8B
Measured output voltage.
No difference: default value not applicable, read-only, paged, not stored in
NVM.
READ_IOUTn
0x8C
Measured output current.
No difference: default value not applicable, read-only, paged, not stored in
NVM.
READ_
TEMPERATURE_1n
0x8D
Measurement of TSNSna (TSNSn)sensed temperature.
No difference: default value not applicable, read-only, paged, not stored in
NVM.
READ_
TEMPERATURE2
0x8E
Measured control IC junction
temperature.
No difference: default value not applicable, read-only, non-paged, not stored
in NVM.
READ_DUTY_
CYCLEn
0x94
Measured duty cycle of MTn .
No difference: default value not applicable, read-only, paged, not stored in
NVM.
READ_POUTn
0x96
Calculated output power.
No difference: default value not applicable, read-only, paged, not stored in
NVM.
PMBUS_REVISION
0x98
PMBus revision supported by this
device.
No difference: 0x11 (Revision 1.1 of Part I and Revision 1.1 of Part II of
PMBus Specification documents), read-only, non-paged, not stored in NVM.
MFR_ID
0x99
Manufacturer identification, in ASCII No difference: “LTC”, read-only, non-paged.
MFR_MODEL
0x9A
Manufacturer’s part number, in ASCII “LTC3880”, read-only, non-paged.
MFR_SERIAL
0x9E
Serial number of this specific unit.
No difference: Up to nine bytes of custom-formatted data that identify the
unit’s configuration, read-only, non-paged.
MFR_VOUT_MAXn
0xA5
Maximum allowed output voltage.
No difference: 0x4189 (4.096V) on Channel 0, 0x5800 (5.500V) on
Channel 1. Read-only, paged, not stored in user-editable NVM.
USER_DATA_00
0xB0
OEM reserved data.
Read/write, non-paged, stored in
user-editable NVM. Recommended
against altering.
Read/write, non-paged, stored in usereditable NVM. Recommended against
altering.
USER_DATA_01n
0xB1
OEM reserved data.
Read/write, paged, stored in
user-editable NVM. Recommended
against altering.
Read/write, paged, stored in usereditable NVM. Recommended against
altering.
USER_DATA_02
0xB2
OEM reserved data.
Read/write, non-paged, stored in
user-editable NVM. Recommended
against altering.
Read/write, non-paged, stored in usereditable NVM. Recommended against
altering.
USER_DATA_03n
0xB3
User-editable words available for
the user.
No difference: 0x0000, read/write, paged, stored in user-editable NVM.
USER_DATA_04
0xB4
A user-editable word available for
the user.
No difference: 0x0000, read/write, non-paged, stored in user-editable NVM.
38
No difference: default value not applicable, read/write, non-paged, not stored
in NVM.
No difference: default value not applicable, read-only, non-paged, not stored
in NVM.
“LTM4676”, read-only, non-paged.
4676fd
For more information www.linear.com/LTM4676
LTM4676
Applications Information
PMBus COMMAND
NAME, OR FEATURE
CMD CODE COMMAND OR FEATURE
(REGISTER) DESCRIPTION
LTC3880 NVM FACTORY-DEFAULT
VALUE AND/OR ATTRIBUTES
LTM4676 NVM FACTORY-DEFAULT
VALUE AND/OR ATTRIBUTES
MFR_EE_UNLOCK
0xBD
Unlock user EEPROM for access by No difference: default value not applicable, read/write, non-paged, not stored
MFR_EE_ERASE and MFR_EE_DATA in NVM.
commands.
MFR_EE_ERASE
0xBE
Initialize user EEPROM for bulk
programming by MFR_EE_DATA.
No difference: default value not applicable, read/write, non-paged, not stored
in NVM.
MFR_EE_DATA
0xBF
Data transferred to and from
EEPROM using sequential PMBus
word reads or writes. Supports bulk
programming.
No difference: default value not applicable, read/write, non-paged, not stored
in NVM.
MFR_CHAN_
CONFIG_*n
0xD0
Channel-specific configuration bits.
0x1F, read/write, paged, stored
in user-editable NVM. Register is
named “MFR_CHAN_CONFIG_
LTC3880”.
0x1F, read/write, paged, stored in
user-editable NVM. Register is named
“MFR_CHAN_CONFIG” and referred to
as “MFR_CHAN_CONFIG_LTM467X”
in LTpowerPlay.
MFR_CONFIG_ALL_*
0xD1
Global configuration bits, i.e.,
common to both VOUT channels 0
and 1.
0x09, read/write, non-paged, stored
in user-editable NVM. Register
is named “MFR_CONFIG_ALL_
LTC3880”.
0x09, read/write, non-paged, stored in
user-editable NVM. Register is named
“MFR_CONFIG_ALL” and referred to
as “MFR_CONFIG_ALL_LTM467X” in
LTpowerPlay.
MFR_GPIO_
PROPAGATE_*n
0xD2
Configuration bits for propagating
faults to the GPIOn pins.
0x2997, read/write, paged, stored
in user-editable NVM. Register is
named “MFR_GPIO_PROPAGATE_
LTC3880”.
0x6893, read/write, paged, stored
in user-editable NVM. Register is
named “MFR_GPIO_PROPAGATE”
and referred to as “MFR_GPIO_
PROPAGATE_LTM467X” in
LTpowerPlay.
MFR_PWM_
MODE_*n
0xD4
Configuration for the PWM engine of 0xC2, read/write, paged, stored in
each VOUT channel.
user-editable NVM. Bit 4 is reserved
and should be 0b. Register is named
“MFR_PWM_MODE_LTC3880”.
MFR_GPIO_
RESPONSEn
0xD5
Action to be taken by the device
when the GPIOn pin is asserted low
by circuitry external to the unit.
No difference: 0xC0 (make the respective output’s power stage high
impedance, i.e., three-stated; autonomous restart upon fault removal),
read/write, paged, stored in user-editable NVM.
MFR_OT_FAULT_
RESPONSE
0xD6
Action to be taken by the device
when a control IC junction
overtemperature fault is detected.
No difference: 0xC0 (make the respective output’s power stage high
impedance, i.e., three-stated; autonomous restart upon fault removal),
read-only, non-paged, not stored in user-editable NVM.
MFR_IOUT_PEAKn
0xD7
Maximum measured value of
READ_IOUTn since the last MFR_
CLEAR_PEAKS.
No difference: default value not applicable, read-only, paged, not stored in
NVM.
MFR_CHANNEL_
ADDRESSn
0xD8
Address to the PAGE-activated
channel.
No difference: 0x80, read/write, paged, stored in user-editable NVM.
0xC2, read/write, paged, stored
in user-editable NVM. When bit 4
of Page 0 (MFR_PWM_MODE_
LTM46760[4]) is 0b, Channel
temperature-sensing is performed per
LTC3880 documentation. When MFR_
PWM_MODE_LTM46760[4]= 1b,
TSNS1A monitors a temperature sensor
external to the LTM4676, per the
Operation section. Register is named
“MFR_PWM_MODE” and referred to
as “MFR_PWM_MODE_LTM467X” in
LTpowerPlay.
4676fd
For more information www.linear.com/LTM4676
39
LTM4676
Applications Information
PMBus COMMAND
NAME, OR FEATURE
CMD CODE COMMAND OR FEATURE
(REGISTER) DESCRIPTION
LTC3880 NVM FACTORY-DEFAULT
VALUE AND/OR ATTRIBUTES
LTM4676 NVM FACTORY-DEFAULT
VALUE AND/OR ATTRIBUTES
MFR_RETRY_
DELAYn
0xDB
Retry interval during fault-retry
mode.
0xFABC (350ms), read/write, paged, 0xF3E8 (250ms), read/write, paged,
stored in user-editable NVM.
stored in user-editable NVM.
MFR_RESTART_
DELAYn
0xDC
Minimum interval (nominal) the
RUNn pin is pulled logic low by
internal circuitry.
0xFBE8 (500ms), read/write, paged, 0xF258 (150ms), read/write, paged,
stored in user-editable NVM.
stored in user-editable NVM.
MFR_VOUT_PEAKn
0xDD
Maximum measured value of
READ_VOUTn since the last MFR_
CLEAR_PEAKS.
No difference: default value not applicable, read-only, paged, not stored in
NVM.
MFR_VIN_PEAK
0xDE
Maximum measured value of
READ_VIN since the last MFR_
CLEAR_PEAKS.
No difference: default value not applicable, read-only, non-paged, not stored
in NVM.
MFR_
TEMPERATURE_1_
PEAKn
0xDF
Maximum value of TSNSna (TSNSn)- No difference: default value not applicable, read-only, paged, not stored in
measured temperature since the last NVM.
MFR_CLEAR_PEAKS.
MFR_CLEAR_PEAKS
0xE3
Clears all peak values.
No difference: default value not applicable, send byte only, non-paged, not
stored in NVM.
MFR_PADS
0xE5
Digital status of the I/O pads.
No difference: default value not applicable, read-only, non-paged, not stored
in NVM.
MFR_ADDRESS
0xE6
The 7 bits of the LTM4676’s I2C
slave address.
0x4F, read/write, non-paged,
stored in user-editable NVM. Least
significant four bits augmented by
ASEL resistor network. Can take on
value 0x80 to disable device-specific
addressing.
0x4F, read-only, non-paged, stored in
factory-only NVM. Least significant
four bits augmented by ASEL resistor
pin-strap. Cannot take on value 0x80;
device-specific addressing cannot be
disabled.
MFR_SPECIAL_ID
0xE7
Manufacturer code representing IC
silicon and revision
0x40XX, read-only, non-paged.
0x448X or 0x440X, read-only, nonpaged.
MFR_IIN_OFFSETn
0xE9
Coefficient used in calculations of
READ_IIN and MFR_READ_IINn ,
representing the contribution of
input current drawn by the control
IC, including the MOSFET drivers.
0x9333 (0.0500A), read/write,
paged, stored in user-editable NVM.
0x8BE7 (0.0305A), read/write, paged,
stored in user-editable NVM.
MFR_FAULT_LOG_
STORE
0xEA
Commands a transfer of the fault log No difference: default value not applicable, send byte only, non-paged, not
from RAM to EEPROM. This causes stored in NVM.
the part to behave as if a channel
has faulted off.
MFR_FAULT_LOG_
CLEAR
0xEC
Initialize the EEPROM block reserved No difference: default value not applicable, send byte only, non-paged, not
for fault logging and clear any
stored in NVM.
previous fault logging locks.
40
4676fd
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LTM4676
Applications Information
PMBus COMMAND
NAME, OR FEATURE
CMD CODE COMMAND OR FEATURE
(REGISTER) DESCRIPTION
LTC3880 NVM FACTORY-DEFAULT
VALUE AND/OR ATTRIBUTES
LTM4676 NVM FACTORY-DEFAULT
VALUE AND/OR ATTRIBUTES
MFR_READ_IINn
0xED
Calculated input current, by channel. No difference: default value not applicable, read-only, paged, not stored in
NVM.
MFR_FAULT_LOG
0xEE
Fault log data bytes. This
No difference: default value not applicable, read-only, non-paged, stored in
sequentially retrieved data is used to fault-log NVM.
assemble a complete fault log.
MFR_COMMON
0xEF
Manufacturer status bits that are
common across multiple LTC ICs/
modules.
No difference: default value not applicable, read-only, non-paged, not stored
in NVM.
MFR_COMPARE_
USER_ALL
0xF0
Compares current command
contents (RAM) with NVM.
No difference: default value not applicable, send byte only, non-paged, not
stored in NVM.
MFR_
TEMPERATURE_2_
PEAK
0xF4
Maximum measured control IC
junction temperature since last
MFR_CLEAR_PEAKS.
No difference: default value not applicable, read-only, non-paged, not stored
in NVM.
MFR_PWM_
CONFIG_*
0xF5
Configuration bits for setting the
phase interleaving angles and output
voltage ranges of Channels 0 and 1,
and SHARE_CLK behavior in UVLO.
0x10, read/write, non-paged, stored
in user-editable NVM. Register
is named “MFR_PWM_CONFIG_
LTC3880”.
0x10, read/write, non-paged, stored in
user-editable NVM. Register is named
“MFR_PWM_CONFIG” and referred to
as “MFR_PWM_CONFIG_LTM467X”
in LTpowerPlay.
MFR_IOUT_CAL_
GAIN_TCn
0xF6
Temperature coefficient of the
current sensing element.
0x0F3C (3900ppm/°C), read/write,
paged, stored in user-editable NVM.
0x0F14 (3860ppm/°C), read/write,
paged, stored in user-editable NVM.
MFR_TEMP_1_
GAINn
0xF8
Sets the slope of the temperature
sensors that interface to TSNSna
(TSNSn).
No difference: 0x4000 (1.0, in custom units), read/write, paged, stored in
NVM.
MFR_TEMP_1_
OFFSETn
0xF9
Sets the offset of the TSNSna
(TSNSn) temperature sensor with
respect to –273.1°C.
No difference: 0x8000 (0.0), read/write, paged, stored in NVM.
MFR_RAIL_
ADDRESSn
0xFA
Common address for PolyPhase
outputs to adjust common
parameters.
No difference: 0x80, read/write, paged, stored in NVM.
MFR_RESET
0xFD
Commanded reset without requiring
a power down.
No difference: default value not applicable, send byte only, non-paged, not
stored in NVM.
4676fd
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41
LTM4676
Applications Information
Table 2. VOUTn CFG Pin Strapping Look-Up Table for the
LTM4676's Output Voltage, Coarse Setting (Not Applicable if
MFR_CONFIG_ALL[6] = 1b)
RVOUTn CFG*
(kΩ)
VOUTn (V) SETTING
COARSE
MFR_PWM_CONFIG[6-n ] BIT
Open
NVM
NVM
32.4
See Table 3
See Table 3
22.6
3.3
0
18.0
3.1
0
15.4
2.9
0
12.7
2.7
0
10.7
2.5
0, if VTRIMn > 0mV
1, if VTRIMn ≤ 0mV
9.09
2.3
1
7.68
2.1
1
6.34
1.9
1
5.23
1.7
1
4.22
1.5
1
3.24
1.3
1
2.43
1.1
1
1.65
0.9
1
0.787
0.7
1
0
0.5
1
*RVOUTn CFG value indicated is nominal. Select RVOUTn CFG from a resistor
vendor such that its value is always within 3% of the value indicated in
the table. Take into account resistor initial tolerance, T.C.R. and resistor
operating temperatures, soldering heat/IR reflow, and endurance of the
resistor over its lifetime. Thermal shock/cycling, moisture (humidity) and
other effects (depending on one’s specific application) could also affect
RVOUTn CFG’s value over time. All such effects must be taken into account
in order for resistor pin strapping to yield the expected result at every
SVIN power-up and/or every execution of MFR_RESET, over the lifetime
of one’s product.
42
Table 3. VTRIMnCFG Pin Strapping Look-Up Table for the
LTM4676's Output Voltage, Fine Adjustment Setting (Not
Applicable if MFR_CONFIG_ALL[6] = 1b)
VTRIM (mV) FINE
ADJUSTMENT
TO VOUTn
SETTING WHEN
RESPECTIVE
RVOUTnCFG ≠
RVTRIMnCFG*
(kΩ)
32.4kΩ
Open
0
VOUTn OUTPUT
VOLTAGE
SETTING
(V) WHEN
VOUTnCFG PIN
USES RCFG =
32.4kΩ
NVM
MFR_PWM_
CONFIG[6-n] BIT
0, if VOUT_OV_
FAULT_LIMITn
> 2.75V
32.4
99
22.6
86.625
18.0
74.25
15.4
61.875
12.7
49.5
10.7
37.125
5.50
0
9.09
24.75
5.25
0
7.68
12.375
5.00
0
6.34
–12.375
4.75
0
5.23
–24.75
4.50
0
4.22
–37.125
4.25
0
3.24
–49.5
4.00
0
2.43
–61.875
3.75
0
1, if VOUT_OV_
FAULT_LIMITn
≤ 2.75V
1.65
–74.25
3.63
0
0.787
–86.625
3.50
0
0
–99
3.46
0
*RVTRIMnCFG value indicated is nominal. Select RVTRIMnCFG from a resistor
vendor such that its value is always within 3% of the value indicated in
the table. Take into account resistor initial tolerance, T.C.R. and resistor
operating temperatures, soldering heat/IR reflow, and endurance of the
resistor over its lifetime. Thermal shock/cycling, moisture (humidity) and
other effects (depending on one’s specific application) could also affect
RVTRIMnCFG’s value over time. All such effects must be taken into account
in order for resistor pin strapping to yield the expected result at every
SVIN power-up and/or every execution of MFR_RESET, over the lifetime of
one’s product.
4676fd
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LTM4676
Applications Information
Table 4. FSWPHCFG Pin Strapping Look-Up Table to Set the LTM4676's Switching Frequency and Channel Phase-Interleaving Angle
(Not Applicable if MFR_CONFIG_ALL[6] = 1b)
RFSWPHCFG*
(kΩ)
SWITCHING FREQUENCY
(kHz)
θSYNC TO θ0
Open
NVM; LTM4676 Default = 500
NVM; LTM4676 Default = 0°
32.4
250
0°
180°
000b
22.6
350
0°
180°
000b
18.0
425
0°
180°
000b
15.4
575
0°
180°
000b
12.7
650
0°
180°
000b
10.7
750
0°
180°
000b
9.09
1000
0°
180°
000b
7.68
500
120°
240°
100b
6.34
500
90°
270°
001b
5.23
External**
0°
240°
010b
4.22
External**
0°
120°
011b
3.24
External**
60°
240°
101b
2.43
External**
120°
300°
110b
1.65
External**
90°
270°
001b
0.787
External**
0°
180°
000b
0
External**
120°
240°
100b
θSYNC TO θ1
bits [2:0] of
MFR_PWM_CONFIG
NVM; LTM4676 Default = 180° NVM; LTM4676 Default = 000b
*RFSWPHCFG value indicated is nominal. Select RFSWPHCFG from a resistor vendor such that its value is always within 3% of the value indicated in
the table. Take into account resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the
resistor over its lifetime. Thermal shock/cycling, moisture (humidity) and other effects (depending on one’s specific application) could also affect
RFSWPHCFG’s value over time. All such effects must be taken into account in order for resistor pin-strapping to yield the expected result at every
SVIN power-up and/or every execution of MFR_RESET, over the lifetime of one’s product.
**"External" setting corresponds to FREQUENCY_SWITCH (Register 0x33) value set to 0x0000; the device synchronizes its switching frequency to
that of the clock provided on the SYNC pin.
4676fd
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43
LTM4676
Applications Information
Table 5. ASEL Pin Strapping Look-Up Table to Set the
LTM4676's Slave Address (Applicable Regardless of
MFR_CONFIG_ALL[6] Setting)
RASEL* (kΩ)
SLAVE ADDRESS
Open
100_1111_R/W
32.4
100_1111_R/W
22.6
100_1110_R/W
18.0
100_1101_R/W
15.4
100_1100_R/W
12.7
100_1011_R/W
10.7
100_1010_R/W
9.09
100_1001_R/W
7.68
100_1000_R/W
6.34
100_0111_R/W
5.23
100_0110_R/W
4.22
100_0101_R/W
3.24
100_0100_R/W
2.43
100_0011_R/W
1.65
100_0010_R/W
0.787
100_0001_R/W
0
100_0000_R/W
Table 6. LTM4676 MFR_ADDRESS Command Examples
Expressed in 7- and 8-Bit Addressing
HEX DEVICE
ADDRESS BIT BIT BIT BIT BIT BIT BIT BIT
DESCRIPTION 7 BIT 8 BIT 7 6 5 4 3 2 1 0 R/W
Rail4
0x5A 0xB4
Global4
0x5B 0xB6
0
1
0
1
1
0
1
1
0
Default
0x4F 0x9E
0
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
0
0
Example 1
0x40 0x80
0
1
0
0
0
0
0
0
0
Example 2
0x41 0x82
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
Disabled2,3
Note 1: This table can be applied to the MFR_CHANNEL_ADDRESSn
and MFR_RAIL_ADDRESSn commands, but not the MFR_ADDRESS
command.
Note 2: A disabled value in one command does not disable the device, nor
does it disable the Global address.
Note 3: A disabled value in one command does not inhibit the device from
responding to device addresses specified in other commands.
Note 4: It is not recommended to write the value 0x00, 0x0C
(7 bit), or 0x5A (7 bit) or 0x5B (7 bit) to the
MFR_CHANNEL_ADDRESSn or the MFR_RAIL_ADDRESSn
commands.
where:
R/W = Read/Write bit in control byte.
All PMBus device addresses listed in the specification are 7 bits wide
unless otherwise noted.
Note: The LTM4676 will always respond to slave address 0x5A and 0x5B
regardless of the NVM or ASEL resistor configuration values.
*RCFG value indicated is nominal. Select RCFG from a resistor vendor
such that its value is always within 3% of the value indicated in the
table. Take into account resistor initial tolerance, T.C.R. and resistor
operating temperatures, soldering heat/IR reflow, and endurance of the
resistor over its lifetime. Thermal shock cycling, moisture (humidity)
and other effects (depending on one’s specific application) could
also affect RCFG’s value over time. All such effects must be taken into
account in order for resistor pin-strapping to yield the expected result
at every SVIN power-up and/or every execution of MFR_RESET, over the
lifetime of one’s product.
44
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LTM4676
Applications Information
VIN to VOUT Step-Down Ratios
Output Capacitors
There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage.
Each output of the LTM4676 is capable of 95% duty cycle
at 500kHz, but the VIN to VOUT minimum dropout is still
a function of its load current and will limit output current
capability related to high duty cycle on the topside switch.
Minimum on-time tON(MIN) is another consideration in
operating at a specified duty cycle while operating at a
certain frequency due to the fact that tON(MIN) < D/fSW,
where D is duty cycle and fSW is the switching frequency.
tON(MIN) is specified in the electrical parameters as 90ns.
See Note 6 in the Electrical Characteristics section for
output current guideline.
The LTM4676 is designed for low output voltage ripple
noise and good transient response. The bulk output
capacitors defined as COUT are chosen with low enough
effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low
ESR tantalum capacitor, a low ESR polymer capacitor or
ceramic capacitor. The typical output capacitance range
for each output is from 400µF to 700µF. Additional output
filtering may be required by the system designer, if further
reduction of output ripple or dynamic transient spikes
is required. Table 20 shows a matrix of different output
voltages and output capacitors to minimize the voltage
droop and overshoot during a 6.5A/µs transient. The table
optimizes total equivalent ESR and total bulk capacitance
to optimize the transient performance. Stability criteria are
considered in the Table 20 matrix, and the Linear Technology
µModule Power Design Tool will be provided for stability
analysis. Multiphase operation reduces effective output
ripple as a function of the number of phases. Application
Note 77 discusses this noise reduction versus output
ripple current cancellation, but the output capacitance
should be considered carefully as a function of stability
and transient response. The Linear Technology µModule
Power Design Tool can calculate the output ripple reduction as the number of implemented phases increases by N
times. A small value 10Ω resistor can be placed in series
from VOUTn to the VOSNS0+ or VOSNS1 pin to allow for a
bode plot analyzer to inject a signal into the control loop
and validate the regulator stability.
Input Capacitors
The LTM4676 module should be connected to a low acimpedance DC source. For the regulator input four 22µF
input ceramic capacitors are used to handle the RMS
ripple current. A 47µF to 100µF surface mount aluminum
electrolytic bulk capacitor can be used for more input bulk
capacitance. This bulk input capacitor is only needed if
the input source impedance is compromised by long inductive leads, traces or not enough source capacitance.
If low impedance power planes are used, then this bulk
capacitor is not needed.
For a buck converter, the switching duty-cycle can be
estimated as:
Dn =
VOUTn
VINn
Light Load Current Operation
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
ICINn (RMS) =
IOUTn (MAX)
η%
• Dn • (1− Dn )
The LTM4676 has three modes of operation including high
efficiency Burst Mode operation, discontinuous conduction mode or forced continuous conduction mode. Mode
selection is done using the MFR_PWM_MODEn command
(discontinuous conduction is always the start-up mode,
forced continuous is the default running mode).
In the above equation, η% is the estimated efficiency of the
power module. The bulk capacitor can be a switcher-rated
electrolytic aluminum capacitor, or a Polymer capacitor.
4676fd
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45
LTM4676
Applications Information
In Burst Mode operation, the peak current in the inductor
is set to approximately one-third of the maximum sense
voltage even though the voltage on the COMPna pin indicates a lower value. If the average inductor current is
higher than the load current, the error amplifier, EA, will
decrease the voltage on the COMPna pin. When the COMPna
voltage drops below approximately 0.5V, the internal Burst
Mode operation asserts and both power stage MOSFETs
are turned off. In Burst Mode operation, the load current
is supplied by the output capacitor. As the output voltage
decreases, the EA output begins to rise. When the output
voltage drops sufficiently, Burst Mode operation is deasserted, and the controller resumes normal operation by
turning on the top MOSFET (MTn) on the next PWM cycle.
If a channel is enabled for Burst Mode or discontinuous
mode operation, the inductor current is not allowed to
reverse. The reverse current comparator, IREV , turns off
the bottom MOSFET (MBn) just before the inductor current reaches zero, preventing it from reversing and going
negative. Thus, the controller can operate in discontinuous
(pulse-skippng)operation. In forced continuous operation,
the inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor current
is determined solely by the voltage on the COMPna pin.
In this mode, the efficiency at light loads is lower than in
Burst Mode operation. However, continuous mode exhibits
lower output ripple and less interference with audio circuitry. Forced continuous conduction mode may result in
reverse inductor current, which can cause the input supply
to boost. The VIN_OV_FAULT_LIMIT can detect this (if
SVIN is connected to VIN0 and/or VIN1) and turn off the
offending channel. However, this fault is based on an ADC
read and can nominally take up to 100ms to detect. If there
is a concern about the input supply boosting, keep the part
in discontinuous conduction or Burst Mode operation.
If the part is set to Burst Mode operation, as the inductor
average current increases, the controller automatically
modifies the operation from Burst Mode operation, to
discontinuous mode to continuous mode.
46
Switching Frequency and Phase
The switching frequency of the LTM4676’s channels is
established by its analog phase-locked-loop (PLL) locking
on to the clock present at the module’s SYNC pin. The
clock waveform on the SYNC pin can be generated by
the LTM4676’s internal circuitry when an external pull-up
resistor to 3.3V (e.g., VDD33) is provided, in combination
with the LTM4676 control IC’s FREQUENCY_SWITCH
register being set to one of the following supported values:
250kHz, 350kHz, 425kHz, 500kHz, 575kHz, 650kHz,
750kHz, 1MHz (see Table 8 for hexadecimal values). In
this configuration, the module is called a “sync master”:
SYNC becomes a bidirectional open-drain pin, and the
LTM4676 pulls SYNC logic low for nominally 500ns at a
time, at the prescribed clock rate. The SYNC signal can
be bused to other LTM4676 modules (configured as
“sync slaves”), for purposes of synchronizing switching
frequencies of multiple modules within a system—but
only one LTM4676 should be configured as a “sync
master”; the other LTM4676(s) should be configured as
“sync slaves”. To configure an LTM4676 as a “sync slave”,
set its FREQUENCY_SWITCH register to 0x0000. In that
configuration, the LTM4676’s SYNC pin becomes a high
impedance input, only—i.e., it does not drive SYNC low.
The FREQUENCY_SWITCH register can be altered
via I2C commands, but only when switching action is
disengaged, i.e., the module’s outputs are turned off. The
FREQUENCY_SWITCH register takes on the value stored
in NVM at SVIN power-up, but is overridden according to
a resistor pin-strap applied between the FSWPHCFG pin and
SGND only if the module is configured to respect resistor
pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 4
highlights available resistor pin-strap and corresponding
FREQUENCY_SWITCH settings.
The relative phasing of all active channels in a PolyPhase®
rail should be optimally phased. The relative phasing of
each rail is 360°/n, where n is the number of phases in
the rail. MFR_PWM_CONFIG[2:0] configures channel
relative phasing with respect to the SYNC pin. Phase
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LTM4676
Applications Information
relationship values are indicated with 0° corresponding
to the falling edge of SYNC being coincident with the
turn-on of the top MOSFETs, MTn.
The MFR_PWM_CONFIG register can be altered via
I2C commands, but only when switching action is
disengaged, i.e., the module’s outputs are turned off. The
MFR_PWM_CONFIG register takes on the value stored in
NVM at SVIN power-up, but is overridden according to a
resistor pin-strap applied between the FSWPHCFG pin and
SGND only if the module is configured to respect resistor
pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 4
highlights available resistor pin-strap and corresponding
MFR_PWM_CONFIG[2:0] settings.
Some combinations of FREQUENCY_SWITCH and
MFR_PWM_CONFIG[2:0] are not available by resistor
pin-strapping the F SWPHCFG pin. All combinations
of supported values for FREQUENCY_SWITCH and
MFR_PWM_CONFIG[2:0] can be configured by NVM
programming—or, I2C transactions, provided switching
action is disengaged, i.e., the module’s outputs are
turned off.
voltages whose recommended switching frequencies
in Table 7 are significantly different, operation at the
higher of the two recommended switching frequencies
is preferable, but minimum on-time must be considered.
(See Minimum On-Time Considerations section.) For
example, consider an application in which it is desired for
an LTM4676 to step-down 12VIN to 1VOUT on Channel 0,
and 12VIN to 3.3VOUT on Channel 1: according to Table 7,
the recommended switching frequency is 350kHz and
650kHz, respectively. However, the switching frequency
setting of the LTM4676 is common to both channels.
Based on the aforementioned guidance, operation at
650kHz would be preferred—in order to keep inductor
ripple currents reasonable—however, it is then realized
that the on-time for a 12VIN-to-1VOUT condition at
650kHz is only 128ns, which is marginal. Therefore, for
this particular example, the recommended switching
frequency becomes 575kHz.
Table 7. Recommended Switching Frequency for Various
VIN-to-VOUT Step-Down Scenarios.
5VIN
8VIN
12VIN
24VIN
Care must be taken to minimize capacitance on SYNC
to assure that the pull-up resistor versus the capacitor
load has a low enough time constant for the application
to form a “clean” clock. (See “Open-Drain Pins”, later
in this section.)
0.9VOUT
350kHz
350kHz
350kHz
250kHz
1.0VOUT
350kHz
350kHz
350kHz
250kHz
1.2VOUT
350kHz
350kHz
350kHz
350kHz
1.5VOUT
350kHz
350kHz
425kHz
425kHz
1.8VOUT
425kHz
425kHz
500kHz
500kHz
2.5VOUT
425kHz
500kHz
575kHz
650kHz
When an LTM4676 is configured as a sync slave, it is
permissible for external circuitry to drive the SYNC pin
from a current-limited source (less than 10mA), rather
than using a pull-up resistor. Any external circuitry must
not drive high with arbitrarily low impedance at SVIN
power-up, because the SYNC output can be low impedance
until NVM contents have been downloaded to RAM.
3.3VOUT
425kHz
575kHz
650kHz
750kHz
5.0VOUT
N/A
500kHz
750kHz
1MHz
Recommended LTM4676 switching frequencies of
operation for many common VIN-to-VOUT applications
are indicated in Table 7. When the two channels of an
LTM4676 are stepping input voltage(s) down to output
The current drawn by the SVIN pin of the LTM4676 is not
digitized or computed. A value representing the estimated
SVIN current is located in the MFR_IIN_OFFSETn register,
and is used in the computations of input current readback
telemetry, namely READ_IIN and and MFR_READ_IINn.
The recommended setting of MFR_IIN_OFFSETn is
found in Table 8. The same value should be used for
MFR_IIN_OFFSET0 and MFR_IIN_OFFSET1 (i.e., Pages
0x00 and 0x01).
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LTM4676
Applications Information
Table 8. Recommended MFR_IIN_OFFSETn Setting vs
Switching Frequency Setting
SWITCHING
FREQUENCY
(kHz)
FREQUENCY_
SWITCH
REGISTER
VALUE (HEX.)
RECOMMENDED RECOMMENDED
MFR_IIN_
MFR_IIN_
OFFSETn
OFFSETn
SETTING (mA) SETTING (HEX.)
250
0xF3E8
20.3
0x8A99
350
0xFABC
24.4
0x8B20
425
0xFB52
27.4
0x8B82
500
0xFBE8
30.5
0x8BE7
575
0x023F
33.6
0x9227
650
0x028A
36.7
0x9259
750
0x02EE
40.8
0x929C
1000
0x03E8
51.0
0x9344
Sync. to
External Clock,
fSYNC
0x0000
0.041 • fSYNC +
10.037
*
*See LTC3880 data sheet, L11 data format.
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTM4676 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <
VOUTn
VINn • fOSC
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTM4676 is 90ns, nominal,
guardband to 130ns.
Variable Delay Time, Soft-Start and Output
Voltage Ramping
The LTM4676 must enter its run state prior to soft-start.
The RUNn pins are released after the part initializes and
SVIN is greater than the VIN_ON threshold. If multiple
LTM4676s are used in an application, they should be
configured to share the same RUNn pins. They all hold
their respective RUNn pins low until all devices initialize
48
and SVIN exceeds the VIN_ON threshold for all devices.
The SHARE_CLK pin assures all the devices connected to
the signal use the same time base.
After the RUNn pin releases, the controller waits for the
user-specified turn-on delay (TON_DELAYn) prior to initiating an output voltage ramp. Multiple LTM4676s and
other LTC parts can be configured to start with variable
delay times. To work correctly, all devices use the same
timing clock (SHARE_CLK) and all devices must share
the RUNn pin. This allows the relative delay of all parts to
be synchronized. The actual variation in the delay will be
dependent on the highest clock rate of the devices connected to the SHARE_CLK pin (all Linear Technology ICs
are configured to allow the fastest SHARE_CLK signal to
control the timing of all devices). The SHARE_CLK signal
can be ±7.5% in frequency, thus the actual time delays
will have some variance.
Soft-start is performed by actively regulating the load
voltage while digitally ramping the target voltage from 0V
to the commanded voltage set point. The rise time of the
voltage ramp can be programmed using the TON_RISEn
command to minimize inrush currents associated with the
start-up voltage ramp. The soft-start feature is disabled
by setting TON_RISEn to any value less than 0.250ms.
The LTM4676 performs the necessary math internally to
assure the voltage ramp is controlled to the desired slope.
However, the voltage slope can not be any faster than the
fundamental limits of the power stage. The number of steps
in the ramp is equal to TON_RISE/0.1ms. Therefore, the
shorter the TON_RISEn time setting, the more jagged the
soft-start ramp appears.
The LTM4676 PWM always operates in discontinuous
mode during the TON_RISEn operation. In discontinuous
mode, the bottom MOSFET (MBn) is turned off as soon
as reverse current is detected in the inductor. This allows
the regulator to start up into a pre-biased load.
There is no analog tracking feature in the LTM4676; however, two outputs can be given the same TON_RISEn and
TON_DELAYn times to achieve ratiometric rail tracking.
Because the RUNn pins are released at the same time and
both units use the same time base (SHARE_CLK), the
outputs track very closely. If the circuit is in a PolyPhase
configuration, all timing parameters must be the same.
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Applications Information
Coincident rail tracking can be achieved by setting two
outputs to have the same turn-on/off slew rates, identical
turn-on delays, and appropriately chosen turn-off delays:
VOUT _COMMANDRAIL1 VOUT _COMMANDRAIL2
=
TON_RISERAIL1
TON_RISERAIL2
and
VOUT _COMMANDRAIL1 VOUT _COMMANDRAIL2
=
TOFF _FALLRAIL1
TOFF _FALLRAIL2
and
TON_DELAYRAIL1 = TON_DELAYRAIL2
and (if VOUT_COMMANDRAIL2 ≥ VOUT_COMMANDRAIL1)
TOFF _DELAYRAIL1 =
 VOUT _COMMANDRAIL1 
TOFF _DELAYRAIL2 +  1–
 VOUT _COMMANDRAIL2 
•TOFF _FALLRAIL2
or else (VOUT_COMMANDRAIL2 < VOUT_COMMANDRAIL1)
TOFF _DELAYRAIL2 =
 VOUT _COMMANDRAIL2 
TOFF _DELAYRAIL1 +  1–
 VOUT _COMMANDRAIL1 
complimented with an externally applied capacitor between
GPIOn and ground—to further filter the waveform. The RC
time-constant of the filter should be set sufficiently fast
to assure no appreciable delay is incurred. For most applications, a value of 300µs to 500µs will provide sufficient
filtering without significantly delaying the trigger event.
Digital Servo Mode
For maximum accuracy in the regulated output voltage,
enable the digital servo loop by asserting bit 6 of the
MFR_PWM_MODEn command. In digital servo mode,
the LTM4676 adjusts the regulated output voltage
based on the ADC voltage reading. Every 100ms the
digital servo loop steps the LSB of the DAC (nominally
1.375mV or 0.6875mV depending on the voltage range
bit, MFR_PWM_CONFIG[6-n]) until the output is at the
correct ADC reading. At power-up this mode engages after
TON_MAX_FAULT_LIMITn unless the limit is set to 0 (infinite). If the TON_MAX_FAULT_LIMITn is set to 0 (infinite),
the servo begins after TON_RISEn is complete and VOUTn
has exceeded VOUT_UV_FAULT_LIMITn and IOUT_OCn
is not present. This same point in time is when the output
changes from discontinuous to the mode commanded by
MFR_PWM_MODEn [1:0]. Refer to Figure 3 for details on
the VOUTn waveform under time based sequencing.
•TOFF _FALLRAIL1
The described method of start-up sequencing is time based.
For concatenated events it is possible to control the RUN
pin based on the GPIOn pin of a different controller (see
Figure 2). The GPIOn pin can be configured to release
when the output voltage of the converter is greater than
the VOUT_UV_FAULT_LIMITn. It is recommended to use
the unfiltered VOUT UV fault limit because there is little appreciable time delay between the converter crossing the UV
threshold and the GPIOn pin releasing. The unfiltered output
can be enabled by the MFR_GPIO_PROPAGATEn[12] setting. (Refer to the MFR section of the PMBus commands
in the LTC3880 data sheet). The unfiltered signal may
have some glitching as the VOUT signal transitions through
the comparator threshold. A small digital filter of 250µs
internally deglitches the GPIOn pins. If the TON_RISE
time is greater than 100ms, the deglitch filter should be
RUNn
DIGITAL SERVO
MODE ENABLED FINAL OUTPUT
VOLTAGE REACHED
TON_MAX_FAULT_LIMITn
VOUT_UV_FAULT_LIMITn
DAC VOLTAGE
ERROR (NOT
TO SCALE)
VOUTn
TON_DELAYn
TON_RISEn
TIME DELAY OF
MANY SECONDS
TIME
4676 F03
Figure 3. Timing Controlled VOUT Rise
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LTM4676
Applications Information
If the TON_MAX_FAULT_LIMITn is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSEn is set to
ignore (0x00), the servo begins:
1.After the TON_RISEn sequence is complete
2.After the TON_MAX_FAULT_LIMITn time is reached;
and
3.After the VOUT_UV_FAULT_LIMITn has been exceed
or the IOUT_OC_FAULT_LIMITn is no longer active.
If the TON_MAX_FAULT_LIMITn is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSEn is not set
to ignore (0X00), the servo begins:
1.After the TON_RISEn sequence is complete;
2.After the TON_MAX_FAULT_LIMITn time has expired
and both VOUT_UV_FAULTn and IOUT_OC_FAULTn are
not present.
The maximum rise time is limited to 1.3 seconds.
In a PolyPhase configuration it is recommended only one
of the control loops have the digital servo mode enabled.
This will assure the various loops do not work against each
other due to slight differences in the reference circuits.
Soft Off (Sequenced Off)
In addition to a controlled start-up, the LTM4676 also
supports controlled turn-off. The TOFF_DELAYn and
TOFF_FALLn functions are shown in Figure 4. TOFF_FALLn
is processed when the RUNn pin goes low or if the module
is commanded off. If the module faults off or GPIOn is
pulled low externally and the module is programmed to
RUNn
VOUTn
TOFF_DELAYn
TOFF_FALLn
TIME
Figure 4. TOFF_DELAYn and TOFF_FALLn
50
4676 F04
respond to this (MFR_GPIO_RESPONSEn = 0xC0), the
output three-states (becomes high impedance) rather than
exhibiting a controlled ramp. The output then decays as
a function of the load.
The output voltage operates as shown in Figure 4 so long as
the part is in forced continuous mode and the TOFF_FALLn
time is sufficiently slow that the power stage can achieve
the desired slope. The TOFF_FALLn time can only be met if
the power stage and controller can sink sufficient current
to assure the output is at zero volts by the end of the fall
time interval. If the TOFF_FALLn time is set shorter than
the time required to discharge the load capacitance, the
output will not reach the desired zero volt state. At the end
of TOFF_FALLn, the controller ceases to sink current and
VOUTn decays at the natural rate determined by the load
impedance. If the controller is in discontinuous mode, the
controller does not pull negative current and the output
becomes pulled low by the load, not the power stage. The
maximum fail time is limited to 1.3 seconds. The number of
steps in the ramp is equal to TOFF_FALL/0.1ms.Therefore,
the shorter the TOFF_FALLn setting, the more jagged the
TOFF_FALLn ramp appears.
Undervoltage Lockout
The LTM4676 is initialized by an internal threshold-based
UVLO where SVIN must be approximately 4V and INTVCC,
VDD33, VDD25 must be within approximately 20% of the
regulated values. In addition, VDD33 must be within approximately 7% of the targeted value before the LTM4676
releases its RUNn pins. After the part has initialized, an
additional comparator monitors SVIN. The VIN_ON threshold must be exceeded before the power sequencing can
begin. When SVIN drops below the VIN_OFF threshold,
the LTM4676 pulls its RUNn pins low and SVIN must increase above the VIN_ON threshold before the controller
will restart. The normal start-up sequence will be allowed
after the VIN_ON threshold is crossed.
It is possible to program the contents of the NVM in
the application if the VDD33 supply is externally driven.
This activates the digital portion of the LTM4676
without engaging the high voltage sections. PMBus
communications are valid in this supply configuration. If SVIN has not been applied to the LTM4676,
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MFR_COMMON[3] will be asserted low, indicating that
NVM has not initialized. If this condition is detected, the
part will only respond to addresses 0x5A and 0x5B. To
initialize the part issue the following set of commands:
global address 0x5B command 0xBD data 0x2B followed
by global address 0x5B command 0xBD and data 0xC4.
The part will now respond to the correct address. Configure the part as desired then issue a STORE_USER_ALL.
When SVIN is applied a MFR_RESET command must be
issued to allow the PWM to be enabled and valid ADC
conversions to be read.
Fault Conditions
The LTM4676 GPIOn pins are configurable to indicate a
variety of faults including OV/UV, OC, OT, timing faults, peak
overcurrent faults. In addition the GPIOn pins can be pulled
low by external sources to indicate to the LTM4676 the
presence of a fault in some other portion of the system.
The fault response is configurable and allow the following options:
Ignore
n
Shut Down Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAYn
n
Refer to the PMBus section of the LTC3880 data sheet
and the PMBus specification for more details.
The OV response is automatic and rapid. If an OV is detected, MTn is turned off and BGn is turned on, until the
OV condition clears.
Fault logging is available on the LTM4676. The fault logging is configurable to automatically store data when a
fault occurs that causes the unit to fault off. The header
portion of the fault logging table contains peak values. It
is possible to read these values at any time. This data will
be useful while troubleshooting the fault.
If the LTM4676 internal temperature is in excess of 85°C
or below 0°C, the write into the NVM is not recommended.
The data will still be held in RAM, unless the 3.3V supply
UVLO threshold is reached. If the die temperature exceeds
130°C all NVM communication is disabled until the die
temperature drops below 125°C.
Open-Drain Pins
The LTM4676 has the following open-drain pins:
3.3V Pins
1. GPIOn
2. SYNC
3. SHARE_CLK
5V Pins (compatible with 3.3V digital logic thresholds)
1. RUNn
2. ALERT
3. SCL
4. SDA
All the above pins have on-chip pull-down transistors
that can sink 3mA at 0.4V. The low threshold on the
pins is 1.4V; thus, plenty of margin on the digital signals
with 3mA of current. For 3.3V pins, 3mA of current is
a 1.1k resistor. Unless there are transient speed issues
associated with the RC time constant of the resistor pullup and parasitic capacitance to ground, a 10k resistor or
larger is generally recommended.
For high speed signals such as the SDA, SCL and SYNC,
a lower value resistor may be required. The RC time constant should be set to 1/3 to 1/5 the required rise time
to avoid timing issues. For a 100pF load and a 400kHz
PMBus communication rate, the rise time must be less
than 300ns. The resistor pull-up on the SDA and SCL pins
with the time constant set to 1/3 the rise time:
RPULLUP =
tRISE
= 1k
3 •100pF
Be careful to minimize parasitic capacitance on the SDA and
SCL pins to avoid communication problems. To estimate
the loading capacitance, monitor the signal in question
and measure how long it takes for the desired signal to
reach approximately 63% of the output value. This is one
time constant.
The SYNC pin has an on-chip pull-down transistor with
the output held low for nominally 500ns. If the internal
oscillator is set for 500kHz and the load is 100pF and a
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LTM4676
Applications Information
3x time constant is required, the resistor calculation is
as follows:
RPULLUP =
2µs – 500ns
= 5k
3 •100pF
The closest 1% resistor is 4.99k.
If timing errors are occurring or if the SYNC frequency is
not as fast as desired, monitor the waveform and determine
if the RC time constant is too long for the application. If
possible reduce the parasitic capacitance. If not reduce
the pull up resistor sufficiently to assure proper timing.
Phase-Locked Loop and Frequency
Synchronization
The LTM4676 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. The PLL is locked to the falling edge of
the SYNC pin. The phase relationship between channel 0,
channel 1 and the falling edge of SYNC is controlled by
the lower 3 bits of the MFR_PWM_CONFIG command. For
PolyPhase applications, it is recommended all the phases
be spaced evenly. Thus for a 2-phase system the signals
should be 180° out of phase and a 4-phase system should
be spaced 90°.
The phase detector is an edge-sensitive digital type that
provides a known phase shift between the external and
internal oscillators. This type of phase detector does not
exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complementary current sources that charge or discharge the internal
filter network. The PLL lock range is guaranteed between
225kHz and 1.1MHz.
The PLL has a lock detection circuit. If the PLL should lose
lock during operation, bit 4 of the STATUS_MFR_SPECIFIC
command is asserted and the ALERT pin is pulled low.
The fault can be cleared by writing a 1 to the bit. If the
user does not wish to see the PLL_FAULT, even if a
synchronization clock is not available at power up, bit 3
of the MFR_CONFIG_ALL command must be asserted.
If the SYNC signal is not clocking in the application, the
PLL runs at the lowest free running frequency of the VCO.
This will be well below the intended PWM frequency of
the application and may cause undesirable operation of
the converter.
If the PWM (SWn) signal appears to be running at too high
a frequency, monitor the SYNC pin. Extra transitions on the
falling edge will result in the PLL trying to lock on to noise
instead of the intended signal. Review routing of digital
control signals and minimize crosstalk to the SYNC signal
to avoid this problem. Multiple LTM4676s are required to
share the SYNC pin in PolyPhase configurations; for other
configurations, it is optional. If the SYNC pin is shared between LTM4676s, only one LTM4676 can be programmed
with a frequency output. All the other LTM4676s must be
configured for external clock (FREQUENCY_SWITCH =
0x0000, and/or see Table 4).
RCONFIG Pin-Straps (External Resistor
Configuration Pins)
The LTM4676 default NVM is programmed to respect
the RCONFIG pins. If a user wishes the output voltage,
PWM frequency and phasing and the address to be set
without programming the part or purchasing specially
programmed parts, the RCONFIG pins can be used to
establish these parameters—provided MFR_CONFIG_
ALL[6] = 0b. The RCONFIG pins only require a resistor
terminating to SGND of the LTM4676. The RCONFIG pins
are only monitored at initial power up and during a reset
(MFR_RESET) so modifying their values perhaps using a
DAC after the part is powered will have no effect. To assure
proper operation, the value of RCONFIG resistors applied
to the LTM4676 pin-strapping pins must not deviate more
than ±3% away from the target nominal values indicated
in lookup Tables 2 to 5, over the lifetime of the product.
Thin film, 1% tolerance (or better), ±50ppm/°C-T.C.R.
rated (or better) resistors from vendors such as KOA
Speer, Panasonic, Vishay and Yageo are good candidates.
Noisy clock signals should not be routed near these pins.
Voltage Selection
When an output voltage is set using the RCONFIG pins on
VOUTn_CFG and VTRIMn_CFG (MFR_CONFIG_ALL[6] =
52
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0b), the following parameters are set as a percentage of
the output voltage:
• VOUT_OV_FAULT_LIMIT
+10%
• VOUT_OV_WARN+7.5%
• VOUT_MAX+7.5%
• VOUT_MARGIN_HI+5%
• POWER_GOOD_ON–7%
• POWER_GOOD_OFF–8%
• VOUT_MARGIN_LO–5%
• VOUT_UV_WARN
–6.5%
• VOUT_UV_FAULT_LIMIT
–7%
Connecting the USB to the I2C/SMBus/PMBus
Controller to the LTM4676 In System
The LTC USB to I2C/SMBus/PMBus controller can be
interfaced to the LTM4676 on the user’s board for programming, telemetry and system debug. The controller,
when used in conjunction with LTpowerPlay, provides a
powerful way to debug an entire power system. Faults are
MODULE PROGRAMMING
AND COMMUNICATION
INTERFACE HEADER
SEE TABLES 9-13 FOR
CONNECTOR AND
PINOUT OPTIONS
quickly diagnosed using telemetry, fault status registers
and the fault log. The final configuration can be quickly
developed and stored to the LTM4676 EEPROM.
Figures 5 and 6 illustrate the application schematics for
powering, programming and communicating with one or
more LTM4676s via the LTC I2C/SMBus/PMBus controller
regardless of whether or not system power is present.
If system power is not present the dongle will power
the LTM4676 through the VDD33 supply pin. To initialize
the part when SVIN is not applied and the VDD33 pin is
powered use global address 0x5B command 0xBD data
0x2B followed by address 0x5B command 0xBD data
0xC4. The part can now be communicated with, and the
project file updated. To write the updated project file to
the NVM issue a STORE_USER_ALL command. When
SVIN is applied, a MFR_RESET must be issued to allow
the PWM to be enabled and valid ADCs to be read.
Because of the controllers limited current sourcing
capability, only the LTM4676s, their associated pull-up
resistors and the I2C pull-up resistors should be powered
from the ORed 3.3V/3.4V supply. In addition, any device
sharing the I2C bus connections with the LTM4676 must
not have body diodes between the SDA/SCL pins and
VIN
100k
100k
SVIN
ISOLATED 3.4V
(USUALLY NEEDED)
SCL
TP0101K
SOT-23
SDA
VDD33
10k
10k
TO LTC DC2086 DIGITAL
POWER PROGRAMMING
ADAPTER (REQUIRES LTC
DC1613 USB TO I2C/SMBus/
PMBus CONTROLLER)
VGS MAX ON THE TP0101K IS 8V. IF VIN > 16V,
CHANGE THE RESISTOR DIVIDER ON THE PFET GATE
ALTERNATE PFETS/PACKAGES:
SOT-723: GOOD-ARK SEMI SSF2319GE
ON SEMI NTK3139PT1G
ROHM RZM002P02T2L
SOT-523: DIODES INC. DMG1013T-7
GOOD-ARK SEMI SSF2319GD
SOT-563: DIODES INC. DMP2104V-7
ON SEMI NTZS3151PT1G
SOT-323: DIODES INC. DMG1013UW-7
ON SEMI NTS2101PT1G
VISHAY Si1303DL-T1-E3
VDD25
LTM4676
SCL
SDA
WP SGND
SVIN
TP0101K
SOT-23
•
•
•
VDD33
VDD25
LTM4676
SCL
SDA
WP SGND
•
•
•
4676 F05
Figure 5. Circuit Suitable for Programming EEPROM/NVM of LTM4676 and Other LTC
PSM Modules/ICs in Vast Systems, Even When VIN Power Is Absent, 0°C < TJ ≤ 85°C
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LTM4676
Applications Information
MODULE PROGRAMMING
AND COMMUNICATION
INTERFACE HEADER
SEE TABLES 9-13 FOR
CONNECTOR AND
PINOUT OPTIONS
VIN
SVIN
ISOLATED 3.4V
(USUALLY NEEDED)
SCL
VDD33
D1
SOD882
SDA
TO LTC DC2086 DIGITAL
POWER PROGRAMMING
ADAPTER (REQUIRES LTC
DC1613 USB TO I2C/SMBus/
PMBus CONTROLLER)
10k
10k
D2
SOD882
SCL
SDA
WP SGND
SVIN
VDD33
•
•
•
D1, D2: NXP PMEG2005AEL OR PMEG2005AELD.
DIODE SELECTION IS NOT ARBITRARY.
USE VF < 210mV AT IF = 20mA
VDD25
LTM4676
VDD25
LTM4676
SCL
SDA
WP SGND
•
•
•
4676 F06
Figure 6. Circuit Suitable for Programming EEPROM/NVM of LTM4676 and Other LTC PSM
Modules/ICs in Vast Systems, Even When VIN Power Is Absent, TA > 20°C and TJ < 85°C
their respective VDD node because this will interfere with
bus communication in the absence of system power. In
Figure 5, the dongle will not bias the LTM4676s when
SVIN is present. It is recommended the RUNn pins be held
low to avoid providing power to the load until the part is
fully configured.
The LTC controller/adapter I2C connections are optoisolated from the PC USB. The 3.3V/3/4V from the
controller/adapter and the LTM4676 VDD33 pin must be
driven to each LTM4676 with a separate PFET or diode,
according to Figures 5 and 6. Only when SVIN is not applied is it permissible for the VDD33 pins to be electrically
in parallel because the INTVCC LDO is off. The DC1613’s
3.3V current limit is 100mA but typical VDD33 currents are
under 15mA. The VDD33 does back drive the INTVCC pin.
Normally this is not an issue if SVIN is open. The DC2086
is capable of delivering 3.4V at 2A.
Using a 4-pin header in Figure 5 or 6 maximizes flexibility
to alter the LTM4676’s NVM contents at any stage of the
user’s product development and production cycles. If
the LTM4676’s NVM is “pre-programmed”, i.e., contains
its finalized configuration, prior to being soldered to the
user’s PCB/motherboard—or, if other means have been
54
provided for altering the LTM4676's NVM contents in the
user’s system—then the 3.3V/3.4V pin on the header is
not needed, and a 3-pin header is sufficient to establish
GUI communications. The LTM4676 can be purchased
with customized NVM contents; consult factory for details.
Alternatively, the NVM contents of the LTM4676 can be
configured in a mass production environment by designing for it in ICT (in-circuit test), or by providing a means
of applying SVIN while holding the LTM4676’s RUN pins
low. Communication to the module must be made possible
via the SCL and SDA pins/nets in all NVM programming
scenarios. Recommended headers are found in Tables 9
and 10.
LTpowerPlay: An Interactive GUI for Digital
Power System Management
LTpowerPlay is a powerful Windows-based development
environment that supports Linear Technology digital
power ICs including the LTM4676. The software supports a variety of different tasks. LTpowerPlay can be
used to evaluate Linear Technology ICs by connecting to
a demo board or the user application. LTpowerPlay can
also be used in an offline mode (with no hardware pres4676fd
For more information www.linear.com/LTM4676
LTM4676
Applications Information
Table 9. 4-Pin Headers, 2mm Pin-to-Pin Spacing, Gold Flash or Plating, Compatible with DC2086 Cables
MOUNTING
STYLE
INSERTION
ANGLE
INTERFACE STYLE
Shrouded and Keyed Header
Vertical
Non Shrouded, Non-Keyed Header
Shrouded and Keyed Header
Surface Mount
Right Angle
Vertical
Through-Hole
Right Angle
Non Shrouded. Cable-to-Header/PCB
Mechanics Yield Keying Effect
Shrouded and Keyed Header
Non Shrouded, Non-Keyed Header
Shrouded and Keyed Header
Non Shrouded. Cable-to-Header/PCB
Mechanics Yield Keying Effect
VENDOR PART NUMBER
Hirose DF3DZ-4P-2V(51)
DF3DZ-4P-2V(50)
DF3Z-4P-2V(50)
3M
951104-2530-AR-PR
Hirose DF3DZ-4P-2H(51)
DF3DZ-4P-2H(50)
FCI
10112684-G03-04ULF
Hirose
Harwin
Samtec
Sullins
Hirose
Norcomp
Harwin
Samtec
DF3-4P-2DSA(01)
M22-2010405
TMM-104-01-LS
NRPN041PAEN-RC
DF3-4P-2DS(01)
27630402RP2
M22-2030405
TMM-104-01-L-S-RA
PINOUT STYLE (SEE TABLE 11)
Type A
Type A and B Supported. Reversible/Not Keyed
Type A
Type B. Keying Achieved by PCB Surface
Type A
Type A and B Supported. Reversible/Not Keyed
Type A
Type B. Keying Achieved by Intentional PCB
Interference
Table 10. 3-Pin Headers, 2mm Pin-to-Pin Spacing, Gold Flash or Plating, Compatible with DC2086 Cables
MOUNTING
STYLE
INSERTION
ANGLE
INTERFACE STYLE
Shrouded and Keyed Header
Vertical
Non Shrouded, Non-Keyed Header
Shrouded and Keyed Header
Surface Mount
Right Angle
Vertical
Through-Hole
Right Angle
Non Shrouded. Cable-to-Header/PCB
Mechanics Yield Keying Effect
Shrouded and Keyed Header
Non Shrouded, Non-Keyed Header
Shrouded and Keyed Header
Non Shrouded. Cable-to-Header/PCB
Mechanics Yield Keying Effect
VENDOR PART NUMBER
Hirose DF3DZ-3P-2V(51)
DF3DZ-3P-2V(50)
DF3Z-3P-2V(50)
3M
951103-2530-AR-PR
Hirose DF3DZ-3P-2H(51)
DF3DZ-3P-2H(50)
FCI
10112684-G03-03LF
Hirose
Harwin
Samtec
Sullins
Hirose
Norcomp
Harwin
Samtec
Table 11. Recommended 4-Pin Header Pinout (Pin Numbering Scheme
Adheres to Hirose Conventions). Interfaces to DC2086 Cables
PIN NUMBER
PINOUT STYLE “A”
(SEE TABLE 9)
PINOUT STYLE “B”
(SEE TABLE 9)
1
SDA
Isolated 3.3V/3.4V
2
GND
SCL
3
SCL
GND
4
Isolated 3.3V/3.4V
SDA
PINOUT STYLE (SEE TABLE 12)
Type A
Type A and B Supported. Reversible/Not Keyed
Type A
Type B. Keying Achieved by PCB Surface
DF3-3P-2DSA(01)
M22-2010305
TMM-103-01-LS
NRPN031PAEN-RC
DF3-3P-2DS(01)
27630302RP2
M22-2030305
TMM-103-01-L-S-RA
Type A
Type A and B Supported. Reversible/Not Keyed
Type A
Type B. Keying Achieved by Intentional PCB
Interference
Table 12. Recommended 3-Pin Header Pinout (Pin Numbering
Scheme Adheres to Hirose Conventions). Interfaces to DC2086
Cables
PIN NUMBER
PINOUT STYLE “A”
(SEE TABLE 10)
PINOUT STYLE “B”
(SEE TABLE 10)
1
SDA
SCL
2
GND
GND
3
SCL
SDA
4676fd
For more information www.linear.com/LTM4676
55
LTM4676
Applications Information
Table 13. 4-Pin Male-to-Male Shrouded and Keyed Adapter
(Optional. Eases Creation of Adapter Cables, if Deviating from
Recommended Connectors/Connector Pinouts). Interfaces to
DC2086 Cables
Vendor
Part Number
Website
Hirose
DF3-4EP-2A
www.hirose.com, www.hirose.co.jp
ent) in order to build multiple IC configuration files that
can be saved and reloaded at a later time. LTpowerPlay
provides unprecedented diagnostic and debug features.
It becomes a valuable diagnostic tool during board bringup to program or tweak the power system or to diagnose
power issues when bringing up rails. LTpowerPlay utilizes
Linear Technology’s USB-to-I2C/SMBus/PMBus controller
to communication with one of the many potential targets
including the DC1811A (single LTM4676) or DC1989 (dual,
triple, quad LTM4676) demo boards, or a customer target
system. The software also provides an automatic update
feature to keep the revisions current with the latest set of
device drivers and documentation. A great deal of context
sensitive help is available with LTpowerPlay along with
several tutorial demos. Complete information is available at
http://www.linear.com/ltpowerplay
PMBus Communication and Command
Processing
The LTM4676 has one deep buffer to hold the last data
written for each supported command prior to processing
as shown in Figure 8; Write Command Data Processing.
When the part receives a new command from the bus,
it copies the data into the Write Command Data Buffer,
indicates to the internal processor that this command
data needs to be fetched, and converts the command to
its internal format so that it can be executed.
Figure 7
56
4676fd
For more information www.linear.com/LTM4676
LTM4676
Applications Information
CMD
PMBus
WRITE
WRITE COMMAND
DATA BUFFER
DECODER
PAGE
CMDS
DATA
MUX
CALCULATIONS
PENDING
S
R
•
•
•
VOUT_COMMAND
0x00
0x21
•
•
•
MFR_RESET
INTERNAL
PROCESSOR
FETCH,
CONVERT
DATA
AND
EXECUTE
0xFD
x1
4676 F08
Figure 8. Write Command Data Processing
Two distinct parallel blocks manage command buffering
and command processing (fetch, convert, and execute)
to ensure the last data written to any command is never
lost. Command data buffering handles incoming PMBus writes by storing the command data to the Write
Command Data Buffer and marking these commands for
future processing. The internal processor runs in parallel
and handles the sometimes slower task of fetching, converting and executing commands marked for processing.
Some computationally intensive commands (e.g., timing
parameters, temperatures, voltages and currents) have
internal processor execution times that may be long
relative to PMBus timing. If the part is busy processing a
command, and new command(s) arrive, execution may
be delayed or processed in a different order than received.
The part indicates when internal calculations are in process
via bit 5 of MFR_COMMON (‘calculations not pending’).
When the part is busy calculating, bit 5 is cleared. When
this bit is set, the part is ready for another command. An
example polling loop is provided in Figure 8 which ensures
that commands are processed in order while simplifying
error handling routines.
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on part configuration it may either
NACK the command or return all ones (0xFF) for reads. It
may also generate a BUSY fault and ALERT notification,
or stretch the SCL clock low. For more information refer
to PMBus Specification v1.1, Part II, Section 10.8.7 and
SMBus v2.0 section 4.3.3. Clock stretching can be enabled
by asserting bit 1 of MFR_CONFIG_ALL. Clock stretching
will only occur if enabled and the bus communication
speed exceeds 100kHz.
PMBus busy protocols are well accepted standards, but
can make writing system level software somewhat complex. The part provides three ‘hand shaking’ status bits
which reduce complexity while enabling robust system
level communication.
The three hand shaking status bits are in the MFR_
COMMON register. When the part is busy executing an
internal operation, it will clear bit 6 of MFR_COMMON
(‘module not busy’). When the part is busy specifically
because it is in a transitional VOUT state (margining hi/lo,
power off/on, moving to a new output voltage set point,
etc.) it will clear bit 4 of MFR_COMMON (‘output not in
transition’). When internal calculations are in process, the
part will clear bit 5 of MFR_COMMON (‘calculations not
pending’). These three status bits can be polled with a
PMBus read byte of the MFR_COMMON register until all
three bits are set. A command immediately following the
status bits being set will be accepted without NACKing or
generating a BUSY fault/ALERT notification. The part can
NACK commands for other reasons, however, as required
by the PMBus spec (for instance, an invalid command or
data). An example of a robust command write algorithm
for the VOUT_COMMANDn register is provided in Figure 9.
// wait until bits 6, 5, and 4 of MFR_COMMON are all set
do
{
mfrCommonValue = PMBUS_READ_BYTE(0xEF);
partReady = (mfrCommonValue & 0x68) == 0x68;
}while(!partReady)
// now the part is ready to receive the next command
PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_COMMAND to 2V
Figure 9. Example of a Command Write of VOUT_COMMAND
It is recommended that all command writes (write byte,
write word, etc.) be preceded with a polling loop to avoid
the extra complexity of dealing with busy behavior and
unwanted ALERT notification. A simple way to achieve this
is by creating SAFE_WRITE_BYTE() and SAFE_WRITE_
WORD() subroutines. The above polling mechanism allows
one’s software to remain clean and simple while robustly
communicating with the part. For a detailed discussion
of these topics and other special cases please refer to
the application note section located at www.linear.com/
designtools/app_notes.
For more information www.linear.com/LTM4676
4676fd
57
LTM4676
Applications Information
When communicating using bus speeds at or below
100kHz, the polling mechanism shown here provides a
simple solution that ensures robust communication without
clock stretching. At bus speeds in excess of 100kHz, it is
strongly recommended that the part be configured to enable clock stretching. This requires a PMBus master that
supports clock stretching. System software that detects
and properly recovers from the standard PMBus NACK/
BUSY faults as described in the PMBus Specification v1.1,
Part II, Section 10.8.7 is required to communicate above
100kHz without clock stretching. Clock stretching will not
extend the PMBus speed beyond the specified 400kHz.
Thermal Considerations and
Output Current Derating
The thermal resistances reported in the Pin Configuration
section of this data sheet are consistent with those parameters defined by JESD51-12 and are intended for use
with finite element analysis (FEA) software modeling tools
that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on
a µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients is
found in JESD51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
Many designers may opt to use laboratory equipment and a
test vehicle such as the demo board to predict the µModule
regulator’s thermal performance in their application at
various electrical and environmental operating conditions
to compliment any FEA activities. Without FEA software,
the thermal resistances reported in the Pin Configuration
section are, in and of themselves, not relevant to providing
guidance of thermal performance. Instead, the derating
curves provided later in this data sheet can be used in
a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
The Pin Configuration section gives four thermal coefficients explicitly defined in JESD51-12. These coefficients
are quoted or paraphrased as follows:
58
1 θJA, the thermal resistance from junction to ambient, is
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a JESD51-9 defined test board, which may not reflect
an actual application.
2 θJCbottom, the thermal resistance from junction to the
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the package. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
3 θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top of
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4 θJB, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the
bottom of the µModule regulator and into the board,
and is really the sum of the θJCbottom and the thermal
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from the
package, using a two sided, two layer board. This board
is described in JESD51-9.
4676fd
For more information www.linear.com/LTM4676
LTM4676
Applications Information
A graphical representation of the aforementioned thermal
resistances is given in Figure 10; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom of the µModule package—as the standard defines
for θJCtop and θJCbottom, respectively. In practice, power
loss is thermally dissipated in both directions away from
the package. Granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4676, be aware there are multiple power
devices and components dissipating power, with a consequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—but
also, not ignoring practical realities—an approach has been
taken using FEA software modeling along with laboratory
testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values
supplied in this data sheet: (1) Initially, FEA software is
used to accurately build the mechanical geometry of the
LTM4676 and the specified PCB with all of the correct
material coefficients along with accurate power loss
source definitions; (2) this model simulates a softwaredefined JEDEC environment consistent with JESD51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the LTM4676 with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled environment
chamber while operating the device at the same power
loss as that which was simulated. The outcome of this
process and due diligence yields the set of derating curves
provided in later sections of this data sheet, along with
well-correlated JESD51-12-defined θ values provided in
the Pin Configuration section of this data sheet.
The 1V, 1.8V and 3.3V power loss curves in Figures 11, 12
and 13 respectively can be used in coordination with the load
current derating curves in Figures 14 to 31 for calculating
an approximate θJA thermal resistance for the LTM4676
with various heat sinking and air flow conditions. These
thermal resistances represent demonstrated performance
of the LTM4676 on DC1811A hardware; a 4-layer FR4 PCB
measuring 99mm × 113mm × 1.6mm using outer and inner
copper weights of 2oz and 1oz, respectively. The power loss
curves are taken at room temperature, and are increased
with multiplicative factors with ambient temperature.
These approximate factors are listed in Table 14.
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
4676 F10
µMODULE DEVICE
Figure 10. Graphical Representation of JESD51-12 Thermal Coefficients
4676fd
For more information www.linear.com/LTM4676
59
LTM4676
Applications Information
(Compute the factor by interpolation, for intermediate
temperatures.) The derating curves are plotted with the
LTM4676’s paralleled outputs initially sourcing up to
26A and the ambient temperature at 30°C. The output
voltages are 1V, 1.8V and 3.3V. These are chosen to
include the lower and higher output voltage ranges for
correlating the thermal resistance. Thermal models are
derived from several temperature measurements in a
controlled temperature chamber along with thermal
modeling analysis. The junction temperatures are
monitored while ambient temperature is increased with and
without air flow, and with and without a heat sink attached
with thermally conductive adhesive tape. The BGA heat
sinks evaluated in Table 18 (and attached to the LTM4676
with thermally conductive adhesive tape listed in Table 19)
yield very comparable performance in laminar airflow
despite being visibly different in construction and form
factor. The power loss increase with ambient temperature
change is factored into the derating curves. The junctions
are maintained at 120°C maximum while lowering output
current or power while increasing ambient temperature. The
decreased output current decreases the internal module
loss as ambient temperature is increased. The monitored
junction temperature of 120°C minus the ambient operating
temperature specifies how much module temperature rise
can be allowed. As an example in Figure  15, the load current
is derated to ~19A at ~80°C ambient with 400LFM airflow
and no heat sink and the room temperature (25°C) power
loss for this 12VIN to 1VOUT at 19AOUT condition is ~4W.
A 4.8W loss is calculated by multiplying the ~4W room
temperature loss from the 12VIN to 1VOUT power loss curve
60
at 19A (Figure 11), with the 1.2 multiplying factor at 80°C
ambient (from Table 14). If the 80°C ambient temperature
is subtracted from the 120°C junction temperature, then
the difference of 40°C divided by 4.8W yields a thermal
resistance, θJA, of 8.3°C/W—in good agreement with
Table 15. Tables 15, 16 and 17 provide equivalent thermal
resistances for 1V, 1.8V and 3.3V outputs with and without
air flow and heat sinking. The derived thermal resistances
in Tables 15, 16 and 17 for the various conditions can be
multiplied by the calculated power loss as a function of
ambient temperature to derive temperature rise above
ambient, thus maximum junction temperature. Room
temperature power loss can be derived from the efficiency
curves in the Typical Performance Characteristics section
and adjusted with ambient temperature multiplicative
factors from Table 14.
Table 14. Power Loss Multiplicative Factors vs Ambient
Temperature
AMBIENT TEMPERATURE
POWER LOSS MULTIPLICATIVE
FACTOR
Up to 40°C
1.00
50°C
1.05
60°C
1.10
70°C
1.15
80°C
1.20
90°C
1.25
100°C
1.30
110°C
1.35
120°C
1.40
4676fd
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LTM4676
Applications Information
Table 15. 1.0V Output
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
Figures 14, 15, 16
Figures 14, 15, 16
Figures 14, 15, 16
Figures 17, 18, 19
Figures 17, 18, 19
Figures 17, 18, 19
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
Figure 11
Figure 11
Figure 11
Figure 11
Figure 11
Figure 11
0
200
400
0
200
400
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
Figures 20, 21, 22
Figures 20, 21, 22
Figures 20, 21, 22
Figures 23, 24, 25
Figures 23, 24, 25
Figures 23, 24, 25
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
Figure 12
Figure 12
Figure 12
Figure 12
Figure 12
Figure 12
0
200
400
0
200
400
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
Figure 26, 27, 28
Figure 26, 27, 28
Figure 26, 27, 28
Figure 29, 30, 31
Figure 29, 30, 31
Figure 29, 30, 31
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
0
200
400
0
200
400
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
θJA (°C/W)
10.6
9.5
8.5
9.8
8.2
7.1
Table 16. 1.8V Output
θJA (°C/W)
10.7
9.4
8.4
9.9
8.3
7.1
Table 17. 3.3V Output
θJA (°C/W)
10.6
9.3
8.4
10.0
8.4
7.3
Table 18. Heat Sink Manufacturer (Thermally Conductive Adhesive Tape Pre-Attached)
HEAT SINK MANUFACTURER
PART NUMBER
WEBSITE
Aavid Thermalloy
375424B00034G
www.aavid.com
Cool Innovations
4-050503PT411
www.coolinnovations.com
Wakefield Engineering
LTN20069
www.wakefield.com
Table 19. Thermally Conductive Adhesive Tape Vendor
THERMALLY CONDUCTIVE ADHESIVE
TAPE MANUFACTURER
PART NUMBER
WEBSITE
Chomerics
T411
www.chomerics.com
4676fd
For more information www.linear.com/LTM4676
61
LTM4676
Applications Information
Table 20. LTM4676 Channel Output Voltage Response vs Component Matrix. 6.5A Load-Stepping at 6.5A/µs. Typical Measured Values
COUTH VENDORS PART NUMBER
COUTL
VENDORS
AVX
12106D107MAT2A (100µF, 6.3V, 1210 Case Size)
Sanyo POSCAP 6TPF330M9L (330µF, 6.3V, 9mΩ ESR, D3L Case Size)
Murata
GRM32ER60J107ME20L (100µF, 6.3V, 1210 Case Size) Sanyo POSCAP 6TPD470M (470µF, 6.3V, 10mΩ ESR, D4D Case Size)
Taiyo Yuden
JMK325BJ107MM-T (100µF, 6.3V, 1210 Case Size)
TDK
C3225X5R0J107MT (100µF, 6.3V, 1210 Case Size)
PART NUMBER
Sanyo POSCAP 2R5TPE470M9 (470µF, 2.5V, 9mΩ ESR, D2E Case Size)
FSWPHCFG
PINSTRAP,
CONNECT
RTHn CTHn
RESISTOR
(EXT (EXT
COUTLn
COMPn a TO
COUTHn
TO SGND
LOOP LOOP
(CERAMIC (BULK
COMPn b?
OUTPUT OUTPUT (INTERNAL LOOP COMP) COMP) fSW (Table 4)
VOUTn VINn
REF.
(kΩ)
(kΩ) (nF) (kHz)
CAP)
CAP)
COMP)
(V) (V) CIRCUIT*
VOUTn CFG
PINSTRAP
RESISTOR
TO SGND
(Table 2)
(kΩ)
VTRIMn CFG
PINSTRAP,
RESISTOR
TO SGND
(Table 3)
(kΩ)
TRANSIENT
DROOP
(0A TO
6.5A)
(mV)
PK-PK
DEVIATION
(0A TO RECOV6.5A
ERY
TO 0A) TIME
(mV)
(µs)
0.9
5
Test Ckt. 2 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
350
22.6
1.65
None
42
79
45
0.9
5
Test Ckt. 2 100µF × 3
330µF
No. Use RTH, CTH
4.12
2.2
350
22.6
1.65
None
91
162
40
0.9
12 Test Ckt. 1 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
350
22.6
1.65
None
42
79
45
0.9
12 Test Ckt. 1 100µF × 3
330µF
No. Use RTH, CTH
4.12
2.2
350
22.6
1.65
None
91
162
40
0.9
24 Test Ckt. 1 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
250
32.4
1.65
None
45
85
45
0.9
24 Test Ckt. 1 100µF × 3
330µF
No. Use RTH, CTH
4.12
2.2
350
22.6
1.65
None
94
165
40
1
5
Test Ckt. 2 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
350
22.6
2.43
0
44
85
45
1
5
Test Ckt. 2 100µF × 3
330µF
No. Use RTH, CTH
4.22
2.2
350
22.6
2.43
0
90
160
40
1
12 Test Ckt. 1 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
350
22.6
2.43
0
44
85
45
1
12 Test Ckt. 1 100µF × 3
330µF
No. Use RTH, CTH
4.22
2.2
350
22.6
2.43
0
90
160
40
1
24 Test Ckt. 1 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
250
32.4
2.43
0
47
90
45
1
24 Test Ckt. 1 100µF × 3
330µF
No. Use RTH, CTH
4.22
2.2
350
22.6
2.43
0
93
164
40
1.2
5
Test Ckt. 2 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
350
22.6
3.24
0
45
85
45
1.2
5
Test Ckt. 2 100µF × 3
330µF
No. Use RTH, CTH
4.42
2.2
350
22.6
3.24
0
89
149
40
1.2
12 Test Ckt. 1 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
350
22.6
3.24
0
45
85
45
1.2
12 Test Ckt. 1 100µF × 3
330µF
No. Use RTH, CTH
4.42
2.2
350
22.6
3.24
0
89
149
40
1.2
24 Test Ckt. 1 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
350
22.6
3.24
0
48
81
45
1.2
24 Test Ckt. 1 100µF × 3
330µF
No. Use RTH, CTH
4.42
2.2
350
22.6
3.24
0
92
154
40
1.5
5
Test Ckt. 2 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
350
22.6
4.22
None
45
85
45
1.5
5
Test Ckt. 2 100µF × 3
330µF
No. Use RTH, CTH
4.75
2.2
350
22.6
4.22
None
89
149
40
1.5
12 Test Ckt. 1 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
350
22.6
4.22
None
45
85
45
1.5
12 Test Ckt. 1 100µF × 3
330µF
No. Use RTH, CTH
4.75
2.2
350
22.6
4.22
None
89
149
40
1.5
24 Test Ckt. 1 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
425
18.0
4.22
None
48
91
45
1.5
24 Test Ckt. 1 100µF × 3
330µF
No. Use RTH, CTH
4.75
2.2
350
22.6
4.22
None
93
156
40
1.8
5
Test Ckt. 2 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
425
18.0
6.34
0
45
85
45
1.8
5
Test Ckt. 2 100µF × 3
330µF
No. Use RTH, CTH
4.99
2.2
500
None
6.34
0
88
144
40
1.8
12 Test Ckt. 1 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
500
None
6.34
0
45
85
45
1.8
12 Test Ckt. 1 100µF × 3
330µF
No. Use RTH, CTH
4.99
2.2
500
None
6.34
0
88
144
40
1.8
24 Test Ckt. 1 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
500
None
6.34
0
48
92
45
62
4676fd
For more information www.linear.com/LTM4676
LTM4676
Applications Information
Table 20. LTM4676 Channel Output Voltage Response vs Component Matrix. 6.5A Load-Stepping at 6.5A/µs. Typical Measured Values
FSWPHCFG
PINSTRAP,
CONNECT
RTHn CTHn
RESISTOR
(EXT (EXT
COUTLn
COMPn a TO
COUTHn
TO SGND
LOOP LOOP
(CERAMIC (BULK
COMPn b?
OUTPUT OUTPUT (INTERNAL LOOP COMP) COMP) fSW (Table 4)
VOUTn VINn
REF.
(kΩ)
(kΩ) (nF) (kHz)
CAP)
CAP)
COMP)
(V) (V) CIRCUIT*
VOUTn CFG
PINSTRAP
RESISTOR
TO SGND
(Table 2)
(kΩ)
VTRIMn CFG
PINSTRAP,
RESISTOR
TO SGND
(Table 3)
(kΩ)
TRANSIENT
DROOP
(0A TO
6.5A)
(mV)
PK-PK
DEVIATION
(0A TO RECOV6.5A
ERY
TO 0A) TIME
(mV)
(µs)
1.8
24 Test Ckt. 1 100µF × 3
330µF
No. Use RTH, CTH
4.99
2.2
500
None
6.34
0
94
158
40
2.5
5
Test Ckt. 2 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
425
18.0
10.7
None
46
86
45
2.5
5
Test Ckt. 2 100µF × 3
330µF
No. Use RTH, CTH
5.62
2.2
575
15.4
10.7
None
89
148
40
2.5
12 Test Ckt. 1 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
575
15.4
10.7
None
46
86
45
2.5
12 Test Ckt. 1 100µF × 3
330µF
No. Use RTH, CTH
5.62
2.2
575
15.4
10.7
None
90
150
40
2.5
24 Test Ckt. 1 100µF × 7
None
Yes, cf. Fig. 44
N/A
N/A
650
12.7
10.7
None
48
94
45
2.5
24 Test Ckt. 1 100µF × 3
330µF
No. Use RTH, CTH
5.62
2.2
650
12.7
10.7
None
92
154
40
3.3
5
Test Ckt. 2 100µF × 5
None
Yes, cf. Fig. 44
N/A
N/A
425
18.0
22.6
None
56
110
45
3.3
12 Test Ckt. 1 100µF × 5
None
Yes, cf. Fig. 44
N/A
N/A
650
12.7
22.6
None
60
112
45
3.3
24 Test Ckt. 1 100µF × 5
None
Yes, cf. Fig. 44
N/A
N/A
750
10.7
22.6
None
62
115
45
5**
12 Test Ckt. 1 100µF × 5
None
Yes, cf. Fig. 44
N/A
N/A
750
10.7
32.4
7.68
62
125
50
5**
24 Test Ckt. 1 100µF × 5
None
Yes, cf. Fig. 44
N/A
N/A
1000
9.09
32.4
7.68
65
130
50
*For all conditions: CINH input capacitance is 10µF × 3, per channel (VIN0, VIN1). CINL bulk input capacitance of 150µF is optional if VIN has very low input
impedance.
**5VOUT supported on VOUT1 channel output, only. VOUT0 channel supported range of output voltage regulation is limited to 4VOUT, max. Exception for
dual phase single output operation shown in Figure 42.
Applications Information—Derating Curves
See also Figure 43, 12VIN to 5VOUT derating curves.
8
10
7
9
24VIN
12VIN
3
5VIN
6
5
4
3
2
1
0
7
POWER LOSS (W)
POWER LOSS (W)
POWER LOSS (W)
5
2
12
8
6
4
14
24VIN
12VIN
5VIN
4676 F11
Figure 11. 1VOUT Power Loss Curve
0
8
6
4
24VIN
12VIN
5VIN
2
1
0 2 4 6 8 10 12 14 16 18 20 22 24 26
OUTPUT CURRENT (A)
10
0 2 4 6 8 10 12 14 16 18 20 22 24 26
OUTPUT CURRENT (A)
4676 F12
Figure 12. 1.8VOUT Power Loss Curve
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26
OUTPUT CURRENT (A)
4676 F13
Figure 13. 3.3VOUT Power Loss Curve
4676fd
For more information www.linear.com/LTM4676
63
LTM4676
40
30
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
MAXIMUM LOAD CURRENT (A)
400LFM
200LFM
0LFM
26
24
22
20
18
16
14
12
10
8
6
4
2
0
400LFM
200LFM
0LFM
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4676 F14
40
30
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
26
24
22
20
18
16
14
12
10
8
6
4
2
0
400LFM
200LFM
0LFM
40
30
30
40
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
4676 F20
Figure 20. 5V to 1.8V Derating
Curve, No Heat Sink
64
26
24
22
20
18
16
14
12
10
8
6
4
2
0
400LFM
200LFM
0LFM
40
30
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4676 F19
Figure 18. 12V to 1V Derating
Curve, with Heat Sink
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4676 F18
Figure 17. 5V to 1V Derating
Curve, with Heat Sink
400LFM
200LFM
0LFM
40
Figure 16. 24V to 1V Derating
Curve, No Heat Sink
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4676 F17
26
24
22
20
18
16
14
12
10
8
6
4
2
0
30
4676 F16
MAXIMUM LOAD CURRENT (A)
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
Figure 15. 12V to 1V Derating Curve,
No Heat Sink
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
26
24
22
20
18
16
14
12
10
8
6
4
2
0
26
24
22
20
18
16
14
12
10
8
6
4
2
0
4676 F15
Figure 14. 5V to 1V Derating
Curve, No Heat Sink
26
24
22
20
18
16
14
12
10
8
6
4
2
0
Figure 19. 24V to 1V Derating
Curve, with Heat Sink
MAXIMUM LOAD CURRENT (A)
26
24
22
20
18
16
14
12
10
8
6
4
2
0
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
Applications Information—Derating Curves
400LFM
200LFM
0LFM
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4676 F21
Figure 21. 12V to 1.8V Derating
Curve, No Heat Sink
26
24
22
20
18
16
14
12
10
8
6
4
2
0
400LFM
200LFM
0LFM
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4676 F22
Figure 22. 24V to 1.8V Derating
Curve, No Heat Sink
4676fd
For more information www.linear.com/LTM4676
LTM4676
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4676 F23
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
26
24
22
20
18
16
14
12
10
8
6
4
2
0
400LFM
200LFM
0LFM
30
40
40
MAXIMUM LOAD CURRENT (A)
26
24
22
20
18
16
14
12
10
8
6
4
2
0
4676 F29
Figure 29. 5V to 3.3V Derating
Curve, with Heat Sink
26
24
22
20
18
16
14
12
10
8
6
4
2
0
400LFM
200LFM
0LFM
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4676 F30
Figure 30. 12V to 3.3V Derating
Curve, with Heat Sink
For more information www.linear.com/LTM4676
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
400LFM
200LFM
0LFM
30
40
4676 F27
MAXIMUM LOAD CURRENT (A)
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
40
Figure 25. 24V to 1.8V Derating
Curve, with Heat Sink
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4676 F28
Figure 28. 24V to 3.3V Derating
Curve, No Heat Sink
Figure 27. 12V to 3.3V Derating
Curve, No Heat Sink
400LFM
200LFM
0LFM
30
30
4676 F25
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4676 F26
Figure 26. 5V to 3.3V Derating
Curve, No Heat Sink
26
24
22
20
18
16
14
12
10
8
6
4
2
0
400LFM
200LFM
0LFM
Figure 24. 12V to 1.8V Derating
Curve, with Heat Sink
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
400LFM
200LFM
0LFM
26
24
22
20
18
16
14
12
10
8
6
4
2
0
4676 F24
Figure 23. 5V to 1.8V Derating
Curve, with Heat Sink
26
24
22
20
18
16
14
12
10
8
6
4
2
0
MAXIMUM LOAD CURRENT (A)
400LFM
200LFM
0LFM
MAXIMUM LOAD CURRENT (A)
400LFM
200LFM
0LFM
26
24
22
20
18
16
14
12
10
8
6
4
2
0
MAXIMUM LOAD CURRENT (A)
26
24
22
20
18
16
14
12
10
8
6
4
2
0
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
Applications Information—Derating Curves
26
24
22
20
18
16
14
12
10
8
6
4
2
0
400LFM
200LFM
0LFM
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4676 F31
Figure 31. 24V to 3.3V Derating
Curve, with Heat Sink
4676fd
65
LTM4676
Applications Information
Connecting an optional series RC network from SWn to
GND can dampen high frequency (~30MHz+) switch node
ringing caused by parasitic inductances and capacitances
in the switched-current paths. The RC network is called
a snubber circuit because it dampens (or “snubs”) the
resonance of the parasitics, at the expense of higher
power loss.
To use a snubber, choose first how much power to allocate
to the task and how much PCB real estate is available to
implement the snubber. For example, if PCB space allows a low inductance 1W resistor to be used—derated
conservatively to 600mW (PSNUB)—then the capacitor in
the snubber network (CSW) is computed by:
CSW =
PSNUB
VINn(MAX)2 • fSW
where VINn(MAX) is the maximum input voltage that the
input to the power stage (VINn ) will see in the application,
and fSW is the DC/DC converter’s switching frequency
of operation. CSW should be NPO, C0G or X7R-type (or
better) material.
The snubber resistor (RSW) value is then given by:
RSW =
5nH
CSW
The snubber resistor should be low ESL and capable of
withstanding the pulsed currents present in snubber circuits. A value between 0.7Ω and 4.2Ω is normal.
For ease of snubber implementation, integrated 2.2nF
snubber capacitors connect to each of the LTM4676’s
channel switch nodes via a low inductance path. The
electrically floating ends of these snubber capacitors are
made available on the SNUBn pins of the LTM4676. Using the aforementioned guidance on snubber selection,
a properly sized snubber resistor can be conveniently
connected directly between SNUBn and GND.
66
70
60
SIGNAL AMPLITUDE (dB µV/m)
The SWn pin provides access to the midpoint of the power
MOSFETs in LTM4676’s power stages.
EMI performance of LTM4676 (on DC1811A) with and
without a snubber is compared and contrasted in Figures 32
and 33. The snubber resistors applied to the SNUBn pins
reduce EMI signal amplitude by several dBµV/m.
50
40
30
20
10
0
–10
30
226.2
814.8
422.4 618.6
FREQUENCY (MHz)
1010
4676 F32
Figure 32. Radiated Emissions Scan of LTM4676 Producing
1VOUT at 26A, from 12VIN. DC1811A Hardware with Outputs
Paralleled. No Snubbers Applied. fSW = 350kHz. Measured
in a 10m Chamber. Peak Detect Method
70
60
SIGNAL AMPLITUDE (dB µV/m)
EMI Performance
50
40
30
20
10
0
–10
30
226.2
814.8
422.4 618.6
FREQUENCY (MHz)
1010
4676 F33
Figure 33. Radiated Emissions Scan of LTM4676 Producing
1VOUT at 26A, from 12VIN. DC1811A Hardware with Outputs
Paralleled. 1Ω (1/4W rated) Snubber Resistors Applied
from SNUBn to GND. fSW = 350kHz. Measured in a 10m
Chamber. Peak Detect Method
4676fd
For more information www.linear.com/LTM4676
LTM4676
Applications Information
Safety Considerations
The LTM4676 modules do not provide galvanic isolation
from VIN to VOUT. There is no internal fuse. If required,
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure.
The fuse or circuit breaker should be selected to limit the
current to the regulator during overvoltage in case of an
internal top MOSFET fault. If the internal top MOSFET fails,
then turning it off will not resolve the overvoltage, thus the
internal bottom MOSFET will turn on indefinitely trying to
protect the load. Under this fault condition, the input voltage will source very large currents to ground through the
failed internal top MOSFET and enabled internal bottom
MOSFET. This can cause excessive heat and board damage depending on how much power the input voltage can
deliver to this system. A fuse or circuit breaker can be used
as a secondary fault protector in this situation. The device
does support over current and overtemperature protection.
Layout Checklist/Example
The high integration of LTM4676 makes the PCB board
layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations
are still necessary.
• Use large PCB copper areas for high current paths,
including VINn , GND and VOUTn . It helps to minimize
the PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capacitors next to the VINn , GND and VOUTn pins to minimize
high frequency noise.
• Place a dedicated power ground layer underneath the
module.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put vias directly on pads, unless they are capped
or plated over.
• Use a separate SGND copper plane for components
connected to signal pins. Connect SGND to GND local
to the LTM4676.
• For parallel modules, tie the VOUTn, VOSNS0+/VOSNS– and/
or VOSNS1/SGND voltage-sense differential pair lines,
RUNn, GPIOn, COMPna, SYNC and SHARE_CLK pins
together—as shown in Figure 39.
• Bring out test points on the signal pins for monitoring.
Figure 34 gives a good example of the recommended layout.
12
VIN0
GND
VIN1
CIN0
CIN1
12
10
11
9
10
8
GND
SGND
7
GND
GND
7
6
COUT0 6
COUT1
5
5
GND
4
4
3
GND
3
2
VOUT0
2
1
VOUT0
VIN1
GND
8
9
GND
VIN0
11
A
B
C
D
E
F G
CNTRL
H
J
K
L
M
VOUT1
4676 F34a
VOUT1
1
A
B
C
D
E
F
G
H
J
K
L
M
Figure 34. Recommended PCB Layout Package Top View
4676fd
For more information www.linear.com/LTM4676
67
LTM4676
VIN0
VIN1
SVIN
VDD33
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
WP
SMBus INTERFACE WITH
PMBus COMMAND SET
ON/OFF CONTROL, FAULT
MANAGEMENT, POWER
SEQUENCING
PWM CLOCK SYNCH.
TIME BASE SYNCH.
• SLAVE ADDRESS = 1001010_R/W (0X4A)
• 350kHz SWITCHING FREQUENCY
• NO GUI CONFIGURATION AND
NO PART-SPECIFIC PROGRAMMING REQUIRED EXCEPT:
VIN_OFF < VIN_UV_WARN_LIMIT < VIN_ON < 4.3V
IN MULTI-MODULE SYSTEMS, CONFIGURING RAIL_ADDRESS
IS RECOMMENDED
10.7k
1%
±50ppm/°C
LTM4676
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
10k
×7
VOUT0
TSNS0a
TSNS0b
ISNS0a+
ISNS0b+
ISNS0a–
ISNS0b–
VORB0+
VOSNS0+
VOSNS0–
VORB0–
VORB1
VOUT1
TSNS1a
TSNS1b
ISNS1a+
ISNS1b+
ISNS1a–
ISNS1b–
VOSNS1
SGND
GND
CINH
22µF
×3
CINL
220µF
FSWPHCFG
+
COMP0a
COMP0b
COMP1a
COMP1b
ASEL
VIN
4.5V to 5.75V
INTVCC
VDD25
SW0
SW1
SNUB0
SNUB1
Typical Applications
COUT
100µF
×14
VOUT, 1.5V
ADJUSTABLE
UP TO 26A
LOAD
4676 F35
2.1k
1%
±50ppm/°C
22.6k
1%
±50ppm/°C
14
14
12
12
CHANNEL OUTPUT CURRENT (A)
CHANNEL OUTPUT CURRENT (A)
Figure 35. 26A, 1.5V Output DC/DC µModule Regulator with I2C/SMBus/PMBus Serial Interface
10
8
IOUT1
6
IOUT0
4
2
0
–2
0
4
20
24
16
12
TOTAL OUTPUT CURRENT (A)
8
28
10
IOUT1
8
IOUT0
6
4
2
0
–2
0
4
20
24
8
16
12
TOTAL OUTPUT CURRENT (A)
4676 F36a
(a) 5VIN, Figure 35 Circuit
28
4676 F36b
(b) 12VIN, Figure 35 Circuit with INTVCC Open
and VOUT Commanded to 1V
Figure 36. Current Sharing Performance of the LTM4676's Channels
68
4676fd
For more information www.linear.com/LTM4676
LTM4676
Typical Applications
CINH
22µF
×3
CINL
220µF
VIN0
VIN1
SVIN
VOUT0
TSNS0a
TSNS0b
ISNS0a+
ISNS0b+
ISNS0a–
ISNS0b–
+
V
INTVCC
VDD25
SW0
SW1
SNUB0
SNUB1
VDD33
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
WP
SMBus INTERFACE WITH
PMBus COMMAND SET
ON/OFF CONTROL, FAULT
MANAGEMENT, POWER
SEQUENCING
PWM CLOCK SYNCH.
TIME BASE SYNCH.
• SLAVE ADDRESS = 1001111_R/W (0X4F)
• 350kHz SWITCHING FREQUENCY
• NO GUI CONFIGURATION AND
NO PART-SPECIFIC PROGRAMMING REQUIRED EXCEPT:
VIN_OFF < VIN_UV_WARN_LIMIT < VIN_ON < 4.5V
IN MULTI-MODULE SYSTEMS, CONFIGURING RAIL_ADDRESS
IS RECOMMENDED
ORB0
VOSNS0+
VOSNS0–
–
V
LTM4676
22.6k
1%
±50ppm/°C
COUT0
100µF
×7
VOUT0, 1.2V
ADJUSTABLE
UP TO 13A
LOAD0
ORB0
VORB1
VOUT1
TSNS1a
TSNS1b
ISNS1a+
ISNS1b+
ISNS1a–
ISNS1b–
VOSNS1
SGND
GND
10k
×9
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
+
COMP0a
COMP0b
COMP1a
COMP1b
ASEL
FSWPHCFG
5V
LOW POWER BIAS
<100mA
3.3VIN
NOMINAL
3.24k
1%
±50ppm/°C
COUT1
100µF
×7
VOUT1, 2.5V
ADJUSTABLE
UP TO 13A
LOAD1
4676 F37
10.7k
1%
±50ppm/°C
Figure 37. 13A, 1.2V and 2.5V Outputs Generated from 3.3V Power Input and Providing I2C/SMBus/PMBus Serial Interface
VOUT1
50mV/DIV
VOUT1
50mV/DIV
VOUT0
50mV/DIV
VOUT0
50mV/DIV
SCL
5V/DIV
SDA
5V/DIV
SCL
5V/DIV
SDA
5V/DIV
4ms/DIV
4ms/DIV
4676 F38a
(a) PMBus Operation (Reg. 0x01): 0x80 → 0xA8 (Margin High)
VOUT1
50mV/DIV
4676 F38b
(b) PMBus Operation (Reg. 0x01): 0xA8 → 0x80 (Margin Off)
VOUT1
50mV/DIV
VOUT0
50mV/DIV
SCL
5V/DIV
SDA
5V/DIV
VOUT0
50mV/DIV
SCL
5V/DIV
SDA
5V/DIV
4ms/DIV
4676 F38c
(c) PMBus Operation (Reg. 0x01): 0x80 → 0x98 (Margin Low)
4ms/DIV
4676 F38d
(d) PMBus Operation (Reg. 0x01): 0x98 → 0x80 (Margin Off)
Figure 38. Output Voltage Margining, Figure 37 Circuit
4676fd
For more information www.linear.com/LTM4676
69
LTM4676
10k
×7
U1
LTM4676
VINO
VIN1
SVIN
CIN2
10µF
×4
INTVCC
VDD25
SW0
SW1
SNUB0
SNUB1
COMP0a
COMP0b
COMP1a
COMP1b
ASEL
FSWPHCFG
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
WP
VDD33
SVIN
INTVCC
VDD25
SW0
SW1
SNUB0
SNUB1
VINO
VIN1
CIN3
10µF
×4
FSWPHCFG
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
U2
LTM4676
COMP0a
COMP0b
COMP1a
COMP1b
ASEL
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
WP
VDD33
INTVCC
VDD25
SW0
SW1
SNUB0
SNUB1
VINO
VIN1
SVIN
CIN4
10µF
×4
FSWPHCFG
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
U3
LTM4676
COMP0a
COMP0b
COMP1a
COMP1b
ASEL
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
WP
VDD33
ON/OFF CONTROL, FAULT
MANAGEMENT, POWER
SEQUENCING
PWM CLOCK SYNCH.
TIME BASE SYNCH.
RTH
1.65k
CTH
3.3nF
U4
LTM4676
CTHP
220pF
FSWPHCFG
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
SMBus INTERFACE WITH
PMBus COMMAND SET
COMP0a
COMP0b
COMP1a
COMP1b
ASEL
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
WP
VOUT0
TSNS0a
TSNS0b
ISNS0a+
ISNS0b+
ISNS0a–
ISNS0b–
VOSNS0+
VOSNS0–
VOUT1
TSNS1a
TSNS1b
ISNS1a+
ISNS1b+
ISNS1a–
ISNS1b–
VOSNS1
SGND
COUT(BULK)
330µF
×10
VOUT, 1V
COUT(MLCC)
ADJUSTABLE
100µF
UP TO 100A
×10
LOAD
GND
VINO
VIN1
SVIN
VDD33
CIN1
10µF
×4
22.6k
1%
±50ppm/°C
VOUT0
TSNS0a
TSNS0b
ISNS0a+
ISNS0b+
ISNS0a–
ISNS0b–
VOSNS0+
VOSNS0–
VOUT1
TSNS1a
TSNS1b
ISNS1a+
ISNS1b+
ISNS1a–
ISNS1b–
VOSNS1
SGND
GND
CIN5
150µF
787Ω
1%
±50ppm/°C
VOUT0
TSNS0a
TSNS0b
ISNS0a+
ISNS0b+
ISNS0a–
ISNS0b–
VOSNS0+
VOSNS0–
VOUT1
TSNS1a
TSNS1b
ISNS1a+
ISNS1b+
ISNS1a–
ISNS1b–
VOSNS1
SGND
1.65k
1%
±50ppm/°C
GND
+
1.65k
1%
±50ppm/°C
VOUT0
TSNS0a
TSNS0b
ISNS0a+
ISNS0b+
ISNS0a–
ISNS0b–
VOSNS0+
VOSNS0–
VOUT1
TSNS1a
TSNS1b
ISNS1a+
ISNS1b+
ISNS1a–
ISNS1b–
VOSNS1
SGND
GND
VIN
5.75V TO 16V
INTVCC
VDD25
SW0
SW1
SNUB0
SNUB1
Typical Applications
1.21k
1%
±50ppm/°C
3.24k
1%
±50ppm/°C
U1: SLAVE ADDRESS = 1000000_R/W (0X40)
U2: SLAVE ADDRESS = 1000001_R/W (0X41)
U3: SLAVE ADDRESS = 1000010_R/W (0X42)
U4: SLAVE ADDRESS = 1000011_R/W (0X43)
350kHz SWITCHING FREQUENCY WITH
INTERLEAVING
NO GUI CONFIGURATION AND NO PART-SPECIFIC
PROGRAMMING REQUIRED
4676 F39
IN MULTI-MODULE SYSTEMS, CONFIGURING
RAIL_ADDRESS IS RECOMMENDED
ELECTRICALLY UNCONNECTED PINS
VORB0+, VORB0– AND VORB1 NOT SHOWN
Figure 39. Four Paralleled LTM4676 Producing 1VOUT at Up to 100A. Integrated Power System Management Features Accessible Over
2-Wire I2C/SMBus/PMBus Serial Interface. For Evaluation and More Information, See Demo Boards DC1989, DC1989A-C
70
4676fd
For more information www.linear.com/LTM4676
LTM4676
Typical Applications
CIN5
150µF
VINO
VIN1
SVIN
VDD33
CIN1
10µF
×4
10k
×6
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
WP
SMBus INTERFACE WITH
PMBus COMMAND SET
ON/OFF CONTROL, FAULT
MANAGEMENT, POWER
SEQUENCING
COMP0a
COMP0b
COMP1a
COMP1b
ASEL
FSWPHCFG
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
PWM CLOCK SYNCH.
TIME BASE SYNCH.
U1
LTM4676
VOUT0
TSNS0a
TSNS0b
ISNS0a+
ISNS0b+
ISNS0a–
ISNS0b–
VOSNS0+
VOSNS0–
VOUT1
TSNS1a
TSNS1b
ISNS1a+
ISNS1b+
ISNS1a–
ISNS1b–
VOSNS1
SGND
COUT(BULK)
470µF
×10
U1: SLAVE ADDRESS = 1000000_R/W (0x40)
500kHz SWITCHING FREQUENCY WITH INTERLEAVING
NO GUI CONFIGURATION AND NO PART-SPECIFIC
PROGRAMMING REQUIRED EXCEPT:
IOUT_OC_WARN_LIMITn =18A
MFR_GPIO_RESPONSEn = 0x00
IN MULTI-MODULE SYSTEMS, CONFIGURING
RAIL_ADDRESS IS RECOMMENDED
RTH*
RTEMP3
121k
TEMP
EXTVCC
PHASMD
RTEMP4
121k
TEMP
EXTVCC
PHASMD
SGND
INTVCC
GND
PGOOD1
VOUT1
VOUTS1
VFB1
CINTVCC4
4.7µF
DIFFP
DIFFN
DIFFOUT
VOUT2
VOUTS2
VFB2
U4*
CLKOUT
RFSET4
121k
COMP1
COMP2
fSET
SGND
CLKOUT
RUN1
RUN2
TRACK1
TRACK2
CINTVCC3
4.7µF
PGOOD2
SW1
CIN4
10µF
×4
PGOOD1
VOUT1
VOUTS1
VFB1
DIFFN
DIFFOUT
VOUT2
VOUTS2
VFB2
U3*
MODE_PLLIN
RFSET3
121k
RVFB
8.25k
DIFFP
RUN1
RUN2
TRACK1
TRACK2
COMP1
COMP2
fSET
ELECTRICALLY UNCONNECTED PINS
VORB0+, VORB0– AND VORB1 NOT SHOWN
GND
CIN3
10µF
×4
SW2
RFSET2
121k
CINTVCC2
4.7µF
PGOOD2
SW2
–
COMP1
COMP2
fSET
DIFFN
DIFFOUT
VOUT2
VOUTS2
VFB2
U2*
SW1
U5B
1/2 LT1801
SW2
SW1
RUN1
RUN2
TRACK1
TRACK2
+
PGOOD1
VOUT1
VOUTS1
VFB1
DIFFP
4676 F40
PGOOD2
SGND
TEMP
EXTVCC
PHASMD
CLKOUT
RDIV2*
VIN
MODE_PLLIN
RDIV1*
RTEMP2
121k
MODE_PLLIN
M1
2N7002A
–
CIN2
10µF
×4
1.2k
1%
±50ppm/°C
INTVCC
U5A
1/2 LT1801
6.34k
1%
±50ppm/°C
INTVCC
RCLK
200Ω
+
GND
CTH*
VOUT, 1V
COUT(MLCC)
ADJUSTABLE
100µF
UP TO 100A~130A
×20
LOAD
GND
+
INTVCC
VDD25
SW0
SW1
SNUB0
SNUB1
12VIN ±20%
*STUFFING OPTIONS
DEMO BOARD OUTPUT CURRENT U2, U3, U4 RDIV1 RDIV2 RTH CTH
DC2106A-A
UP TO 100A
LTM4620A 23.2k 76.8k 6.98k 4.7nF
20k 80.6k 7.15k 2.2nF
DC2106A-B
UP TO 130A
LTM4630
Figure 40. One LTM4676 Operating In Parallel with 3xLTM4620A or 3xLTM4630 (See Demo Boards DC2106A-A, DC2106A-B)
Producing 1VOUT at up to 100A ~ 130A. Power System Management Features Accessible Through LTM4676. See Figure 41
For more information www.linear.com/LTM4676
4676fd
71
LTM4676
Typical Applications
CHANNEL OUTPUT CURRENT (A)
14
12
10
U1-LTM4676-IOUT0
U1-LTM4676-IOUT1
U2-LTM4620A-IOUT1
U2-LTM4620A-IOUT2
U3-LTM4620A-IOUT1
U3-LTM4620A-IOUT2
U4-LTM4620A-IOUT1
U4-LTM4620A-IOUT2
8
6
4
2
0
–2
0
10 20 30 40 50 60 70 80 90 100
TOTAL OUTPUT CURRENT (A)
4676 F41a
(a) LTM4676 Paralleled with 3x LTM4620A (Up to 100A Output)
CHANNEL OUTPUT CURRENT (A)
21
18
15
U1-LTM4676-IOUT0
U1-LTM4676-IOUT1
U2-LTM4630-IOUT1
U2-LTM4630-IOUT2
U3-LTM4630-IOUT1
U3-LTM4630-IOUT2
U4-LTM4630-IOUT1
U4-LTM4630-IOUT2
12
9
6
3
0
–3
0
20
40
80 100 120
60
TOTAL OUTPUT CURRENT (A)
140
4676 F41b
(b) LTM4676 Paralleled with 3x LTM4630 (Up to 130A Output)
Figure 41. Current Sharing Performance of Figure 40 Circuit at 12VIN
72
4676fd
For more information www.linear.com/LTM4676
LTM4676
Typical Applications
GND REF/BYP
RSET2
1.62k
10k
×7
SMBus INTERFACE WITH
PMBus COMMAND SET
ON/OFF CONTROL, FAULT
MANAGEMENT, POWER
SEQUENCING
CINH
22µF
×3
VIN0
VIN1
SVIN
VDD33
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
WP
U1
LTM4676
COMP0a
COMP0b
COMP1a
COMP1b
ASEL
PWM CLOCK SYNCH.
TIME BASE SYNCH.
CINL
220µF
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
+
FSWPHCFG
VIN
5.75V to 26.5V
OPTIONAL: INSTALLING U2 AWAY FROM HEAT SOURCES
ALLOWS INTVCC LDO LOSSES NORMALLY INCURRED BY
THE LTM4676 TO BE DISSIPATED INSTEAD BY THE LT3060.
THERMAL-DERATING CAN THUS BE IMPROVED
VOUT0
TSNS0a
TSNS0b
ISNS0a+
ISNS0b+
ISNS0a–
ISNS0b–
VORB0+
VOSNS0+
VOSNS0–
–
V
ORB0
VORB1
VOUT1
TSNS1a
TSNS1b
ISNS1a+
ISNS1b+
ISNS1a–
ISNS1b–
VOSNS1
SGND
COUT
100µF
×10
RDIV1
249Ω
0.1%
VOUT, 5V
ADJUSTABLE
UP TO 26A
LOAD
RDIV2
249Ω
0.1%
GND
RSET1
13.3k
INTVCC
VDD25
SW0
SW1
SNUB0
SNUB1
OUT
U2
LT3060
SHDN
ADJ
IN
• SLAVE ADDRESS = 1000101_R/W (0X45)
• 750kHz SWITCHING FREQUENCY
4676 F42
• NO GUI CONFIGURATION AND
NO PART-SPECIFIC PROGRAMMING REQUIRED
IN MULTI-MODULE SYSTEMS, CONFIGURING RAIL_ADDRESS
4.22k
5.36k
32.4k
7.68k
IS RECOMMENDED
1%
1%
1%
1%
• IN ORDER TO OPERATE CHANNEL 0 AT 5VOUT, A RESISTOR-DIVIDER
±50ppm/°C
±50ppm/°C
±50ppm/°C
±50ppm/°C
NETWORK (RDIV1 AND RDIV2) IS USED TO KEEP VOSNS0±
WITHIN ITS VALID COMMON MODE RANGE
• AS A RESULT OF THE 2:1 FEEDBACK RESISTOR-DIVIDER NETWORK (RDIV1 AND RDIV2), ALL LTM4676 CHANNEL 0 VOUT-RELATED PARAMETERS, THRESHOLDS,
AND VOUT TELEMETRY ARE COMMANDED AND READBACK AS ONE-HALF OF WHAT IS DESIRED OR PRESENT AT THE LOAD
(EXPLICITLY: 5VOUT AT THE LOAD CORRESPONDS TO A VOUT_COMMAND0 SETTING OF 2.5V AND A READ_VOUT0 RESULT OF 2.5V)
• IN THIS CONFIGURATION, THE OUTPUT CURRENT READING OF CHANNEL 0 READS LOWER THAN NORMAL AND IS INVALID (AND SIMILARLY, FOR RELATED TELEMETRY:
CHANNEL 0 OUTPUT POWER AND INPUT CURRENT READBACK). ALL CHANNEL 1 TELEMETRY, HOWEVER, REMAINS VALID
MAXIMUM LOAD CURRENT (A)
Figure 42. 26A, 5V Output DC/DC µModule Regulator with Serial Interface
26
24
22
20
18
16
14
12
10
8
6
4
2
0
400LFM, WITH U2, RSET1 AND RSET2 INSTALLED: θJA = 6.2°C/W
200LFM, WITH U2, RSET1 AND RSET2 INSTALLED: θJA = 7.9°C/W
400LFM, WITH U2, RSET1 AND RSET2 NOT USED: θJA = 7.3°C/W
200LFM, WITH U2, RSET1 AND RSET2 NOT USED: θJA = 8.9°C/W
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4676 F43
Figure 43. Output Derating Curve of Figure 42 Circuit Tested on DC1811A, 12VIN, No Heat Sink
4676fd
For more information www.linear.com/LTM4676
73
LTM4676
Package Description
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
Table 21. LTM4676 BGA Pinout
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
F1
ISNS0b+
F2
ISNS0a+
A1
VOUT0
B1
VOUT0
C1
VOUT0
D1
VOUT0
E1
A2
VOUT0
B2
VOUT0
C2
VOUT0
D2
VOUT0
E2
ISNS0b–
ISNS0a–
A3
VOUT0
B3
VOUT0
C3
VOUT0
D3
VOUT0
E3
GND
F3
GND
A4
GND
B4
GND
C4
GND
D4
GND
E4
GPIO0
F4
GPIO1
A5
SNUB0
B5
GND
C5
TSNS0b
D5
TSNS0a
E5
ALERT
F5
RUN0
A6
GND
B6
GND
C6
GND
D6
SDA
E6
SCL
F6
RUN1
A7
GND
B7
GND
C7
GND
D7
GND
E7
SYNC
F7
SGND
A8
GND
B8
GND
C8
GND
D8
COMP0b
E8
COMP0a
F8
SGND
+
–
A9
GND
B9
GND
C9
GND
D9
VOSNS0
E9
VOSNS0
F9
INTVCC
A10
GND
B10
SW0
C10
DNC
D10
VORB0+
E10
VORB0–
F10
GND
A11
VIN0
B11
VIN0
C11
VIN0
D11
VIN0
E11
DNC
F11
SVIN
A12
VIN0
B12
VIN0
C12
VIN0
D12
VIN0
E12
VIN0
F12
SVIN
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
G1
ISNS1b–
H1
ISNS1b+
J1
VOUT1
K1
VOUT1
L1
VOUT1
M1
VOUT1
G2
–
H2
+
J2
VOUT1
K2
VOUT1
L2
VOUT1
M2
VOUT1
ISNS1a
ISNS1a
G3
GND
H3
GND
J3
VOUT1
K3
VOUT1
L3
VOUT1
M3
VOUT1
G4
ASEL
H4
FSWPHCFG
J4
GND
K4
GND
L4
GND
M4
GND
G5
VOUT0CFG
H5
VTRIM0CFG
J5
TSNS1a
K5
TSNS1b
L5
GND
M5
SNUB1
G6
VOUT1CFG
H6
VTRIM1CFG
J6
VDD25
K6
WP
L6
GND
M6
GND
G7
SGND
H7
SHARE_CLK
J7
VDD33
K7
GND
L7
GND
M7
GND
G8
SGND
H8
COMP1a
J8
COMP1b
K8
GND
L8
GND
M8
GND
G9
INTVCC
H9
VOSNS1
J9
VORB1
K9
GND
L9
GND
M9
GND
G10
GND
H10
GND
J10
GND
K10
DNC
L10
SW1
M10
GND
G11
GND
H11
DNC
J11
VIN1
K11
VIN1
L11
VIN1
M11
VIN1
G12
GND
H12
VIN1
J12
VIN1
K12
VIN1
L12
VIN1
M12
VIN1
74
4676fd
For more information www.linear.com/LTM4676
LTM4676
Package Description
1
2
3
4
5
TOP VIEW
6
7
8
9
10
11
12
SNUB0
A
VOUT0
GND
GND
SW0
GND
DNC
B
GND
TSNS0b
VIN0
C
VOUT0
TSNS0a
SDA
GND
+
COMP0b VOSNS0
VORB0+
SYNC
–
COMP0a VOSNS0
VORB0–
VIN0
D
ISNS0b–
ISNS0a–
GPIO0
ALERT
SCL
ISNS0b+
ISNS0a+
GPIO1
RUN0
RUN1
ISNS1b–
ISNS1a–
ISNS1b+
ISNS1a+
DNC
E
SVIN
SVIN
F
GND
ASEL
SGND
VOUT0CFG VOUT1CFG
INTVCC
G
FSWPHCFG VTRIM0CFG VTRIM1CFG SHARE_CLK COMP1a
VOSNS1
GND
DNC
H
TSNS1a
VDD25
TSNS1b
WP
VDD33
COMP1b
VORB1
J
VOUT1
DNC
VIN1
K
GND
GND
SW1
L
VOUT1
SNUB1
GND
GND
VIN1
M
Package Photograph
4676fd
For more information www.linear.com/LTM4676
75
aaa Z
0.630 ±0.025 Ø 144x
E
PACKAGE TOP VIEW
3.1750
3.1750
SUGGESTED PCB LAYOUT
TOP VIEW
1.9050
4
0.6350
0.0000
0.6350
PIN “A1”
CORNER
1.9050
For more information www.linear.com/LTM4676
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
Y
X
D
DETAIL B
H2
MOLD
CAP
ccc Z
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
H1
SUBSTRATE
A1
NOM
5.01
0.60
4.41
0.75
0.63
16.00
16.00
1.27
13.97
13.97
0.41
4.00
MAX
5.21
0.70
4.51
0.90
0.66
Z
NOTES
DETAIL B
PACKAGE SIDE VIEW
0.46
4.05
0.15
0.10
0.20
0.30
0.15
TOTAL NUMBER OF BALLS: 144
0.36
3.95
MIN
4.81
0.50
4.31
0.60
0.60
b1
DIMENSIONS
ddd M Z X Y
eee M Z
DETAIL A
Øb (144 PLACES)
aaa Z
A2
A
(Reference LTC DWG # 05-08-1920 Rev B)
// bbb Z
76
Z
BGA Package
144-Lead (16mm × 16mm × 5.01mm)
e
11
b
10
9
7
G
6
5
e
PACKAGE BOTTOM VIEW
8
4
3
2
DETAIL A
1
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
BALL DESIGNATION PER JESD MS-028 AND JEP95
7
TRAY PIN 1
BEVEL
!
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
M
L
K
J
H
G
F
E
D
C
B
A
3
SEE NOTES
PIN 1
7
SEE NOTES
BGA 144 0213 REV B
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
COMPONENT
PIN “A1”
F
b
12
LTM4676
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
4676fd
6.9850
5.7150
4.4450
4.4450
5.7150
6.9850
LTM4676
Revision History
REV
DATE
DESCRIPTION
A
12/13
Added Video Tech Clip link
PAGE NUMBER
Corrected figure numbers in Tables 15, 16 and 17
1
61
B
2/14
Added SnPb BGA option
1, 3
Updated part number in Figure 40
71
C
8/14
Update Note 13
10
Update Block Diagram
19
Update Functional Diagram
20
Update Test Circuits
21
Update I2C Commands
Update Manufacturer Product ID Code
Update "RESTORE_USER_ALL” Attributes
35
Correct Phase Information in Table 4
43
Update Figures 35, 37, 44
D
09/15
27
28, 40
Clarified pin function descriptions
68, 69, 78
18
4676fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTM4676
77
LTM4676
Typical Application
CINH
22µF
×3
VIN0
VIN1
SVIN
VOUT0
TSNS0a
TSNS0b
ISNS0a+
ISNS0b+
ISNS0a–
ISNS0b–
VORB0+
VOSNS0+
VOSNS0–
–
V
VDD33
10k
×9
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
WP
SMBus INTERFACE WITH
PMBus COMMAND SET
ON/OFF CONTROL, FAULT
MANAGEMENT, POWER
SEQUENCING
PWM CLOCK SYNCH.
TIME BASE SYNCH.
• SLAVE ADDRESS = 1001111_R/W (0X4F)
• SWITCHING FREQUENCY: 350kHz
• NO GUI CONFIGURATION AND
NO PART SPECIFIC PROGRAMMING REQUIRED
IN MULTI-MODULE SYSTEMS, CONFIGURING
RAIL_ADDRESS IS RECOMMENDED
LTM4676
22.6k
1%
±50ppm/°C
COUT0
100µF
×7
VOUT0, 1.0V
ADJUSTABLE
UP TO 13A
LOAD0
ORB0
VORB1
VOUT1
TSNS1a
TSNS1b
ISNS1a+
ISNS1b+
ISNS1a–
ISNS1b–
VOSNS1
SGND
GND
CINL
220µF
INTVCC
VDD25
SW0
SW1
SNUB0
SNUB1
+
COMP0a
COMP0b
COMP1a
COMP1b
ASEL
FSWPHCFG
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
VIN
5.75V TO 26.5V
COUT1
100µF
×7
VOUT1, 1.8V
ADJUSTABLE
UP TO 13A
LOAD1
4676 F44
6.34k
1%
±50ppm/°C
Figure 44. 13A, 1V and 13A, 1.8V Output DC/DC µModule Regulator with Serial Interface
Design Resources
SUBJECT
µModule Design and Manufacturing Resources
DESCRIPTION
Design:
Manufacturing:
• Selector Guides
• Quick Start Guide
• Demo Boards and Gerber Files
• PCB Design, Assembly and Manufacturing Guidelines
• Free Simulation Tools
• Package and Board Level Reliability
1. Sort table of products by parameters and download the result as a spread sheet.
µModule Regulator Products Search
2. Search using the Quick Power Search parametric table.
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
TechClip Videos
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
Related Parts
PART NUMBER DESCRIPTION
LTM4675
Smaller, Lower Power than LTM4676
LTM4676A
LTM2987
LTpowerPlay
COMMENTS
Dual 9A, Single 18A; 11.9mm x 16mm BGA; Fits in the Larger Foot
Print Layout of the LTM4676 Dual 13A
Faster Turn-On Time than LTM4676
70ms vs. 170ms; Pin-Compatible with the LTM4676; up to 5.5VOUT
16-Channnel PMBus Power System Manager
Provides Digital Telemetry Control of Several POL Regulators: Fault
Log, Margin, Trip, etc.
Program and Adjust Power Management Schemes; Includes Diagnostics
Free Evaluation and Development Software for Linear Technology’s
Digital Power System Manager Products (I2C/PMBus/SMBus Interface) and Debugging; Automatic Software Update and Device Drivers
Licensed under U.S. Patent 7000125 and other related patents worldwide.
78 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTM4676
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTM4676
4676fd
LT 0915 REV D • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2013