PANASONIC AN5165K

ICs for TV
AN5165K
A Single Chip IC for NTSC Color-TV
■ Overview
1
1.778
52
■ Features
• Built-in video IF circuit, sound IF circuit, video signal
processing circuit, color signal processing circuit, deflection correction circuit and sync. signal processing
circuit
• Built-in I2C bus interface
0.5±0.1
1.0±0.25
Unit: mm
47.7±0.3
The AN5165K is an IC in which all of the NTSC
system color television signal processing circuits are integrated on a single chip. The rationalization of set production line can be realized by this IC incorporating I2C
bus interface.
26
27
13.7±0.3
(0.7)
3.85±0.3 (3.3)
■ Applications
• TVs
3° to 15°
(15.24)
3° to 15°
SDIP052-P-0600A
1
CW Out
V Out1
2
H Out
51
52
YS&YM
APC
BPF SW
SW
SW
Cut Off B SW
Cut Off R SW
Cut off DAC
Drive
DAC DAC
L.P.F.
RGB Limit
3-bit
C Filter
B.P.F.2
B.P.F.1
to Chroma
8-bit
7-bit
Cut Off Drive
7-bit
DAC
Gain Control
DEM
Color
Contrast
ACC2
ACC1
DAC 5-bit
SW
DC
ABL SW
γ
Black
Expamsion
8-bit
Y Clamp
Bright
DAC
Y Contrast
6-bit
Sharpness
DAC
SW
SW γ On/Off SW
DAC
On/Off SW7-bit
DAC
Y.N.R
SW
3-bit
Trap
38
VCO
7-bit
50
H Center
C In
Tint
DAC
49
B.G.P
43
CW Out
47
CCP (Hosc4)
40
SW
Killer
HOSC
DL
L.P.F.
37
ACC DET
48
Ver.
Sync. Sep.
PT
VIF
Amp.
APC
34
Killer Off SW
46
Trig1
Trig2
A Trig
P.EQP
X-ray
45
H Out2
44
AFC2
VCJ GND
VCO
CTRL
9-bit
AFT
DAC
IF
AGC
SW
V SW
VA
SW
VSW
DAC 7-bit
RF
AGC
IF
DET
NI
VAMP
DAC 4-bit
IF AGC
to Video
RGB
AFC1
42
VBLK
6.3 V
41
VCO
35
VCO1
36
VCO2
Hor.
CountDown
FBP In
31
Hosc1
H Pluse
Hosc2
H Out1
V/C/J/5 V
30
2fH
Ver.
CountDown
H Sync.
39
Lock DET
V Clamp
33
AFC1
V Sync. Y In
X-ray
BLDET
SIF
ASW
DAC
VOL
5-bit
DEMP
PLL
RAMP
DC
28
H.EQP
32fH
IF 9 V
32
Ver. Out
APC
CV Clamp
DET Out
Hor.
Sync. Sep.
Int.V
HBLK
AFT Out
SW
Video Out
to Video
29
HBLK
SIF In
HVCO
Ext.Audio
S.SW
AN5165K
ICs for TV
■ Block Diagram
27
26
25
24
23
22
21
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Decoupling
Ext.Video
Audio Out
APC
RF AGC Out
20
GND (IF)
19
18 IF 5 V
9V
BLK In (SCP)
SCL
SDA
ACL/NECK
GND (RGB)
Lock DET
B
G
R
V/C/J 9 V
B In
G In
R In
YS&YM
APC
Chroma VCO
ICs for TV
AN5165K
■ Pin Description
Pin No.
Description
Pin No.
Description
1
Chroma VCO (3.58 MHz)
28
SIF Input/White Expand-Level
2
Chroma APC Filter
29
IF AGC Filter
3
YS & YM Input
30
Video Output
4
External R Input
31
AFT Output
5
External G Input
32
Internal Video Input
6
External B Input
33
VIF Detect Output
7
VCC1-1 9 V (VCJ)
34
VIF APC Filter
8
R Output
35
VIF VCO (1)
9
G Output
36
VIF VCO (2)
10
B Output
37
VCC1-2 9 V
11
Hor. Lock Detect
38
Black Detect
12
GND
(RGB/I2C/
39
Y/Ver. Sync. Input
13
ACL/NECK Protect
40
Ver. Sync. Clamp
14
SDA
41
Hor. Sync. Input
15
SCL
42
VCC2-2 5 V (Chroma/jungle/DAC)
16
BLK Pulse Input/HSYNC2 Output
43
Chroma Input/Black Expansion Start
17
White Detect
44
GND (Video/Chroma/Jungle)
18
VCC2-1 5 V (VIF/SIF)
45
FBP Input
19
VIF Input (1)
46
VCC3 6.2 V
20
VIF Input (2)
47
AFC1 Filter
21
GND (VIF/SIF)
48
Hor. VCO (32 fH)
22
RF AGC Output
49
X-ray Protection Input
23
SIF APC Filter
50
Hor. Pulse Output
24
Audio Output
51
DAC)
25
External Video Input
26
DC Decoupling Filter
27
External Audio Input
CW Output/Spot KILLER Off Input/
X-ray Protection Output
52
Ver. Pulse Output
■ Absolute Maximum Ratings
Parameter
Supply voltage
Supply current
Symbol
VCC
ICC
Rating
Unit
VCC1 (7·37)
10.5
VCC2 (18·42)
6.0
VCC3 (46)
6.5
I7+37
117
I18+42
68
I46
6.3
V
mA
3
AN5165K
ICs for TV
■ Absolute Maximum Ratings (continued)
Parameter
Power dissipation
Symbol
Rating
Unit
PD
1 481
mW
Topr
−20 to +70
°C
Tstg
−55 to +150
°C
*2
Operating ambient temperature
Storage temperature
*1
*1
Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C.
*2: The power dissipation shown is the value for Ta = 70°C
■ Recommended Operating Range
Parameter
Supply voltage
Symbol
Range
Unit
VCC1
8.1 to 9.9
V
VCC2
4.5 to 5.5
VCC3
6.05 to 6.35
■ Electrical Characteristics at Ta = 25°C
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Power supply
Supply current 1
I7+I37
Current at V7 = 9 V, current at
V37 = 9 V
68
85
100.5
mA
Supply current 2
I18+I42
Current at V18 = 5 V, current at
V42 = 5 V
38
48
57
mA
Supply current 3
I46
Current, when V46 = 6.2 V
2
5
6
mA
Supply current 4
I46
Current at V46 = 6.2 V. However
all other power supplies are off state
5
7
9
mA
Modulation factor m = 87.5%
Data 0D = 88
1.75
2.1
2.5
V[p-p]
VIF circuit (Typical input fP = 45.75 MHz, VIN = 90 dBµ)
Video detection output (typ.)
VPO
Video detection output (max.)
VPOmax
Data 0D = F8
2.15
2.6
3.3
V[p-p]
Video detection output (min.)
VPOmin
Data 0D = 08
1.1
1.6
2.0
V[p-p]
Video detection output f characteristics
fPC
Frequency of output −3 dB for 1 MHz
5.5
8
12
MHz
Synchronous peak value voltage
VSP
Voltage in VPO measurement
1.6
2.0
2.4
V
APC pull-in range (Hu)
fPPHU
High band side pull-in range
(Difference from fP = 45.75 MHz)
1.0
1.5

MHz
APC pull-in range (Lu)
fPPLU
Low band side pull-in range

−1.5
−1.0
MHz
(Difference from fP = 45.75 MHz)
4
RF AGC delay point adjustment
range
DVRFDP
Input to become delay point
(V22 = approx. 6.5 V), when Data
0C = 00 to 7F
75

95
dBm
RF AGC maximum sink current
IRFmax
Maximum current IC can sink when
pin 22 is low
1.5
3.0

mA
ICs for TV
AN5165K
■ Electrical Characteristics at Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VIF Circuit (continued) (Typical input fP = 45.75 MHz, VIN = 90 dBµ)
RF AGC minimum sink current
IRFmin
Leak current of IC, when pin 22 is
high
−50
0
50
mA
AFT discrimination sensitivity
µAFT
Df = ±25 kHz
40
57
75
mV/kHz
AFT center voltage
VAFT
V31 without VIN
4.0
4.5
5.0
V
AFT maximum output voltage
VAFTmax
V31 at f = fP−500 kHz
7.8
8.1
8.7
V
AFT minimum output voltage
VAFTmin
V31 at f = fP+500 kHz
0.3
0.8
1.0
V
Df = ±25 kHz, 0A = 10
250
350
450
mV[rms]
SIF circuit (Typical input fS = 4.5 MHz, fM = 400 Hz, VIN = 90 dBµ)
Audio detection output
VSO
Audio detection output (max.)
VSOmax
Data 0A = 1F
300
390
480
mV[rms]
Audio detection output (min.)
VSOmin
Data 0A = 00
150
256
350
mV[rms]
3.3

5.7
MHz
SIF pull-in range
fSP
AV SW circuit
Video SW voltage gain
GVSW
f = 1 MHz, VIN = 1 V[p-p]
6.2
7.2
8.2
dB
Video SW frequency characteristics
fVSW
Frequency of output −3 dB from 1 MHz
10


MHz
Audio SW voltage gain
GASW
Data 0 F−D5 = 1 (external)
f = 400 Hz, VIN = 1 V[p-p]
−3
−1
1
dB
Video signal processing circuit (In the following test conditions, the measurements are made withinput: 2.0 V[p-p]
(VWB = 1.43 V[0-p]stair-step) at GOUT.)
Data 03 = 40 (typ.) (Contrast)
1.9
2.4
2.9
V[0-p]
VYOmax
Data 03 = 7 F (max.)
3.8
4.8
5.8
V[0-p]
VYOmin
Data 03 = 00 (min.)
0.07
0.3
0.6
V[0-p]
19
22
26
dB
6.0
8.0
10.0
MHz
7
10.5
14
dB
Video output (typ.)
VYO
Video output (max.)
Video output (min.)
Contrast variable range
Video frequency characteristics
Sharpness variable range
YCmax/min 03 = 7F
03 = 00
fYC
Data 0F−D7 = 0 (Trap Off)
Data 04 = 00 (Sharpness)
Frequency to become −3 dB from
f = 0.5 MHz
YSmax/min 04 = 3F
04 = 00
f = 3.8 MHz
Data 0F − D7 = 0
Pedestal level (typical)
VPED
Data 02 = 80 (typ.) (Brightness)
2.4
3.0
3.6
V
Pedestal variable width
∆VPED
Difference between Data 02 = 00
and FF
2.2
2.6
3.0
V
Brightness control sensitivity
∆VBRT
Average amount of change per 1 step,
when Data 02 = 60 and A0
9.5
12.5
15.5 mV/Step
ACL sensitivity
ACL
Change of YOUT from V13 = 3.0 V to 3.5 V
2.3
2.9
3.6
V/V
Blanking level
VYBL
DC voltage of blanking pulse
0.9
1.4
1.9
V
5
AN5165K
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Video signal processing circuit (continued) (In the following test conditions, the measurements are made with
input: 2.0 V[p-p] (VWB = 1.43 V[0-p] stair-step) at GOUT.)
Video input clamp current
IYCLP
DC measurement: Sink current inside IC
5
10
15
µA
ACL start point
VACL
V13 voltage at which output amplitude
becomes 90% when ACL pin (V13)
is being decreased from 5 V.
3.5
4.0
4.5
V
Color signal processing circuit (In the following test conditions, burst = 300 mV[p-p], reference is BOUT)
Color difference output (typ.)
VCO
Color difference output (max.)
Color difference output (min.)
Contrast variable range
Input: Color bar
Data 00 = 40 (typ.), 03 = 40 (typ.)
2.8
3.5
4.2
V[p-p]
VCOmax
Data 00 = 7 F one side amplitude
Data 03 = 40
2.3
3.4

V[0-p]
VCOmin
Data 00 = 00, Data 03 = 40
0

100
mV[p-p]
15
20
25
dB
CCmax/min 03 = FF
03 = 00
Data 00 = 40
ACC characteristics 1
ACC1
Burst 300 mV[p-p]→600 mV[p-p]
Input: Color bar
0.8
1.0
1.2
Time
ACC characteristics 2
ACC2
Burst 300 mV[p-p]→60 mV[p-p]
Input: Color bar
0.7
1.0
1.2
Time
Tint center
∆θC
Difference (Tint) between Data 01 = 40
and that of tint adjusted at center
−13
0
13
STEP
Tint variable range 1
∆θ1
Data 01 = 7F
30
45
60
deg
Tint variable range 2
∆θ2
Data 01 = 00
−60
−45
−30
deg
Demodulation output ratio (R)
R/B
Input: Rainbow
0.81
0.95
1.09
Time
Demodulation output ratio (G)
G/B
Input: Rainbow
0.3
0.36
0.42
Time
Demodulation output angle (R)
∠R
Input: Rainbow
92
104
116
deg
Demodulation output angle (G)
∠G
Input: Rainbow
223
235
237
deg
APC pull-in range (H)
fCPH
450
900

Hz
APC pull-in range (L)
fCPL

−900
−450
Hz
RGB processing circuit
Pedestal difference voltage
∆VIPL
Difference voltage of RGB out pedestal − 0.3

0.3
V
Brightness voltage tracking
∆TBL
Ratio of R, G, B out fluctuation level 0.9
for Data 02 (Bright) 02 = 40 to C0
1.0
1.1
Time
Video voltage gain relative ratio
∆GYC
Output ratio of R, B out to GOUT
0.8
1.0
1.2
Time
∆TCONT
Gain ratio of R, G, B out for Data
03 (Contrast) 03 = 20 to 60
0.9
1.0
1.1
Time/
Time
GDV
AC change amount of R, B out between
drive adjustment max. and min.
5.9
7.1
8.3
dB
Video voltage gain tracking
Drive adjustment range
6
ICs for TV
AN5165K
■ Electrical Characteristics at Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
1.8
2.4
3.0
V
RGB processing circuit (continued)
Cutoff adjustment range
VCUTOFF DC change amount of R, G, B out
between drive adjustment max. and min.
YS threshold voltage
VYS
Minimum DC voltage at which YS
turns on
2.7
3.1
3.6
V
YM threshold voltage
VYM
Minimum DC voltage at which YM
turns on
0.7
1.0
1.3
V
YM operating voltage gain
∆GYM
YM on/off gain difference
−12
−9
−6
dB
External RGB pedestal voltage
VEPL
YS is on
2.1
2.7
3.3
V
External RGB pedestal difference
voltage
∆VEPL
YS is on, R−G, G−B
−250

250
mV
Internal/external pedestal difference
voltage
∆VPL/IE
Internal−external
−100
200
500
mV
External RGB output voltage
VERGB
Input 3 V[p-p], contrast 03 =7 F
1.2
1.7
2.2
V[0-p]
∆VERGB
Input 3 V[p-p], contrast 03 = 7F
− 0.6
0
0.6
V
5
8
11
dB
Input 0.2 V[p-p], DC = 1 V
8
12

MHz
External RGB output difference
voltage
External RGB contrast variable range ECmax/min 03 = 7F
03 = 00
External RGB frequency characteristics
fRGBC
Synchronizing signal processing circuit
Horizontal free-running oscillation
frequency
fHO
Without sync. signal input
15.4
15.75
16
kHz
Horizontal pull-in range
fHP
Difference from fH = 15.75 kHz
±500
±650

Hz
58
60
62
Hz
5.5
6.5
7.5
1/fH
5.9
7.3
9.1
µs
Vertical free-running oscillation
frequency
Vertical output pulse width
Picture center variable range
fVO-N
Without sync. signal input
τVO
∆THC
Change amount of phase difference
between HSYNC and HOUT Data from
0E: 00 to 1F
I2C interface
SCL, SDA signal input high level
VIHI
3.1

5.0
V
SCL, SDA signal input low level
VILO
0

0.9
V
Allowable maximum input frequency
fImax
100


kbit/s
• Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input level to become VPO = −3 dB

52
60
dBµ
VIF Circuit (Typical input fP = 45.75 MHz, VIN = 90 dBµ)
Input sensitivity
VPS
7
AN5165K
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
104
110

dBµ
VIF circuit (continued) (Typical input fP = 45.75 MHz, VIN = 90 dBµ)
Maximum allowable input
Input level to become VPO = +1 dB
SN ratio
SNP
50
53

dB
Differential gain
DGP
0
3
5
%
Differential phase
DPP
0
3
5
deg
Black noise detection level
∆VBN
Difference from sync. peak value
−55
−45
−35
IRE
Black noise clamp level
∆VBNC
Difference from sync. peak value
35
45
55
IRE
RF AGC operation sensitivity
GRF
Input level difference to become
V22 = 1 V→7 V
0.5
1.5
3.0
dB
VCO switch on drift
∆fPD
Frequency drift from 5 seconds
after SW On to 5 mins. after

70

kHz
Intermodulation
IM
VFC−VFP = −2 dB, VFS−VFP = −12 dB
46
52

dB
RF AGC adjustment sensitivity
SRF
Average amount of change of output
voltage V22 for Data 1Step
1.0
1.7
2.5
V/Step
AFT offset adjustment sensitivity
SAFT
Average amount of change of output 0.15
voltage V31 for Data 1Step
0.2
0.25
V/Step
Video detection output fluctuation
with VCC
∆VP/V
VCC = ±10%

±10
±15
%
Video detection output-temperature
characteristics
∆VP/T
Ta = −20°C to +70°C

±5
±10
%
Input resistance (pin 19, 20)
RI19,20
f = 45.75 MHz

1.2

kΩ
Input capacitance (pin 19, 20)
CI19,20
f = 45.75 MHz

4.0

pF
Sound IF output level
VSIF
fS = 45.75 MHz−4.50 MHz,
P/S = 20 dB
94
100
106
dBm
VCO control sensitivity 1
βPU
DV34 = 2.0 V−3.8 V, f = 45.75 MHz
1.3
2.2
3.1
kHz/mV
VCO control sensitivity 2
βPJ
DV34 = 2.0 V−3.8 V, f = 58.75 MHz
1.3
2.2
3.1
kHz/mV
RF AGC delay point
-temperature characteristics
∆VDP/T
Ta = −20°C to +70°C
0
3
5
dB
VCO free-running frequency
-temperature characteristics
∆fP/T
Ta = −20°C to +70°C

300

kHz
AFT center frequency
-temperature characteristics
∆fAFT/T
Ta = −20°C to +70°C
Input frequency at which AFT output
voltage becomes 4.5 V

300

kHz
VCO free-run adjustment
VAFTADJ
AFT center voltage adjustment

4.5

V
−300
0
300
kHz
VCO free-running frequency 1
8
VPmax
∆fP1
Dispersion without VIN.
V29 (IF AGC) = 0 V (Difference
from 45.75 MHz is measured)
ICs for TV
AN5165K
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
−300
0
300
kHz
VIF circuit (continued) (Typical input fP = 45.75 MHz, VIN = 90 dBµ)
VCO free-running frequency 2
∆fP2
Dispersion without VIN.
V29 (IF AGC) = 0 V (Difference
from 58.75 MHz is measured)
APC pull-in range (Hj)
fPPHJ
High band side pull-in range
(Difference from fP = 58.75 MHz)
1.0
1.5

MHz
APC pull-in range (Lj)
fPPLJ
Low band side pull-in range
(Difference from fP = 58.75 MHz)

−1.5
−1.0
MHz
Detection output resistance
RO33
DC measurement
70
120
170
Ω
SIF circuit (Typical input fS = 4.5 MHz, fM = 400 Hz, VIN = 90 dBµ)
Input limiting level
VLIM
Input level to become VSOP = −3 dB

44
50
dBµ
AM rejection ratio
AMR
AM = 30%
60
70

dB
Total harmonic distortion
THD
Df = ±50 kHz
0
0.3
0.5
%
SN ratio
SNA
50
55

dB
Audio detection output linearity
∆VSOP
Ratio of ∆f = ±50 kHz to
∆f = ±25 kHz
5
6
7
dB
Audio output fluctuation with VCC
∆VS/V
VCC = ±10%

±3
±6
%
Audio output-temperature
characteristics
∆VS/T
Ta = −20°C to +70°C

±5
±10
%
Audio output-frequency
characteristics 1
fSOP1
APC pin C = 100 pF
100


kHz
Audio output-frequency
characteristics 2
fSOP2
APC pin C = 5600 pF

2.2

kHz
f = 1 MHz, VIN = 1 V[p-p],
Inside→Outside, Outside→Inside

−60
−50
dB
AV SW circuit
Video SW crosstalk
CTVSW
Video SW external input terminal
voltage
V25
DC measurement
1.3
1.6
1.9
V
Video SW internal input terminal
voltage
V32
DC measurement
1.3
1.6
1.9
V
Video SW internal output DC voltage
V30I
DC measurement Data 04−D6 = 0
3.4
4.2
5.0
V
Video SW external output DC voltage
V30E
DC measurement Data 0F−D5 = 1
3.4
4.2
5.0
V
Video SW input resistance
RI25, 32
DC measurement

524

Ω
Video SW output resistance
RO30
DC measurement
20
50
100
Ω
9
AN5165K
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
AV SW circuit (continued)
Audio SW crosstalk
(Internal→External)
CTAIE
fS = 4.5 MHz, fM = 400 Hz,
No external input

−73
−67
dB
Audio SW crosstalk
(External→Internal)
CTAEI
fS = 4.5 MHz, fM = 0 Hz, External
f = 400 Hz, VIN = 600 mV[rms]

−73
−67
dB
Audio SW input terminal voltage
V27
DC measurement
3.7
4.2
4.7
V
Audio SW internal output DC voltage
V24I
DC measurement
3.7
4.2
4.7
V
Audio SW external output DC voltage
V24E
DC measurement
3.7
4.2
4.7
V
Audio SW internal/external DC
difference voltage
∆V24
DC measurement
−300
0
300
mV
Audio SW input resistance
RI27
DC measurement
61
72
83
kΩ
Audio SW output resistance
RO24
DC measurement
200
400
600
Ω
Video signal processing circuit (In the following test conditions, the measurements are made with input 2.0 V[p-p]
(VWB = 1.43 V[0-p]) GOUT)
Y signal delay time 1
TDL1
Phase difference from Y-input
(For both trap on/off)
620
690
760
ns
Y signal delay time 2
TDL2
Phase difference from Y-input
(Trap through)

200

ns
Black level extension 1
VBL1
Input: Total black, difference between −100
pin 38 of 9 V and open (With RC filter)
0
100
mV
Black level extension 2
VBL2
Input: Total black, pin 38 GND and
black slice potential V43 = 2.5 V
700
900
1 300
mV
Black level extension 3
VBL3
Voltage difference between pin 38
open and 9V. Black slice potential
V43 = 2.5 V
400
600
800
mV
Contrast variation with sharpness
DVCS
YOUT output level difference between
sharpness max. and min.
−300
0
300
mV
Contrast variation with sharpness
DVBS
Pedestal level DC difference between
sharpness max. and min.
−250
0
250
mV
Input dynamic range
VImax
Contrast 03 = 40
2.8


V[p-p]
Y signal SN ratio
SNY
Contrast 03 = 7F
51
56

dB
Black level extension start point
VBLS
Start point when V43 = 4.5 V
50
57
64
IRE
Trap on/off through-gain difference DGTRAP
Trap on/off/through
−1
0
1
dB
Trap frequency error
DfTRAP
Trap center frequency at chroma
input 3.58 MHz
−70
0
70
kHz
Trap attenuation amount
AttTRAP
3.58 MHz component attenuation
amount at chroma input 3.58 MHz
26
30

dB
10
ICs for TV
AN5165K
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Video Signal Processing Circuit (continued) (In the following test conditions, the measurements are made with
input 2.0 V[p-p] (VWB = 1.43 V[0-p]) GOUT)
Trap automatic adjustment range
fTRAP
VCO frequency of ∆fTRAP ≤ 70 kHz
3

4
MHz
Video output fluctuation with VCC
∆VY/V
VCC1 = 9 V (allowance: ±10%)
0
100
250
mV/V
Video output-temperature characteristics
∆VY/T
Ta = −20°C to +70°C
0
5
10
%
YNR operation I
SNYNR
S/N, when YNR: min.→max. and
sharpness max.

−4

dB

−1.5

dB
01−D7 = 1, when V13 = 1.5 V→3.5 V
Pedestal level fluctuation
0.3
0.5
0.7
V/V
YNR operation II
ABL sensitivity
SNYNR Sharpness max., YNR: max.
(IFAGC) S/N at IF AGC 2 V→4 V
ABL
White gradation correction 1
γ1
White detection pin V17 = 4.5 V
Difference of amplitude between
GOUT gamma on/off
120
125
130
%
White gradation correction 2
γ2
White detection pin V17 = 2.0 V
Difference of amplitude between
GOUT gamma on/off
70
75
80
%
0.3
0.5
1.0
V
90
100
110
%
0

50
mV[p-p]
Difference from f = 3.579545 MHz −300
0
300
Hz
∆VC/V
VCC1 = 9 V (allowance: ±10%)
−300
0
300
Hz
Static phase error
∆θN
Tint shift at
∆fC = −300 to +300 Hz change

1
3
deg/100 Hz
Demodulation output bandwidth
fCC
Band to become −3 dB
400
600
800
kHz
Demodulation output fluctuation
with VCC
∆VC/V
VCC1 = 9 V (allowance: ±10%)

±4

%
Demodulation output
-temperature characteristics
∆VC/T
Ta = −20°C to +70°C

±10
±20
%
−250
0
250
mV
0

20
mV
Neck protector threshold voltage
VNP
DC restoration ratio
TDC
APL 10% to 90%
∆AC−∆DC
TDC =
× 100
∆AC
Color signal processing circuit (Burst 300 mV[p-p], reference is BOUT)
Demodulation output residual carrier
VCO free running frequency
fCO fluctuation with VCC
VCAR
fCN
Brightness variation with color
VBC
Brightness variation difference
voltage with color
∆VBC
fSC level of pin 8, 9, 10
Pedestal level DC difference between
color max. and min.
R, G, B Out variation voltage
difference
11
AN5165K
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Color signal processing circuit (continued) (Burst 300 mV[p-p], reference is BOUT)
Color killer allowance 1
VKILL1
0 dB = 300 mV[p-p], 00−D7 = 0
−53
−46
−39
dB
Color killer allowance 2
VKILL2
0 dB = 300 mV[p-p], 00−D7 = 1
−50
−43
−36
dB
CW output level (3.58 MHz)
VCW
AC component of (3.58 MHz)
0.6
1.1
1.4
V[p-p]
B.P.F. (Symmetrical) frequency
characteristics
fB.P.F.
Band to become
−3 dB from 3.58 MHz
400
600
800
kHz
Slant of 3.58 MHz ±500 kHz

9.0

dB/MHz
0.9
1.2
1.5
V[0-p]/
V[p-p]
−100
0
100
ns
7
11

MHz
B.P.F. (Asymmetrical) slant
VB.P.F./f
RGB processing circuit
(C−Y)/Y
RC/Y
Color bar input, BOUT
Contrast typ. color Data 00 = 60
(C−Y), Y delay difference
∆TC/Y
Color bar input, BOUT
Phase of green→magenta
YS changeover speed
fYS
fYS, when external input is 3 V,
output level −3 dB
External RGB input dynamic range
VDEXT
Contrast max. Data 03 = 7F
6.5
7.0

V[0-p]
Internal/external crosstalk
CTRGB
Leakage when f = 1 MHz, 1 V[p-p],
YS = 5 V

−60
−50
dB
Spot killer operation
VSPK
V9 at which spot killer turns on by
decreasing V9 from 9 V
7.3
7.7
8.0
V
Brightness variation with contrast
VBAC
Pedestal level DC difference between
contrast max. and min.
−250
0
250
mV
0

20
mV
−60
0
60
mV
Brightness variation difference
voltage with contrast
DVBAC
R, G, B Out variation voltage
difference
Color /B&W DC difference voltage
DVCBW
Pedestal level voltage difference
between with and without burst signal
Pedestal level fluctuation with VCC
DVPL/V
VCC1 = 9 V (allowance: ±10%)
0
200
400
mV/V
Pedestal level-temperature characteristics
DVPL/T
Ta = −20°C to +70°C

− 0.6

mV/°C
Pedestal level difference voltage
fluctuation with VCC
DVPD/V
VCC1 = 9 V (allowance: ±10%)
R−G, B−G

0

mV/V
Burst input only
0.8
1.3
1.8
V
External RGB output blanking voltage
VBLK
RGB limiter control range 1
VBEAM1
Input 2 V[p-p], contrast max.
RGB limiter 0E = 70
6.4
6.7
7.0
V
RGB limiter control range 2
VBEAM2
Input 2 V[p-p], contrast max.
RGB limiter 0E = F0
5.6
6.0
6.4
V
12
ICs for TV
AN5165K
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Synchronizing signal processing circuit
Horizontal output start voltage
VfHS
Minimum V46, when H osc. output is
1 V[p-p] or more and fO becomes >10 kHz
3.9
4.4
4.9
V
Lock detection output voltage 1
VLD1
V11, when horizontal AFC is locked
3.8
4.3
4.8
V
Lock detection output voltage 2
VLD2
V11, when horizontal AFC is unlocked.
0
0.1
0.5
V
±0.5
±0.7
±1.1
mA
Lock detection charge and discharge
current
ILD
DC measurement
EBP (BLK) slice level
VFBP
Minimum voltage of pin 45, when
blanking is applied to RGB output
0.3
0.66
1.0
V
EBP (AFC2) slice level
VFBPH
Minimum voltage of pin 45, when
AFC2 operates
1.45
1.85
2.25
V
Horizontal AFC µ
µH
DC measurement
26
33
40
µA/µs
Horizontal VCO β
βH
β curve gradient near f = 15.75 kHz
1.4
1.8
2.2
Hz/mV
Delay from HSYNC rise
0.2
0.4
0.6
µs
2.5
3.0
3.5
µs
Burst gate pulse position
Burst gate pulse width
PBGP
WBGPN
V blanking pulse width
WVN
Pulse width, when fH = 15.75 kHz
1.04
1.14
1.24
ms
EBP allowable range
TFBP
Time from HOUT rise to FBP center
12

19
µs
Overvoltage protective operation
voltage
VXRAY
Dispersion from the minimum voltage
at which H osc. comes to be out of
synchronization
−60

60
mV
Black-out operation voltage
VBLOUT
Difference voltage from hold-down
to black out
10
110
160
mV
HSYNC2 output level
VSCP
HSYNC2 output DC level
8.0
8.2
8.4
V
HSYNC2 output width
WSCP
HSYNC2 output pulse width

2

µs
HSYNC2 output position
PSCP
The period of time from HSYNC
center to HSYNC2 rise

3

µs
Horizontal output pulse duty cycle
tHO
Upward going pulse duty cycle
32
38
44
%
Horizontal output voltage (high)
V50H
High level DC voltage
2.8
3.1
3.4
V
Horizontal output voltage (low)
V50L
Low level DC voltage
0

0.3
V
Vertical output voltage (high)
V52H
High level DC voltage
3.9
4.2
4.5
V
Vertical output voltage (low)
V52L
Low level DC voltage
0

0.3
V
Synchronizing signal clamp voltage (Ver.)
V39
V39 clamp voltage
3.2
3.6
4.0
V
Synchronizing signal clamp voltage (Hor.)
V41
V41 clamp voltage
3.2
3.6
4.0
V
External blanking input threshold level
V16I
0.4
0.75
1.1
V
Vertical pull-in range
fVP-N
56

64
Hz
fH = 15.75 kHz
13
AN5165K
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
1.8
2.5
5.0
mA
I2C interface
Sink current when ACK
IACK
Bus free before start
tBUF
4.0


µs
Start condition set-up time
tSU, STA
4.0


µs
Start condition hold time
tHD, STA
4.0


µs
Low period SCL,SDA
tLOW
4.0


µs
High period SCL
tHIGH
4.0


µs
Rise time SCL,SDA
tR


1.0
µs
Fall time SCL,SDA
tF


0.35
µs
Data set-up time(write)
tSU, DAT
0.25


µs
Data hold time(write)
tHD, DAT
0


µs
Acknowledge set-up time
tSU, ACK


3.5
µs
Acknowledge hold time
tHD, ACK
0


µs
Stop condition set-up time
tSU, STO
4.0


µs
0.1
1.0
1.9
LSB
Step
Maximum value of sink current
for pin 14 at ACK
DAC
3, 4, 5, 6, 7-bit DAC DNLE
L3, 4, 5, 6, 7 1LSB = {Data (max.)−Data (00)}
/7, 15, 31, 63, 127
L8
1LSB = {Data (FF)−Data (00)}/255
0.1
1.0
1.9
LSB
Step
DSTEP
Overlap of 8-bit 2-stage changeover
of R, B cut-off (Same for AFT)
27
32
37
Step
8-bit DAC DNLE
Cut-Off DAC overlap
• Standard conditions when testing
1. Input signal
1) VIF
2) SIF
: fP = 45.75 MHz, VIN = 90 dBµ, at video modulation: Modulation signal is 10-staircase
Modulation m = 87.5%, pin 19 input level 84 dBµ when VIN = 90 dBµ
: fS = 4.5 MHz, VIN = 90 dBµ, modulation signal fM = 400 Hz, deviation: NTSC ±25 kHz
: 10-staircase 2 V[p-p] (VBW = 1.43 V[0-p])
: Color bar signal: Burst level 300 mV[p-p]
Rainbow signal : Burst level 300 mV[p-p]
5) Sync. signal: Video signal 1.5 V[p-p] to 2.5 V[p-p] for both horizontal and vertical sync. signal input
3) Video
4) Chroma
14
ICs for TV
AN5165K
■ Electrical Characteristics at Ta = 25°C (continued)
• Standard conditions when testing (continued)
2. I2C BUS condition
Sub Address
Data (H)
40
Sub Address
08
Data (H)
00
Color
Drive R
40
01
Tint
40
02
Bright
80
09
Drive B
40
0A
Audio Adj, YNR
10
03
Contrast
40
0B
AFT
10
04
Sharpness
00
0C
RFAGC
40
05
Cut-off R
80
0D
Video Adj
08
06
Cut-off G
40
0E
H center, RGB limiter
10
07
Cut-off B
80
■ Terminal Equivalent Circuits
Pin No.
Equivalent circuit
1
100 Ω
3.58 MHz
1
1.5 kΩ
IN2
C8
15 pF
IN1
200 µA 200 µA
500 µA
Description
I/O
Chroma oscillation pin (3.58 MHz)
• Pin for chroma oscillation of 3.58 MHz.
• The pattern between pin and oscillator
should be made as short as possible.
AC
f = fC
approx.
0.3 V[p-p]
APC filter pin
• Filter pin for APC detection circuit
(Operates for BGP period)
• Detection sensitivity becomes high when
external R→Large (Tends to be easily
pulled in and
β curve
afffected
by noise.)
f
DC
approx.
5.6 V
Temperature characteristic
product should be used for C8
(−750 ppm/°C)
2
25 µA
270 Ω
6.3 V
200 Ω
84 kΩ
270 Ω
2
50 µA
1.0 µF
3 300 pF
C
R
3.3 kΩ
1 000 µA
V2
9 V (VCC1-1)
3
25 µA
5V
25 µA
25 µA 3 V
16 kΩ
3V
1V
270 Ω 1 kΩ
3
50 kΩ
25 µA
25 µA
YS/YM input pin
• Fast blanking pulse input pin for OSD
• YM On (Half-tone) at 1.0 V[0-p] or
higher
• YS ON(OSD input) at 3.0 V[0-p] or
higher
• Recommended use range: 0 V to 6 V
AC
(Pulse)
YS
YM
25 µA
15
AN5165K
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
9 V (VCC1-1)
4
5
6
50 µA
to RGB Output
Circuit
200 Ω
pin4, 5, 6
50 kΩ
5.0 V
0
50 kΩ
I/O
External R input pin
External G input pin
External B input pin
• External input pin for OSD
• Output linearly changes according to
input level
• Recommended use range: 0 V to 6 V
AC
(Pulse)
5.0 V
0
from
µ-COM

7
9 V (VCC1-1)
8
9
10
100 µA
50 Ω
Pin 8
9
10
100 µA
11
5V
(VCC2-2)
to
Chroma
Circuit
10 kΩ
800 µA
12 kΩ 2.8 V
I1
12 kΩ
3.7 V
800 µA
I2
50 µA
270 Ω
11
8 µA
ZO
0.082 µF
VCC1-1 (typ.9 V)
• Video circuit
• Chroma circuit
• RGB circuit
• Sync. circuit
• DAC circuit
DC
9V
R Out pin
G Out pin
B Out pin
• BLK level approx. 1.5 V
• Black (Pedestal) level approx. 3.0 V
• Recommended use range: −2.4 mA to
+4.8 mA
AC
Horizontal sync. detection pin
• Phase of horizontal synchronizing signal
and horizontal output pulse are detected
and outputted
• Pin 11 becomes low at out of
synchronization
• Color control becomes min. and chroma
output disappears and VOUT goes into freerunning state in a asynchronous condition
• Pay attention to impedance when pin 11
voltage is used for microcomputer
(ZO ≥ 680 kΩ required)
DC
when
synchronized
4.5 V
when
asynchronous
0.1 V
pin 50
H Out
ZO≥680 kΩ
pin 41
HSYNC In
• HSYNC period, when pin 50
at high: I1 ON
at low: I2 ON
12
16

GND
• RGB circuit
• DAC. I2C circuit
• VIF (VCO) circuit
DC
ICs for TV
AN5165K
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
I/O
9V
(VCC1-1)
13
ACL/ABL pin
DC
• RGB output is blacked out when DC voltage approx. 3.5 V
of pin 13 is decreased from the outside.
140kΩ
However, it is not blacked out when service
Neck
switch has been turned on.
(Service switch priority)
6.9 kΩ
• When 01−D7 = 1, ABL functions, and brightness
7.1 kΩ
ABL
decreases by lowering DC voltage of pin 13
5 kΩ
6.9 kΩ
• When pin 13 is grounded, ACC gain becomes
13
min. and it is possible to measure chroma
free-running frequency. Measuring point is
pin 51.
When neck protect time high • Recommended use range: 0 V to V
CC1
5.9 V
60 kΩ
60 kΩ
6.9 kΩ
2.7 V
7.1 kΩ
2.7 V
14
5V
(VCC2-2)
5V
2.7 kΩ
20 µA
3.25 V
50 µA
10 kΩ
Data 14 1 kΩ
14
100 Ω
51 kΩ
2 kΩ
from
µ-com
30 kΩ
15
20 µA
50 µA
3.25 V
10 kΩ
1 kΩ
5.0 V
0
2 kΩ
to Logic
Circuit
ACK
30 kΩ
16
50 µA
10 kΩ
30 kΩ
9V
(VCC1-1)
H Sync.2
10 kΩ
0.7 V
2.7 kΩ
40 kΩ
AC
(Pulse)
0
51 kΩ
from
µ-com
50 µA
I2C clock input pin
• Input low level: 0.9 V or less
• Input high level: 3.1 V or more
• Recommended use range: 0 V to VCC2
5.0 V
30 kΩ
5V
(VCC2-2)
5V
Clock
15
100 Ω
AC
(Pulse)
to Logic
Circuit
ACK
2.7 kΩ
I2C BUS Data input pin
• Input low level: 0.9 V or less
• Input high level: 3.1 V or more
• ACK sink capability: 1.8 mA
• Recommended use range: 0 V to VCC2
100 kΩ
3.9 kΩ
16
270 Ω 5.6 kΩ
External blanking input pin
• RGB out blanking is applied when a voltage
of 0.8 V or more is applied
• HSCP pulse output pin
Horizontally synchronized 2 µs pulse is
outputted.
• Recommended use range: − 0.8 mA to
0.2 mA, 0 V to 5.0 V
AC
(Pulse)
8.2 V
5V
0V
17
AN5165K
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
17
40 µA
10 µA
20 µA
9V
Description
9V
(VCC1-1)
YOUT
4.7 µF
270 Ω
17
I/O
White Peak Detect Filter input pin
• White gradation correction response
characteristic is determined.
When there is screen sag, make C→larger
When screen response is slow, make
C→smaller
DC
VCC2-1 (typ.5 V)
• VIF, SIF circuit
DC
5V
375 Ω 50 kΩ
6 kΩ
40 µA
50 µA

18
19
20
5V
(VCC2-1)
3.5 V
27 kΩ
1.2 kΩ
1.2 kΩ
20
0.68 µH
19
0.022 µF
SAW
VIF input pin 1
VIF input pin 2
• VIF amp. input with balanced input
• Input max.120 dBµ
Input resistance: 1.2 kΩ (45.75 MHz)
Input capacitance: 4.0 pF (45.75 MHz)
AC
f = fP
DC level
approx. 2.7 V
150 µA 150 µA

21
22
3 kΩ
6 kΩ
5V
(VCC2-1)
100 µA
10 kΩ
IF AGC
Bias
22
to Tuner
270 Ω
GND
• For VIF and SIF circuit
DC
RF AGC output pin
• Collector open output
• Recommended use range: 0 V to VCC1 (9 V)
Maximum sink current min.: 1.5 mA
DC
SIF APC filter pin
• Filter pin for APC circuit of SIF.
• Deemphasis characteristic is changeable
by the capacitor between pin and GND
DC
approx. 2.5 V
RF AGC
Control
Bias
33 kΩ
40 kΩ
1 kΩ
23
9V
(VCC1-2)
12.2 kΩ 7.5 kΩ
1.5 V
270 Ω
875 Ω
57 kΩ
23
4 pF
18
1 kΩ
100 pF
ICs for TV
AN5165K
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
24
9V
(VCC1-2)
24
270 Ω
Description
I/O
Audio output pin
• DC fluctuates by internal/external changeover
• Recommended use range: − 0.8 mA to
+ 0.8 mA
AC
0 kHz to 20 kHz
DC
approx. 3.9 V
External video input pin
• Input pin for external video signal and DC
cut input
• Typical: 1 V[p-p] (max. 1.5 V[p-p])
• ZO is 100 Ω or less
AC
1 V[p-p]
(Composite)
150 µA 800 µA
25
9V
(VCC1-1)
50 µA
50 µA
(VCC1-2)
Int. Video
1.6 V
to
Video SW
4.7 µF
25
500 Ω
ZO<100 Ω
7 µA
DC
approx. 1.6 V
26
9V
(VCC1-2)
10 kΩ
1.7 kΩ
typ. 4.5 V
3 kΩ
3 kΩ
270 Ω
26
C
4.7 µF
270 Ω
Decoupling pin
• S-curve in IC is wideband, but DC feedback is
applied so that DC voltage of output signal
becomes constant.
• DC level (typ. 4.5 V), fS→high: V26→low
• If C (4.7 µF) is too small, sound distortion
tends to become larger at low frequency.
DC
20 kΩ
100 µA
13 µA
27
9V
(VCC1-2)
50 µA
5.4 V
to
Audio SW
65 kΩ 270 Ω
27
10 µF
270 Ω
External audio input pin
AC
• Input pin for external audio signal. DC cut 0 kHz to 20 kHz
input.
• Adjust typical input level to internal sound
level.
• Input max. 7 V[p-p]
150 µA
28
0.01 µF
3 kΩ
3 kΩ
270 Ω
28
1.5 kΩ
9V
(VCC1-2)
Blooming
DC
128 kΩ
to SIF
Limitter Amp.
80 pF
100 µA
25 µA
SIF signal input pin
AC
• Input max. 110 dBµ
f = fS
Blooming DC adjusting pin
• White gradation correction curve and bias
DC
to determine absolute clip point are provided. approx. 2.3 V
(2.0 V to 4.5 V)
• Recommended use range: 0 V to VCC1 (9 V)
19
AN5165K
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
29
5V
(VCC2-1)
270 Ω 270 Ω
to IF Amp.
30 µA
29
0.47 µF
30
500 Ω
30
9V
(VCC1-2)
100 µA
50 Ω
I/O
IF AGC filter pin
• Pin for IF AGC filter. The current obtained
from peak AGC circuit is smoothed by
external capacitor.
• Since response becomes faster when C goes
smaller, hum characteristic will be improved.
However, sag tends to appear easily.
DC
approx. 2 V
Video output pin
• INT.Video or EXT.Video selected by AV
SW is outputted.
• Recommended use range −3.2 mA to
+0.4 mA
AC
2 V[p-p]
DC level
approx. 4.2 V
400 µA
31
1.1 kΩ
9V
(VCC1-2)
1.1 kΩ
9V
33 kΩ
to Tuner
31
270 Ω
0.01 µF
33 kΩ
1.1 kΩ
40 kΩ
1.1 kΩ
AFT output pin
• Offset of center voltage is adjusted by bus
• When AFT defeat SW is turned on (0B = 00),
V31 becomes a value determined by external
resistance-divider.
• µ of AFT is variable by impedance of
externally attached resistor.
DC
Internal video input pin
• Input pin for signal detected by VIF circuit
(Internal video signal).
• DC cut input
Typical input: 1 V[p-p] (max. 1.5 V[p-p])
ZO ≅ 280 Ω
AC
1 V[p-p]
(Composite)
max. 350 µF
32
50 µA
to
Video SW
9V
(VCC1-1)
50 µA
(VCC1-2)
Int. Video
1.6 V
4.7 µF
32
ZO
500 Ω
7 µA
33
9V
(VCC1-2)
150 µA
50 Ω
33
800 µA
20
DC level
approx. 1.6 V
VIF detection output pin
• Adjusted to center value by I2C bus
(Using upper 4-bit of 0 A)
DC voltage becomes approx. 1 V at
external video mode (04−D6 = 1)
Recommended use range: −1.6 mA to
+ 0.8 mA
AC
approx.
2.1 V[p-p]
ICs for TV
AN5165K
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
34
5V
(VCC2-1)
50 µA
SW
0
1
500 Ω
270 Ω
220 pF to1800 pF
10 kΩ
35
36
I/O
APC filter pin
• Filter pin for VIF APC circuit.
• Lock detection circuit for VCO is built
in the IC inside to changeover the time
constant for APC filter.
DC
approx. 2.5 V
VIF oscillation pin
• Oscillation coil is changed according to
VIF frequency.
• Allowable value of dispersion for coil
resonance point is within 1%.
AC
approx.
0.3 V[p-p]
DC level
approx. 3.9 V
3.25 V
to
VOC
0.47 µF
34
75 µA
75 Ω
25 µA
5V
(VCC2-1)
1.5 kΩ
35
Description
1.5 kΩ
36
2.5V
1 200 µA
1 200 µA 300 µA 300 µA

37
VCC1-2 (typ.9 V)
IF circuit
38
9 V (VCC1-1)
2.5 2.5 kΩ
kΩ
2.5 kΩ
−Y
6.6 kΩ
6.6 kΩ
18 pF
270 Ω
100 µA
50 µA
38
DC
9V
Black level detection pin
DC
• Black level detection pin for black extension approx. 5.1 V
circuit
• The most black Y-level except for blanking
circuit is held.
Black detection sensitivity drops when
ZO is made smaller, so that black detection
becomes impossible unless a large black
area.
ZO
4.7 µF
10 kΩ
9V
(VCC1-1)
39
50 µA 16 kΩ
16 kΩ
Video
5V
220 kΩ
2.2 µF
2.4 kΩ
39
3.5 V
41
1 kΩ
0.015 µF
470 pF
60 pF 10 µA
Vertical sync. separation input pin
Video input pin
• Video signal input pin
(Also composite video input)
• Typical input: 2.0 V[p-p]
• Sync. Top is clamped at 3.5 V
• Video signal should be inputted at low
impedance. (under 100 Ω)
AC
2.0 V[p-p]
8 µA
21
AN5165K
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
40
Description
5V
(VCC2-2)
3 kΩ
4.3 V
30 kΩ
10 kΩ
to Ver.
Count Down
10 kΩ
270 Ω
4 µA
50 kΩ
29
C1 220
2.2 µF
200 Ω
Vertical synchronizing signal clamp pin
• Peak clamp pin for separating vertical sync.
signal.
• Integral amount of vertical sync signal
itself has been determined by internal time
constant. However, trigger application timing
is determined by the selection of external
constant C1.
AC
f = fV
AC
2 V[p-p]
41

Horizontal sync separation input pin
• Internal circuit of pin 39 and 41 are the same.
• When R→large, slice level becomes deeper
(Weak to Sync compression). When R→
small, slice level becomes shallower
(Weak to fluctuation such as Ver. Sag).
• Sync. Top is clamped at 3.5 V.
42

VCC2-2 (typ.5 V)
For chroma, jungle circuit
43
9 V (VCC1-1)
39 kΩ
200 Ω
39 kΩ
43
68 pF
270 Ω
128 kΩ
Chroma
attenuator
circuit
100 µA
60 pF
Blstart
Black extension DC
100 µA
25 µA

44
45
5 V (VCC2-2)
100 µA
50 µA
100 µA
2.7 kΩ
1.9 V
24 kΩ
50 µA
to
AFC
0.7 V
60 kΩ
to
HBLK
40 kΩ
2.7 kΩ 270 Ω
45
100 kΩ
I/O
Chroma signal input pin
Black extension start point adjusting pin
• Pin 43 is chroma signal input pin, and black
extension start point is adjusted by externally
applied DC voltage.
DC level: high ↔ low
Start point: Shallow ↔ Deep
Black extension effect: Small ↔ Large
• Recommended use range: 0 V to VCC1 (9 V)
DC
5V
AC+DC
Burst typ.
300 mV[p-p]
DC typ.
4.5 V
GND
• For video, chroma, jungle circuit
DC
0V
FBP input pin
• FBP input pin for horizontal blanking and
AFC circuit
• Threshold level
HBLK: 0.7 V
AFC: 1.9 V
• A voltage input of 0 V or less is inhibited.
• Recommended use range: 0 V to VCC2 (5 V)
AC
FBP
Horizontal stabilized power supply pin.
DC
6.2 V
50 µA
46
22

ICs for TV
AN5165K
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
47
6.2 V
(VCC3)
4.3 V
27 kΩ
AFC1
Detecter
R1 27 kΩ
1.5 V
47
Hor. Sync.
1 µF
C2
0.033 µF
C1
200 µA
R2
1 000 µA 1.8 kΩ
Hor.
OSC
DC
typ. 4.3 V
fH
V53
48
6.2 V
(VCC3)
22 kΩ
300 Ω
200 µA 10 kΩ 10 kΩ
48
Horizontal AFC1 filter pin
• The capacitor connected to pin 47 is charged
and discharged after comparing the phase
of horizontal synchronizing signal and pulse
inside the IC.
• R1, R2, C1 and C2 are lag lead filter for
AFC1.
Horizontal β curve
I/O
Horizontal oscillation pin
• Oscillation takes place at 32 × fH ≅ 503 kHz
by ceramic oscillator.
• Horizontal and vertical pulse are generated
by count-down circuit inside the IC.
AC
f = 32 fH
(approx.
500 kHz)
Overvoltage protection input pin
• If increasing input pin voltage from 0 V
at VREF (pin 46) = 6.2 V;
(1) Horizontal oscillation come to be out
of synchronization: approx. 6.15 V
(2) Blacked out: (1)+70 mV
• Recommended use range: 0 V to VCC1 (9 V)
DC
Normally
0V
80 µA
100 µA
220 pF: Temperature characteristic product should
be used (−750 ppm/°C)
49
9V
(VCC1-1)
1 kΩ V
CC3
49
1 kΩ
48.3 kΩ
46
20 kΩ
100 µA
50
6.2 V
(VCC3)
4.3 V
19 kΩ
50 Ω
Horizontal pulse output pin
• Duty cycle approx. 37%
• Recommended use range: −6.4 mA to
+0.1 mA
AC
Pulse
3.5 V
0
50
10 kΩ
40 kΩ
3.5 V
0V
Hor. Out
23
AN5165K
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
51
9 V (VCC1-1)
320 kΩ
50 µA
15 pF
30 kΩ
80 kΩ
270 Ω
51
10 kΩ
44 kΩ
596 kΩ
100 µA
Hold
30 kΩ
52
50 kΩ
4.2 V
52
To spot
killer
circuit
5V
(VCC2-2)
I/O
CW output pin / input pin for spot killer off.
AC
(Output amplitude 860 mV[p-p])
Approx.
The pin also shares in Hold-down detection.
830 mV[p-p]
• At normal: 6.1 V (DC)
• At hold-down: 1.2 V (DC)
• Apply 9 V(VCC1) DC to turn off spot killer.
f = 3.58 MHz
Recommended use range: − 0.4 mA to + 0.1 mA
0 V to VCC1
Vertical pulse output pin
• Negative polarity, pulse width 6.25 H
• Recommended use range: − 0.8 mA to + 0.1 mA
AC
Pulse
4.2 V
43 kΩ
0
24
0