Data Sheet

DF
N2
020
D-3
PBSS5330PAS
30 V, 3 A PNP low VCEsat (BISS) transistor
11 September 2014
Product data sheet
1. General description
PNP low VCEsat Breakthrough In Small Signal (BISS) transistor, encapsulated in an ultra
thin DFN2020D-3 (SOT1061D) leadless small Surface-Mounted Device (SMD) plastic
package with medium power capability and visible and soldarable side pads.
NPN complement: PBSS4330PAS
2. Features and benefits
•
•
•
•
•
•
•
•
•
•
Low collector-emitter saturation voltage VCEsat
High collector current capability IC and ICM
High collector current gain (hFE) at high IC
High efficiency due to less heat generation
High temperature applications up to 175 °C
Reduced Printed-Circuit Board (PCB) area requirements
Leadless small SMD plastic package with soldarable side pads
Exposed heat sink for excellent thermal and electrical conductivity
Suitable for Automatic Optical Inspection (AOI) of solder joint
AEC-Q101 qualified
3. Applications
•
•
•
•
•
Loadswitch
Battery-driven devices
Power management
Charging circuits
Power switches (e.g. motors, fans)
4. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCEO
collector-emitter
voltage
open base
-
-
-30
V
IC
collector current
-
-
-3
A
ICM
peak collector current
single pulse; tp ≤ 1 ms
-
-
-5
A
RCEsat
collector-emitter
saturation resistance
IC = -3 A; IB = -300 mA; pulsed;
-
75
107
mΩ
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
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PBSS5330PAS
NXP Semiconductors
30 V, 3 A PNP low VCEsat (BISS) transistor
5. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
1
B
base
2
E
emitter
3
C
collector
Simplified outline
Graphic symbol
3
3
1
2
1
2
sym013
Transparent top view
DFN2020D-3 (SOT1061D)
6. Ordering information
Table 3.
Ordering information
Type number
PBSS5330PAS
Package
Name
Description
Version
DFN2020D-3
DFN2020D-3: plastic thermal enhanced ultra thin small outline
package; no leads; 3 terminals; body 2 x 2 x 0.65 mm
SOT1061D
7. Marking
Table 4.
Marking codes
Type number
Marking code
PBSS5330PAS
E2
PBSS5330PAS
Product data sheet
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PBSS5330PAS
NXP Semiconductors
30 V, 3 A PNP low VCEsat (BISS) transistor
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VCBO
collector-base voltage
open emitter
-
-30
V
VCEO
collector-emitter voltage
open base
-
-30
V
VEBO
emitter-base voltage
open collector
-
-6
V
IC
collector current
-
-3
A
ICM
peak collector current
-
-5
A
IB
base current
-
-500
mA
Ptot
total power dissipation
[1]
-
600
mW
[2][3]
-
1.2
W
[4]
-
1.5
W
[5][6]
-
2.5
W
single pulse; tp ≤ 1 ms
Tamb ≤ 25 °C
Tj
junction temperature
-
175
°C
Tamb
ambient temperature
-55
175
°C
Tstg
storage temperature
-65
175
°C
[1]
[2]
[3]
[4]
[5]
[6]
PBSS5330PAS
Product data sheet
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
2
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm .
Device mounted on an FR4 PCB, 4-layer copper, tin-plated and standard footprint.
2
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 6 cm .
2
Device mounted on an FR4 PCB, 4-layer copper, tin-plated and mounting pad for collector 1 cm .
Device mounted on a ceramic PCB, Al2O3, standard footprint.
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PBSS5330PAS
NXP Semiconductors
30 V, 3 A PNP low VCEsat (BISS) transistor
aaa-013298
3
(1) + (2)
Ptot
(W)
2
(3)
(4) + (5)
1
(6)
0
-75
25
125
Tamb (°C)
225
(1) Ceramic PCB, single-sided copper, standard footprint
(2) FR4 PCB, 4-layer copper, 1 cm
2
(3) FR4 PCB, single-sided copper, 6 cm
2
2
(4) FR4 PCB, single-sided copper, 1 cm
(5) FR4 PCB, 4-layer copper, standard footprint
(6) FR4 PCB, single-sided copper, standard footprint
Fig. 1.
Power derating curves
9. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Conditions
Rth(j-a)
thermal resistance
from junction to
ambient
in free air
[1]
[2]
[3]
[4]
[5]
[6]
PBSS5330PAS
Product data sheet
Min
Typ
Max
Unit
[1]
-
-
250
K/W
[2][3]
-
-
125
K/W
[4]
-
-
100
K/W
[5][6]
-
-
60
K/W
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
2
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm .
Device mounted on an FR4 PCB, 4-layer copper, tin-plated and standard footprint.
2
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 6 cm .
Device mounted on a ceramic PCB, Al2O3, standard footprint.
2
Device mounted on an FR4 PCB, 4-layer copper, tin-plated and mounting pad for collector 1 cm .
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PBSS5330PAS
NXP Semiconductors
30 V, 3 A PNP low VCEsat (BISS) transistor
006aab979
103
Zth(j-a)
(K/W)
duty cycle = 1
102
0.75
0.33
0.5
0.2
0.1
0.05
10
0.02
1
0.01
0
10- 1
10- 5
10- 4
10- 3
10- 2
10- 1
1
10
102
tp (s)
103
FR4 PCB, standard footprint
Fig. 2.
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
006aab980
103
Zth(j-a)
(K/W)
102
duty cycle = 1
0.75
0.33
10
0.2
0.1
0.05
0.02
1
0.5
0.01
0
10- 1
10- 5
10- 4
10- 3
10- 2
FR4 PCB, mounting pad for collector 1 cm
Fig. 3.
10- 1
1
10
102
tp (s)
103
2
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
PBSS5330PAS
Product data sheet
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PBSS5330PAS
NXP Semiconductors
30 V, 3 A PNP low VCEsat (BISS) transistor
006aac000
103
Zth(j-a)
(K/W)
duty cycle = 1
102
0.75
0.5
0.33
10
0.2
0.1
1
0.05
0.02
0
0.01
10- 1
10- 5
10- 4
10- 3
10- 2
FR4 PCB, mounting pad for collector 6 cm
Fig. 4.
10- 1
1
10
102
tp (s)
103
2
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
aaa-013299
103
Zth(j-a)
(K/W)
102
duty cycle = 1
0.75
0.50
0.33
0.20
10
0.10
0.05
0.02
0.01
1
10-1
10-5
0
10-4
10-3
10-2
10-1
1
10
102
tp (s)
103
FR4 PCB, 4-layer copper, standard footprint
Fig. 5.
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
PBSS5330PAS
Product data sheet
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PBSS5330PAS
NXP Semiconductors
30 V, 3 A PNP low VCEsat (BISS) transistor
102
aaa-013300
duty cycle = 1
Zth(j-a)
(K/W)
0.50
10
0.20
0.75
0.33
0.10
0.05
0.02
1
0.01
0
10-1
10-5
10-4
10-3
10-2
10-1
FR4 PCB, 4-layer copper, mounting pad for collector 1 cm
Fig. 6.
1
10
102
tp (s)
103
2
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
102
Zth(j-a)
(K/W)
006aab982
duty cycle = 1
0.75
0.33
0.5
0.2
10
0.1
0.05
1
0.02
0.01
0
10- 1
10- 5
10- 4
10- 3
10- 2
10- 1
1
10
102
tp (s)
103
Ceramic PCB, Al2O3, standard footprint
Fig. 7.
Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
PBSS5330PAS
Product data sheet
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PBSS5330PAS
NXP Semiconductors
30 V, 3 A PNP low VCEsat (BISS) transistor
10. Characteristics
Table 7.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ICBO
collector-base cut-off
current
VCB = -24 V; IE = 0 A; Tamb = 25 °C
-
-
-100
nA
VCB = -24 V; IE = 0 A; Tj = 150 °C
-
-
-50
µA
ICES
collector-emitter cut-off VCE = -24 V; VBE = 0 V; Tamb = 25 °C
current
-
-
-100
nA
IEBO
emitter-base cut-off
current
VEB = -5 V; IC = 0 A; Tamb = 25 °C
-
-
-100
nA
hFE
DC current gain
VCE = -2 V; IC = -0.5 A; pulsed;
200
320
-
175
280
450
140
210
-
100
160
-
-
-45
-70
mV
-
-90
-130
mV
-
-170
-240
mV
IC = -3 A; IB = -300 mA; pulsed;
-
-230
-320
mV
RCEsat
collector-emitter
saturation resistance
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
-
75
107
mΩ
VBEsat
base-emitter saturation IC = -2 A; IB = -100 mA; pulsed;
voltage
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
-
-0.89
-1.1
V
-
-0.97
-1.2
V
-
-0.75
-1
V
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
VCE = -2 V; IC = -1 A; pulsed;
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
VCE = -2 V; IC = -2 A; pulsed;
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
VCE = -2 V; IC = -3 A; pulsed;
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
VCEsat
collector-emitter
saturation voltage
IC = -0.5 A; IB = -50 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
IC = -1 A; IB = -50 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
IC = -2 A; IB = -100 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
IC = -3 A; IB = -300 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
VBEon
base-emitter turn-on
voltage
VCE = -2 V; IC = -1 A; pulsed;
td
delay time
VCC = -9 V; IC = -2 A; IBon = -0.1 A;
-
11
-
ns
tr
rise time
IBoff = 0.1 A; Tamb = 25 °C
-
59
-
ns
ton
turn-on time
-
70
-
ns
ts
storage time
-
165
-
ns
tf
fall time
-
35
-
ns
toff
turn-off time
-
200
-
ns
PBSS5330PAS
Product data sheet
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
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PBSS5330PAS
NXP Semiconductors
30 V, 3 A PNP low VCEsat (BISS) transistor
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fT
transition frequency
VCE = -5 V; IC = -100 mA; f = 100 MHz;
100
165
-
MHz
-
38
45
pF
Tamb = 25 °C
Cc
collector capacitance
VCB = -10 V; IE = 0 A; ie = 0 A;
f = 1 MHz; Tamb = 25 °C
006aac036
800
hFE
600
006aac037
-5
IC
(A)
IB (mA) = - 53
- 42.4
-4
(1)
- 31.8
0
- 10- 1
- 10.6
(3)
- 5.3
-1
-1
- 10
- 102
0
- 103
- 104
IC (mA)
VCE = −2 V
0
- 0.4
- 0.8
- 1.2
- 1.6
- 2.0
VCE (V)
Tamb = 25 °C
(1) Tamb = 100 °C
Fig. 9.
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 8.
- 26.5
- 15.9
-2
200
- 37.1
- 21.2
-3
(2)
400
- 47.7
Collector current as a function of collectoremitter voltage; typical values
DC current gain as a function of collector
current; typical values
PBSS5330PAS
Product data sheet
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PBSS5330PAS
NXP Semiconductors
30 V, 3 A PNP low VCEsat (BISS) transistor
006aac038
- 1.2
006aac039
- 1.4
VBEsat
(V)
VBE
(V)
(1)
- 0.8
- 1.0
(2)
(1)
(3)
(2)
- 0.4
0
- 10- 1
- 0.6
-1
- 102
- 10
- 0.2
- 10- 1
- 103
- 104
IC (mA)
(3)
-1
- 10
VCE = −2 V
IC/IB = 20
(1) Tamb = −55 °C
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
(3) Tamb = 100 °C
Fig. 10. Base-emitter voltage as a function of collector
current; typical values
006aac040
-1
- 102
Fig. 11. Base-emitter saturation voltage as a function of
collector current; typical values
006aac041
-1
VCEsat
(V)
- 103
- 104
IC (mA)
VCEsat
(V)
- 10- 1
- 10- 1
(1)
(1)
(2)
(2)
(3)
- 10- 2
- 10- 2
(3)
- 10- 3
- 10- 1
-1
- 10
- 102
- 10- 3
- 10- 1
- 103
- 104
IC (mA)
-1
IC/IB = 20
Tamb = 25 °C
(1) Tamb = 100 °C
(1) IC/IB = 100
(2) Tamb = 25 °C
(2) IC/IB = 50
(3) Tamb = −55 °C
(3) IC/IB = 10
Fig. 12. Collector-emitter saturation voltage as a
function of collector current; typical values
PBSS5330PAS
Product data sheet
- 10
- 102
- 103
- 104
IC (mA)
Fig. 13. Collector-emitter saturation voltage as a
function of collector current; typical values
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PBSS5330PAS
NXP Semiconductors
30 V, 3 A PNP low VCEsat (BISS) transistor
006aac042
102
006aac043
103
RCEsat
(Ω)
RCEsat
(Ω)
102
10
10
(1)
1
1
10- 1
(1)
(2)
10- 2
- 10- 1
-1
- 10
- 102
(2)
(3)
10- 1
(3)
- 103
- 104
IC (mA)
10- 2
- 10- 1
-1
IC/IB = 20
Tamb = 25 °C
(1) Tamb = 100 °C
(1) IC/IB = 100
(2) Tamb = 25 °C
(2) IC/IB = 50
(3) Tamb = −55 °C
(3) IC/IB = 10
Fig. 14. Collector-emitter saturation resistance as a
function of collector current; typical values
PBSS5330PAS
Product data sheet
- 10
- 102
- 103
- 104
IC (mA)
Fig. 15. Collector-emitter saturation resistance as a
function of collector current; typical values
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PBSS5330PAS
NXP Semiconductors
30 V, 3 A PNP low VCEsat (BISS) transistor
11. Test information
IB
input pulse
(idealized waveform)
90 %
IBon (100 %)
10 %
IBoff
output pulse
(idealized waveform)
IC
90 %
IC (100 %)
10 %
t
td
ts
tr
ton
tf
toff
006aaa003
Fig. 16. BISS transistor switching time definition
VBB
RB
(probe)
oscilloscope
450 Ω
VCC
RC
Vo
(probe)
450 Ω
R2
VI
oscilloscope
DUT
R1
mlb826
Fig. 17. Test circuit for switching times
11.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is
suitable for use in automotive applications.
PBSS5330PAS
Product data sheet
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PBSS5330PAS
NXP Semiconductors
30 V, 3 A PNP low VCEsat (BISS) transistor
12. Package outline
DFN2020D-3: plastic thermal enhanced ultra thin small outline package; no leads;
3 terminals; body 2 x 2 x 0.65 mm
X
v
bp
A B
A
D
SOT1061D
B
A
A1
E
detail X
pin 1
index area
pin 1
index area
solderable lead
end, protrusion
max. 0.02 mm (3x)
e
1
C
y1 C
2
Lp
e1
visible depend upon
used manufacturing
technology (6x)
E1
3
D1
0
1
mm
A(1)
A1
bp
max 0.65 0.04 0.35
nom
min
0.25
2 mm
scale
Dimensions (mm are the original dimensions)
Unit
y
D
D1
E
E1
2.1
1.6
2.1
1.1
1.9
1.4
1.9
0.9
e
1.3
e1
Lp
0.3
0.45
0.2
0.35
v
0.1
y
y1
0.05 0.05
Note
1. Dimension A is including plating thickness
Outline
version
SOT1061D
sot1061d_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
14-03-11
14-03-12
---
Fig. 18. Package outline DFN2020D-3 (SOT1061D)
PBSS5330PAS
Product data sheet
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PBSS5330PAS
NXP Semiconductors
30 V, 3 A PNP low VCEsat (BISS) transistor
13. Soldering
Footprint information for reflow soldering of DFN2020D-3 package
SOT1061D
2.1
1.7
1.3
0.4 (2x)
0.5 (2x)
0.3 (2x)
0.5 (2x) 0.6 (2x) 0.7 (2x)
0.25
1.1
2.5
0.35
0.3
0.25
2.3
0.25
1
0.35
1.1
0.35
1.2
0.35
0.3
0.4
0.5
1.5
1.6
1.7
occupied area
solder resist
solder lands
solder paste
Dimensions in mm
Issue date
14-03-05
14-03-12
sot1061d_fr
Fig. 19. Reflow soldering footprint for DFN2020D-3 (SOT1061D)
PBSS5330PAS
Product data sheet
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PBSS5330PAS
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30 V, 3 A PNP low VCEsat (BISS) transistor
14. Revision history
Table 8.
Revision history
Data sheet ID
Release date
Data sheet status
Change notice
Supersedes
PBSS5330PAS v.1
20140911
Product data sheet
-
-
PBSS5330PAS
Product data sheet
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PBSS5330PAS
NXP Semiconductors
30 V, 3 A PNP low VCEsat (BISS) transistor
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
15. Legal information
15.1 Data sheet status
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Document
status [1][2]
Product
status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Preliminary
[short] data
sheet
Qualification
This document contains data from the
preliminary specification.
Product
[short] data
sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Definition
Please consult the most recently issued document before initiating or
completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the Internet at URL http://www.nxp.com.
15.2 Definitions
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
PBSS5330PAS
Product data sheet
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their
applications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
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PBSS5330PAS
NXP Semiconductors
30 V, 3 A PNP low VCEsat (BISS) transistor
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, ICODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight,
MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug,
TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP
Semiconductors N.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
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Product data sheet
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PBSS5330PAS
NXP Semiconductors
30 V, 3 A PNP low VCEsat (BISS) transistor
16. Contents
1
General description ............................................... 1
2
Features and benefits ............................................1
3
Applications ........................................................... 1
4
Quick reference data ............................................. 1
5
Pinning information ............................................... 2
6
Ordering information ............................................. 2
7
Marking ................................................................... 2
8
Limiting values .......................................................3
9
Thermal characteristics .........................................4
10
Characteristics ....................................................... 8
11
11.1
Test information ................................................... 12
Quality information ............................................. 12
12
Package outline ................................................... 13
13
Soldering .............................................................. 14
14
Revision history ................................................... 15
15
15.1
15.2
15.3
15.4
Legal information .................................................16
Data sheet status ............................................... 16
Definitions ...........................................................16
Disclaimers .........................................................16
Trademarks ........................................................ 17
© NXP Semiconductors N.V. 2014. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 11 September 2014
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Product data sheet
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11 September 2014
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18 / 18
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