DATASHEET

HA-2540
®
Data Sheet
July 2003
400MHz, Fast Settling Operational
Amplifier
FN2897.5
Features
• Very High Slew Rate . . . . . . . . . . . . . . . . . . . . . . 400V/µs
The Intersil HA-2540 is a wideband, very high slew rate,
monolithic operational amplifier featuring superior speed and
bandwidth characteristics. Bipolar construction coupled with
dielectric isolation allows this truly differential device to
deliver outstanding performance in circuits where closed
loop gain is 10 or greater. Additionally, the HA-2540 has a
drive capability of ±10V into a 1kΩ load. Other desirable
characteristics include low input voltage noise, low offset
voltage, and fast settling time.
A 400V/µs slew rate ensures high performance in video and
pulse amplification circuits, while the 400MHz gainbandwidth product is ideally suited for wideband signal
amplification. A settling time of 140ns also makes the
HA-2540 an excellent selection for high speed Data
Acquisition Systems.
Refer to Application Note AN541 and Application Note
AN556 for more information on High Speed Op Amp
applications.
• Fast Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . 140ns
• Wide Gain Bandwidth (AV ≥ 10). . . . . . . . . . . . . . 400MHz
• Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 6MHz
• Low Offset Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 8mV
• Input Voltage Noise . . . . . . . . . . . . . . . . . . . . . . . 6nV/√Hz
• Output Voltage Swing . . . . . . . . . . . . . . . . . . . . . . . ±10V
• Monolithic Bipolar Construction
Applications
• Pulse and Video Amplifiers
• Wideband Amplifiers
• High Speed Sample-Hold Circuits
• Fast, Precise D/A Converters
Ordering Information
For a lower power version of this product, please see
the HA-2850 datasheet.
PART
NUMBER
HA1-2540-5
TEMP.
RANGE (oC)
0 to 75
PACKAGE
14 Ld CERDIP
PKG. DWG. #
F14.3
Pinout
HA-2540 (CERDIP)
TOP VIEW
NC 1
14 NC
NC 2
13 NC
NC 3
12 NC
-IN 4
11 V+
-
+IN 5
+
10 OUTPUT
V- 6
9 NC
NC 7
8 NC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
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HA-2540
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 35V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
Output Current . . . . . . . . . . . . . . 33mARMS Continuous, 50mAPEAK
Thermal Resistance (Typical, Note 2)
θJA (oC/W) θJC (oC/W)
CERDIP Package. . . . . . . . . . . . . . . . .
75
20
Maximum Internal Power Dissipation (Note 1)
Maximum Junction Temperature (Ceramic Package) . . . . . . 175oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range
HA-2540-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Maximum power dissipation with load conditions must be designed to maintain the maximum junction temperature below 175oC for the ceramic
package, and below 150oC for the plastic package. By using Application Note AN556 on Safe Operating Area Equations, along with the thermal
resistances, proper load conditions can be determined. Heat sinking is recommended above 75oC.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
VSUPPLY = ±15V, RL = 1kΩ, CL < 10pF, Unless Otherwise Specified
Electrical Specifications
TEMP (oC)
MIN
TYP
MAX
UNITS
25
-
8
15
mV
Full
-
13
20
mV
Average Offset Voltage Drift
Full
-
20
-
µV/oC
Bias Current
25
-
5
20
µA
Full
-
-
25
µA
25
-
1
6
µA
PARAMETER
INPUT CHARACTERISTICS
Offset Voltage
Offset Current
Full
-
-
8
µA
Input Resistance
25
-
10
-
kΩ
Input Capacitance
25
-
1
-
pF
Common Mode Range
Full
±10
-
-
V
Input Noise Current (f = 1kHz, RSOURCE = 0Ω)
25
-
6
-
pA/√Hz
Input Noise Voltage (f = 1kHz, RSOURCE = 0Ω)
25
-
6
-
nV/√Hz
Large Signal Voltage Gain (Note 3)
25
10
15
-
kV/V
Full
5
-
-
kV/V
Common-Mode Rejection Ratio (Note 4)
Full
60
72
-
dB
Minimum Stable Gain
25
10
-
-
V/V
Gain Bandwidth Product (Notes 5, 6)
25
-
400
-
MHz
Output Voltage Swing (Notes 3, 10)
Full
±10
-
-
V
Output Current (Note 3)
25
±10
±20
-
mA
Output Resistance
25
-
30
-
Ω
Full Power Bandwidth (Notes 3, 7)
25
5.5
6
-
MHz
Rise Time
25
-
14
-
ns
Overshoot
25
-
5
-
%
Slew Rate
25
320
400
-
V/µs
Settling Time: 10V Step to 0.1%
25
-
140
-
ns
TRANSFER CHARACTERISTICS
OUTPUT CHARACTERISTICS
TRANSIENT RESPONSE (Note 8)
2
HA-2540
VSUPPLY = ±15V, RL = 1kΩ, CL < 10pF, Unless Otherwise Specified (Continued)
Electrical Specifications
TEMP (oC)
PARAMETER
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Supply Current
Full
-
20
25
mA
Power Supply Rejection Ratio (Note 9)
Full
60
70
-
dB
NOTES:
3. RL = 1kΩ, VO = ±10V.
4. VCM = ±10V.
5. VO = 90mV.
6. AV = 10.
Slew Rate
7. Full power bandwidth guaranteed based on slew rate measurement using: FPBW = --------------------------- .
2πV PEAK
8. Refer to Test Circuits section of the data sheet.
9. VSUPPLY = +5V, -15V and +15V, -5V.
10. Guaranteed range for output voltage is ±10V. Functional operation outside of this range is not guaranteed.
Test Circuits and Waveforms
VIN
+
VOUT
-
900
NOTES:
11. AV = +10.
12. CL ≤ 10pF.
100
FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT
A
B
Vertical Scale: A = 0.5V/Div., B = 5.0V/Div.
Horizontal Scale: 50ns/Div.
Vertical Scale: Input = 10mV/Div.; Output = 50mV/Div.
Horizontal Scale: 20ns/Div.
LARGE SIGNAL RESPONSE
SMALL SIGNAL RESPONSE
0.001µF
V+
NOTES:
1µF
INPUT
200Ω
OUTPUT
-
+
15. It is recommended that resistors be carbon composition and the
feedback and summing network ratios be matched to 0.1%.
0.001µF
PROBE
MONITOR
500Ω
1µF
VSETTLE
POINT
2kΩ
13. AV = -10.
14. Load Capacitance should be less than 10pF. Turn on time delay
typically 4ns.
16. SETTLE POINT (Summing Node) capacitance should be less
than 10pF. For optimum settling time results, it is recommended
that the test circuit be constructed directly onto the device pins. A
Tektronix 568 Sampling Oscilloscope with S-3A sampling heads
is recommended as a settle point monitor.
5kΩ
FIGURE 2. SETTLING TIME TEST CIRCUIT
3
HA-2540
Schematic Diagram
R2
R1
R23
QP18
V+
R4
R3
QP28
QP22
QP6
QP17
QP19
R24
R5
R13
V-
QP5
QP25
R22
C2
C1
V-
RC2
QN2
QN1
QN7
QN9
R7
R6
QP8
+ INPUT
R18
OUTPUT
QP23
R9
R8
QN21
R19
QN10
QP4
QP3
QP11
- INPUT
V+
R21
Z1
QN25
QN12
V+
R25
R10
QN20
DZ1
QN14
DZ2
R11
R16
QN15
QN13
QN16
R12
QN29
R14
R15
R17
V-
Typical Applications
R1
4K
2K
C1 (NOTE 18)
200
-
+
10K
1K
R2
4K
HA-2540
CF (NOTE 17)
V+
OFFSET
ADJUST
1K
V-
V+
-
SIGNAL
OUT
HA-2540
+
0.1µF
R5
(NOTE 19)
2K
NOTES:
NOTE: With one HA-2540 and two low capacitance
switching diodes, signals exceeding 10MHz can be
separated. This circuit is most useful for full wave
rectification, AM detectors or sync generation.
FIGURE 3. WIDEBAND SIGNAL SPLITTER
R4
4K
V-
17. Used for experimental purposes. CF ≅ 3pF.
18. C1 is optional (0.001µF → 0.01µF ceramic).
19. R5 is optional and can be utilized to reduce input signal
amplitude and/or balance input conditions. R5 = 500Ω to 1kΩ.
FIGURE 4. BOOTSTRAPPING FOR MORE OUTPUT
CURRENT AND VOLTAGE SWING
Refer to Application Note AN541 For Further Application Information.
4
R3
4K
HA-2540
Typical Performance Curves
28
100
OUTPUT VOLTAGE SWING (VP-P)
CLOSED LOOP GAIN (dB)
90
80
70
60
50
40
30
20
10
20
1K
10K
100K
1M
10M
VS = ±10V
16
12
8
VS = ±5V
4
0
-10
100
VS = ±15V
24
0
1K
100M
10K
FREQUENCY (Hz)
28
24
20
16
12
8
4
0
200
400
600
800
1M
10M
100M
FIGURE 6. OUTPUT VOLTAGE SWING vs FREQUENCY
NORMALIZED PARAMETERS REFERRED TO
VALUES AT 25oC
OUTPUT VOLTAGE SWING (VP-P)
FIGURE 5. CLOSED LOOP FREQUENCY RESPONSE
0
100K
FREQUENCY (Hz)
1K
1.2K
1.4
1.3
1.2
1.1
BANDWIDTH
1.0
SLEW RATE
0.9
0.8
0.7
0.6
-80
-40
0
40
80
120
160
TEMPERATURE (oC)
RESISTANCE (Ω)
FIGURE 7. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
FIGURE 8. NORMALIZED AC PARAMETERS vs
TEMPERATURE
28
10mV
1mV
6
4
2
0
-2
-4
1mV
-6
-8
VS = ±15V
24
8
SUPPLY CURRENT (mA)
OUTPUT VOLTAGE STEP (V)
10
10mV
20
16
VS = ±5V
12
8
4
-10
0
40
80
120
160
200
240
SETTLING TIME (ns)
FIGURE 9. SETTLING TIME FOR VARIOUS OUTPUT STEP
VOLTAGES
5
0
-80
-40
0
40
80
120
160
TEMPERATURE (oC)
FIGURE 10. POWER SUPPLY CURRENT vs TEMPERATURE
HA-2540
Typical Performance Curves
(Continued)
14
7
12
6
8
4
6
3
4
2
BIAS CURRENT
2
1
0
-80
-40
0
40
80
120
25
50
20
40
15
20
VOLTAGE
NOISE
5
0
10
10
100
TEMPERATURE (oC)
FIGURE 11. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs
TEMPERATURE
30
CURRENT NOISE
10
0
160
NOISE CURRENT (pA/√Hz)
5
OFFSET VOLTAGE
NOISE VOLTAGE (nV/√Hz)
10
|VIO| OFFSET VOLTAGE (mV)
INPUT BIAS CURRENT (µA)
RSOURCE = 0Ω, VS = ±15
1K
FREQUENCY (Hz)
0
100K
10K
FIGURE 12. INPUT NOISE VOLTAGE AND NOISE CURRENT vs
FREQUENCY
+40µV
VS = ±15, RL = 1K
+30µV
120
+20µV
100
CMRR (dB)
+10µV
0µV
-10µV
80
60
40
-20µV
20
-30µV
-40µV
0
1K
Vertical Scale: 10mV/Div.
Horizontal Scale: 50ms/Div.
FIGURE 13. BROADBAND NOISE (0.1Hz TO 1MHz)
10K
100K
FREQUENCY (Hz)
1M
10M
FIGURE 14. COMMON MODE REJECTION RATIO vs
FREQUENCY
100
100
0
80
60
POSITIVE SUPPLY
40
NEGATIVE SUPPLY
45
GAIN
60
PHASE
90
40
135
20
20
180
0
0
1K
10K
100K
FREQUENCY (Hz)
1M
10M
FIGURE 15. POWER SUPPLY REJECTION RATIO vs FREQUENCY
6
-10
100
225
1K
10K
100K
1M
10M
FREQUENCY (Hz)
100M
FIGURE 16. OPEN LOOP GAIN/PHASE vs FREQUENCY
PHASE (DEGREES)
OPEN LOOP GAIN (dB)
PSRR (dB)
80
HA-2540
Die Characteristics
DIE DIMENSIONS:
SUBSTRATE POTENTIAL (Powered Up):
62 mils x 76 mils x 19 mils
1575 µmx 1930µm x 483µm
VTRANSISTOR COUNT:
METALLIZATION:
30
Type: Al, 1% Cu
Thickness: 16kÅ ±2kÅ
PROCESS:
Bipolar Dielectric Isolation
PASSIVATION:
Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.)
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1.5kÅ
Metallization Mask Layout
HA-2540
V+
OUTPUT
V-
+IN
-IN
- IN
7
+ IN
HA-2540
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
E
M
-Bbbb S
C A-B S
-C-
S1
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.785
-
19.94
5
E
0.220
0.310
5.59
7.87
5
eA
e
ccc M
C A-B S
eA/2
c
aaa M C A - B S D S
D S
NOTES
-
b2
b
MAX
0.014
α
A A
MIN
b
A
L
MILLIMETERS
MAX
A
Q
SEATING
PLANE
MIN
M
(b)
D
BASE
PLANE
SYMBOL
b1
SECTION A-A
D S
INCHES
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
α
90o
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
14
14
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
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