EL8188 CT UCT ODU E P ROD t R P T ra TE OLE UBSTITU rt Cente tsc S B O uppo sil.com/ LE S Sheet SSIB hnical S .interData O P A w ec FOR act our T IL or ww cont -INTERS 8 1-88 ¬ February 24, 2011 Micropower Single Supply Rail-to-Rail Input-Output Precision Op Amp Features The EL8188 is a precision low power, operational amplifier. The device is optimized for single supply operation between 2.4V to 5.5V. This enables operation from one lithium cell or two Ni-Cd batteries. The input range includes both positive and negative rail. • 1mV Max Offset Voltage The EL8188 draws minimal supply current (55µA) while meeting excellent DC-accuracy, noise, and output drive specifications. • Rail-to-rail Input and Output • Typical 55µA Supply Current Ordering Information PART PART NUMBER MARKING EL8188FIZ-T7* (Note 2) 188Z TEMP RANGE (°C) FN7467.7 • Typical 1pA Input Bias Current • 266kHz Gain-bandwidth Product • Single Supply Operation Between 2.4V to 5.5V • Ground Sensing • Output Sources and Sinks 26mA Load Current • Pb-free (RoHS compliant) PACKAGE (Pb-Free) PKG. DWG. # -40 to +125 6 Ld WLCSP W3x2.6C (1.5mmx1.0mm) EL8188FWZ-T7A* BBYA (Notes 1, 3) -40 to +125 6 Ld SOT-23 P6.064A EL8188FWZ-T7* (Notes 1, 3) BBYA -40 to +125 6 Ld SOT-23 P6.064A EL8188ISZ (Note 1) 8188ISZ -40 to +125 8 Ld SOIC M8.15E EL8188ISZ-T7* (Note 1) 8188ISZ -40 to +125 8 Ld SOIC M8.15E EL8188ISZ-T13* (Note 1) 8188ISZ -40 to +125 8 Ld SOIC M8.15E Applications • Battery - or Solar-powered Systems • 4mA to 20mA Current Loops • Handheld Consumer Products • Medical Devices • Thermocouple Amplifiers • Photodiode Pre-amps • pH Probe Amplifiers Pinouts *Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD-020 2. These Intersil Pb-free WLCSP and BGA packaged products products employ special Pb-free material sets; molding compounds/die attach materials and SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. EL8188 (8 LD SO) TOP VIEW EL8188 (6 LD SOT-23) TOP VIEW OUT 1 V- 2 6 V+ + - IN+ 3 DNC 1 5 DNC IN- 2 4 IN- IN+ 3 V- 4 8 DNC + 7 V+ 6 OUT 5 DNC EL8188 (6 LD WLCSP) TOP VIEW 1 2 A DNC OUT B V+ V- C IN- IN+ 3. The part marking is located on the bottom of the part. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. Copyright Intersil Americas Inc. 2004-2009, 2011. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL8188 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage (VS) and Pwr-up Ramp Rate . . . . . . . 5.75V, 1V/µs Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Current into IN+, IN-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V to V+ +0.5V ESD Tolerance Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Thermal Resistance θJA (°C/W) 6 Ld SOT Package . . . . . . . . . . . . . . . . . . . . . . . . . 230 6 Ld WLCSP Package . . . . . . . . . . . . . . . . . . . . . . . 130 8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 125 Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . -65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, VO = 2.5V, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C PARAMETER VOS DESCRIPTION Input Offset Voltage TEST CONDITIONS SOT-23 WLCSP ΔV OS -----------------ΔTime Long Term Input Offset Voltage Stability ΔV OS ---------------ΔT Input Offset Drift vs Temperature IB Input Bias Current (See Figure 20) MIN (Note 4) TYP MAX (Note 4) UNIT -1 0.05 +1 mV -1.5 +1.5 mV -1.5 +1.5 mV -25 3 µV/Mo 1.1 µV/°C 1 -600 25 pA 600 pA Input Noise Voltage Peak-to-Peak f = 0.1Hz to 10Hz 2.8 µVP-P Input Noise Voltage Density fO = 1kHz 48 nV/√Hz iN Input Noise Current Density fO = 1kHz 0.15 pA/√Hz CMIR Input Voltage Range Guaranteed by CMRR test 0 CMRR Common-Mode Rejection Ratio VCM = 0V to 5V 80 eN 5 100 dB 75 PSRR Power Supply Rejection Ratio VS = 2.4V to 5.5V 80 dB 100 dB 80 AVOL VOUT Large Signal Voltage Gain Maximum Output Voltage Swing SOT-23 VO = 0.5V to 4.5V, RL = 100kΩ to (V+ + V-)/2 100 VOL; Output low, RL = 1kΩ to (V+ + V-)/2 2 dB 400 V/mV 100 VOL; Output low, RL = 100kΩ to (V+ + V-)/2 VOH; Output high, RL = 100kΩ to (V+ + V-)/2 4.994 VOH; Output high, RL = 1kΩ to (V+ + V-)/2 4.750 V/mV 3 10 mV 130 250 mV 350 mV 4.9975 4.994 4.7 V V V 4.875 V V FN7467.7 February 24, 2011 EL8188 Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, VO = 2.5V, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C (Continued) PARAMETER VOUT DESCRIPTION Maximum Output Voltage Swing WLCSP TEST CONDITIONS MIN (Note 4) VOL; Output low, RL = 100kΩ to (V+ + V-)/2 VOL; Output low, RL = 1kΩ to (V+ + V-)/2 SR TYP MAX (Note 4) UNIT 3 10 mV 130 250 mV 350 mV VOH; Output high, RL = 100kΩ to (V+ + V-)/2 4.991 4.997 V VOH; Output high, RL = 1kΩ to (V+ + V-)/2 4.750 4.875 V Slew Rate 4.7 0.1 V 0.15 0.07 GBWP Gain Bandwidth Product fO = 100kHz IS, ON Supply Current, Enabled SOT-23 35 55 45 65 40 ISC+ Short Circuit Output Current RL = 10Ω to opposite supply V/µs 0.25 V/µs 266 30 WLCSP 0.19 23 kHz 75 µA 85 µA 85 µA 95 µA 31 mA 18 ISC- Short Circuit Output Current RL = 10Ω to opposite supply 20 mA 26 mA 15 VS Supply Voltage Guaranteed by PSRR mA 2.4 5.5 V 2.4 5.5 V NOTE: 4. .Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 3 FN7467.7 February 24, 2011 EL8188 Typical Performance Curves VS = ±2.5V, TA = +25°C, Unless Otherwise Specified 1 80 RL ≥ 10k VOUT = 0.2VP-P 50 VS = ±1.2 GAIN (dB) -1 VS = ±2.5 GAIN = 200 40 GAIN = 100 GAIN = 10 30 GAIN = 5 20 10 -2 GAIN = 2 0 VS = ±1.0 -3 1k 10k -10 100k -20 1M GAIN = 1 1 10 100 FREQUENCY (Hz) 200 INPUT OFFSET VOLTAGE (µV) SUPPLY CURRENT (µA) 60 50 40 30 20 10 2.5 3.0 4.0 3.5 4.5 5.0 10M 100 0 -100 -200 -0.5 5.5 0.5 1.5 2.5 3.5 4.5 5.5 OUTPUT VOLTAGE (V) FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 4. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE 100 250 150 GAIN (dB) NORMALIZED INPUT OFFSET VOLTAGE (µV) 100k 1M AV = -1 VCM = VDD/2 SUPPLY VOLTAGE (V) 50 -50 80 0 60 45 PHASE -150 90 40 20 -250 -0.5 10k FIGURE 2. FREQUENCY RESPONSE at VARIOUS CLOSED LOOP GAINS FIGURE 1. UNITY GAIN FREQUENCY RESPONSE at VARIOUS SUPPLY VOLTAGES 0 2.0 1k FREQUENCY (Hz) 135 GAIN 180 0 0.5 1.5 2.5 3.5 4.5 5.5 COMMON-MODE INPUT VOLTAGE (V) FIGURE 5. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 4 -20 10 PHASE SHIFT (°) GAIN (dB) GAIN = 500 60 0 RL ≥ 10k VOUT = 0.2VP-P GAIN = 1k 70 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 6. OPEN LOOP GAIN AND PHASE vs FREQUENCY (RL = 1kΩ) FN7467.7 February 24, 2011 EL8188 Typical Performance Curves (Continued) VS = ±2.5V, TA = +25°C, Unless Otherwise Specified (Continued) 100 10 90 0 80 -10 -20 90 50 PHASE 40 135 30 20 180 GAIN 10 CMRR (dB) 60 PHASE SHIFT (°) 70 GAIN (dB) ΔVCM = 1VP-P RL = 100kΩ AV = +1 -30 -40 -50 -60 -70 -80 0 -90 -10 10 -100 10 100 1k 10k 100k 1M 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 8. CMRR vs FREQUENCY FIGURE 7. OPEN LOOP GAIN AND PHASE vs FREQUENCY (RL = 100kΩ) 100 1000 10 ΔVS = 1VP-P RL = 100kΩ -10 AV = +1 -20 -PSRR -40 -50 +PSRR -60 -70 -80 100 1 10 CURRENT -90 -100 10 10 VOLTAGE CURRENT NOISE (pA/√Hz) VOLTAGE NOISE (√µV) -30 100 1k 10k FREQUENCY (Hz) 100k 1 1M FIGURE 9. PSRR vs FREQUENCY 1 10 100 1k 10k 0.1 100k FREQUENCY (Hz) FIGURE 10. INPUT VOLTAGE AND CURRENT NOISE vs FREQUENCY 20 15 VOS DRIFT (µV) VOLTAGE NOISE (500nV/DIV) PSRR (dB) 0 2.8µVP-P 10 5 0 -5 -10 TIME (1s/DIV) FIGURE 11. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE 5 -15 0 500 1000 1500 1800 TIME (HOURS) FIGURE 12. VOS DRIFT (SOT-23 PACKAGE) vs TIME FN7467.7 February 24, 2011 EL8188 Typical Performance Curves (Continued) VS = ±2.5V, TA = +25°C, Unless Otherwise Specified (Continued) 75 85 n = 1500 MAX 70 MAX 75 CURRENT (µA) CURRENT (mA) 65 MEDIAN 60 55 50 MIN 45 70 65 MEDIAN 60 MIN 55 40 35 -40 n = 5000 80 50 -20 0 20 40 60 80 100 45 -40 120 -20 0 FIGURE 13. SOT-23 SUPPLY CURRENT vs TEMPERATURE, VS = ±2.5V n = 1500 200 400 100 200 VOS (√µV) VOS (√µV) 80 100 120 MEDIAN -100 MEDIAN 0 -200 -400 -200 MIN 0 20 40 60 80 MIN -600 -300 -20 n = 1500 MAX 600 0 100 -800 -40 120 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 15. SOT-23 VOS vs TEMPERATURE, VS = ±2.5V FIGURE 16. SOT-23 VOS vs TEMPERATURE, VS = ±1.2V 1500 1500 n = 5000 n = 5000 1000 MAX 1000 MAX 500 500 VOS (µV) VOS (µV) 60 FIGURE 14. WLCSP SUPPLY CURRENT vs TEMPERATURE, VS = ±2.5V MAX 300 0 MEDIAN -500 0 MEDIAN -500 -1000 -1500 -40 40 800 400 -400 -40 20 TEMPERATURE (°C) TEMPERATURE (°C) MIN -20 0 20 40 60 80 TEMPERATURE (°C) -1000 100 120 FIGURE 17. WLCSP VOS vs TEMPERATURE, VS = ±2.5V 6 -1500 -40 MIN -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 18. WLCSP VOS vs TEMPERATURE, VS = ±1.2V FN7467.7 February 24, 2011 EL8188 Typical Performance Curves 160 (Continued) VS = ±2.5V, TA = +25°C, Unless Otherwise Specified (Continued) n = 1500 140 MAX 100 IBIAS -(pA) IBIAS + (pA) 120 80 60 MEDIAN 40 20 MIN 0 -20 -40 -20 0 20 40 60 80 100 120 250 n = 1500 230 210 190 170 150 130 110 90 70 50 30 10 -10 -40 -20 0 FIGURE 19. IBIAS+ vs TEMPERATURE, VS = ±2.5V 125 MAX n = 1500 40 60 80 100 120 110 105 MEDIAN 100 95 115 110 MEDIAN 105 100 95 90 MIN 85 80 -40 MAX n = 1500 120 PSRR (dB) CMRR (dB) 20 130 115 -20 0 20 40 60 80 MIN 90 100 85 -40 120 -20 0 40 60 80 100 120 FIGURE 22. PSRR vs TEMPERATURE ±1.5V TO ±2.5V FIGURE 21. CMRR vs TEMPERATURE, V+ = ±2.5V, ±1.5V 4.9984 4.90 n = 1500 4.89 n = 1500 4.9982 4.9980 MAX MAX 4.9978 VOUT (V) 4.88 4.87 MEDIAN 4.86 4.9976 4.9974 MEDIAN 4.9972 4.9970 4.9968 4.85 4.9964 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 23. VOUT HIGH vs TEMPERATURE, VS = ±2.5V, RL = 1k 7 MIN 4.9966 MIN 4.84 -40 20 TEMPERATURE (°C) TEMPERATURE (°C) VOUT (V) MIN FIGURE 20. IBIAS- vs TEMPERATURE, VS = ±2.5V 130 120 MEDIAN TEMPERATURE (°C) TEMPERATURE (°C) 125 MAX -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 24. VOUT HIGH vs TEMPERATURE, VS = ±2.5V, RL = 100k FN7467.7 February 24, 2011 EL8188 Typical Performance Curves 190 180 (Continued) VS = ±2.5V, TA = +25°C, Unless Otherwise Specified (Continued) 5.0 n = 1500 4.4 160 MEDIAN VOUT (mV) VOUT (mV) MAX 4.6 170 150 140 MIN 130 MEDIAN 4.2 4.0 MIN 3.8 3.6 120 3.4 110 3.2 100 n = 1500 4.8 MAX -40 -20 0 20 40 60 80 100 3.0 120 -40 -20 TEMPERATURE (°C) 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 26. VOUT LOW vs TEMPERATURE, VS = ±2.5V, RL = 100k FIGURE 25. VOUT LOW vs TEMPERATURE, VS = ±2.5V, RL = 1k 510 n = 1500 MAX 460 AVOL (V/mV) 410 360 MEDIAN 310 260 MIN 210 160 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 27. AVOL vs TEMPERATURE, RL = 100k, VO = ±2V @ VS = ±2.5V 8 FN7467.7 February 24, 2011 EL8188 Pin Descriptions 8 LD SOIC SOT-23 PIN 6 Ld WLCSP EQUIVALENT PIN NUMBER NUMBER PIN NUMBER PIN NAME CIRCUIT 1, 5 DNC DESCRIPTION Do Not Connect; Internal connection - Must be left floating. 2 4 C1 IN- Circuit 1 Amplifier’s inverting input 3 3 C2 IN+ Circuit 1 Amplifier’s non-inverting input 4 2 B2 V- Circuit 3 Negative power supply 8 5 A1 DNC 6 1 A2 OUT Circuit 2 Amplifier’s output 7 6 B1 V+ Circuit 3 Positive power supply Do not connect. Pin must be left floating. V+ IN- V+ CAPACITIVELY COUPLED ESD CLAMP OUT IN+ V- VCIRCUIT 1 V+ V- CIRCUIT 2 Application Information Introduction The EL8188 is a rail-to-rail input and output (RRIO), micro-power, precision, single supply op amp. This amplifier is designed to operate from single supply (2.4V to 5.5V) or dual supply (±1.2V to ±2.75V) while drawing only 55µA of supply current.The device achieves rail-to-rail input and output operation while eliminating the drawbacks of many conventional RRIO op amps. Rail-to-Rail Input The PFET input stage of the EL8188 has an input common-mode voltage range that includes the negative and positive supplies without introducing offset errors or degrading performance like some existing rail-to-rail input op amps. Many rail-to-rail input stages use two differential input pairs: a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties result from using this topology. As the input signal moves from one supply rail to the other, the op amp switches from one input pair to the other causing changes in input offset voltage and an undesired change in the input offset current’s magnitude and polarity. The EL8188 achieves rail-to-rail input performance without sacrificing important precision specifications and without degrading distortion performance. The EL8188's input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. Rail-to-Rail Output A pair of complementary MOSFET devices achieves rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction, while the PMOS sources current to 9 CIRCUIT 3 swing the output in the positive direction. The EL8188 with a 100kΩ load swings to within 3mV of the supply rails. Results of Over-Driving the Output Caution should be used when over-driving the output for long periods of time. Over-driving the output can occur in three ways: 1. The input voltage times the gain of the amplifier exceeds the supply voltage by a large value. 2. The output current required is higher than the output stage can deliver. 3. Operating the device in Slew Rate Limit. These conditions can result in a shift in the Input Offset Voltage (VOS) as much as 1µV/hr of exposer under these condition. IN+ and IN- Input Protection In addition to ESD protection diodes to each supply rail, the EL8188 has additional back-to-back protection diodes across the differential input terminals (see “Circuit 1” diagram on page 8). If the magnitude of the differential input voltage exceeds the diode’s VF, then one of these diodes will conduct. For elevated temperatures, the leakage of the protection diodes (Circuit 1 pin description table) increases, resulting in the increase in Ibias as seen in Figures 19 and 20. Usage Implications If the input differential voltage is expected to exceed 0.5V, an external current limiting resistor must be used to ensure the input current never exceeds 5mA. For noninverting unity gain applications the current limiting can be via a series IN+ resistor, or via a feedback resistor of appropriate value. For other gain configurations, the series IN+ resistor is the best choice, unless the feedback (RF) and gain setting (RG) resistors are both sufficiently large to limit the input current to 5mA. FN7467.7 February 24, 2011 EL8188 Large differential input voltages can arise from several sources: 1) During open loop (comparator) operation. The IN+ and INinput voltages don’t track. 2) When the amplifier is disabled but an input signal is still present. An RL or RG to GND keeps the IN- at GND, while the varying IN+ signal creates a differential voltage. Mux Amp applications are similar, except that the active channel VOUT determines the voltage on the IN- terminal. 3) When the slew rate of the input pulse is considerably faster than the op amp’s slew rate. If the VOUT can’t keep up with the IN+ signal, a differential voltage results, and visible distortion occurs on the input and output signals. To avoid this issue, keep the input slew rate below 0.2V/µs, or use appropriate current limiting resistors. Output Current Limiting The EL8188 has no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the “Absolute Maximum Rating” for “operating junction temperature”, potentially resulting in the destruction of the device. Proper Layout Maximizes Precision To achieve the optimum levels of high input impedance (i.e., low input currents) and low offset voltage, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. When input leakage current is a paramount concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 28 shows a guard ring example for a unity gain amplifier that uses the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. For further reduction of leakage currents, mount components to the PC board using Teflon standoffs. HIGH IMPEDANCE INPUT V+ IN Power Dissipation It is possible to exceed the +150°C maximum junction temperature (TJMAX) under certain load and power-supply conditions. It is therefore important to calculate TJMAX for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related as follows: T JMAX = T MAX + ( θ JA × PD MAX ) FIGURE 28. GUARD RING EXAMPLE FOR UNITY GAIN AMPLIFIER Typical Applications (EQ. 1) GENERAL PURPOSE COMBINATION pH PROBE where PDMAX is calculated using: V OUTMAX PD MAX = V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------R V+ + EL8188 V- + 3V COAX L (EQ. 2) where: • TMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation of the amplifier • VS = Supply voltage • IMAX = Maximum supply current of the amplifier • VOUTMAX = Maximum output voltage swing of the application FIGURE 29. pH PROBE AMPLIFIER A general-purpose combination pH probe has extremely high output impedance typically in the range of 10GΩ to 12GΩ. Low loss and expensive Teflon cables are often used to connect the pH probe to the meter electronics. Figure 29 details a low-cost alternative solution using the EL8188 and a low-cost coax cable. The EL8188 PMOS high impedance input senses the pH probe output signal and buffers it to drive the coax cable. Its rail-to-rail input nature also eliminates the need for a bias resistor network required by other amplifiers in the same application. • RL = Load resistance 10 FN7467.7 February 24, 2011 EL8188 R4 100kΩ R3 10kΩ R2 K TYPE THERMOCOUPLE 10kΩ V+ + EL8188 V- 410µV/°C + 5V R1 100kΩ FIGURE 30. THERMOCOUPLE AMPLIFIER Thermocouples are the most popular temperature sensing devices because of their low cost, interchangeability, and ability to measure a wide range of temperatures. In Figure 30, the EL8188 converts the differential thermocouple voltage into single-ended signal with 10X gain. The EL8188's rail-to-rail input characteristic allows the thermocouple to be biased at ground and permits the op amp to operate from a single 5V supply. 11 FN7467.7 February 24, 2011 EL8188 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (0.60) (1.27) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN 12 FN7467.7 February 24, 2011 EL8188 Package Outline Drawing P6.064A 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE Rev 0, 2/10 1.90 0-3° 0.95 D 0.08-0.20 A 5 6 4 PIN 1 INDEX AREA 2.80 3 1.60 3 0.15 C D 2x 1 (0.60) 3 2 0.20 C 2x 0.40 ±0.05 B 5 SEE DETAIL X 3 0.20 M C A-B D TOP VIEW 2.90 5 END VIEW 10° TYP (2 PLCS) 0.15 C A-B 2x H 1.14 ±0.15 C SIDE VIEW 0.10 C 0.05-0.15 1.45 MAX SEATING PLANE DETAIL "X" (0.25) GAUGE PLANE 0.45±0.1 4 (0.60) (1.20) NOTES: (2.40) (0.95) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 3. Dimension is exclusive of mold flash, protrusions or gate burrs. 4. Foot length is measured at reference to guage plane. 5. This dimension is measured at Datum “H”. 6. Package conforms to JEDEC MO-178AA. (1.90) TYPICAL RECOMMENDED LAND PATTERN 13 FN7467.7 February 24, 2011 EL8188 Wafer Level Chip Scale Package (WLCSP) W3x2.6C 3x2 ARRAY 6 BALL WAFER LEVEL CHIP SCALE PACKAGE E D PIN 1 ID TOP VIEW A2 A A1 SYMBOL MILLIMETERS A 0.51 Min, 0.55 Max A1 0.225 ±0.015 A2 0.305 ±0.013 b Φ0.323 ±0.025 D 0.955 ±0.020 D1 0.50 BASIC E 1.455 ±0.020 E1 1.00 BASIC e 0.50 BASIC SD 0.25 BASIC SE 0.00 BASIC Rev. 3 03/08 b NOTES: SIDE VIEW 1. All dimensions are in millimeters. E1 e SE D1 2 SD 1 b C B A BOTTOM VIEW All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN7467.7 February 24, 2011