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HA5024
ESIGNS
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Data
February 8, 2006
REC
HA5023
Quad 125MHz Video Current
Feedback Amplifier with Disable
Features
• Quad Version of HA-5020
The HA5024 is a quad version of the popular Intersil
HA5020. It features wide bandwidth and high slew rate, and
is optimized for video applications and gains between 1 and
10. It is a current feedback amplifier and thus yields less
bandwidth degradation at high closed loop gains than
voltage feedback amplifiers.
The low differential gain and phase, 0.1dB gain flatness, and
ability to drive two back terminated 75cables, make this
amplifier ideal for demanding video applications.
The HA5024 also features a disable function that
significantly reduces supply current while forcing the output
to a true high impedance state. This functionality allows 2:1
and 4:1 video multiplexers to be implemented with a single IC.
The current feedback design allows the user to take
advantage of the amplifier’s bandwidth dependency on the
feedback resistor. By reducing RF, the bandwidth can be
increased to compensate for decreases at higher closed
loop gains or heavy output loads.
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
HA5024IP
-40 to 85
20 Ld PDIP
E20.3
HA5024IPZ
(Note)
HA5024IPZ
-40 to 85
20 Ld PDIP*
(Pb-free)
E20.3
HA5024IB
HA5024IB
-40 to 85
20 Ld SOIC
M20.3
HA5024IBZ
(Note)
HA5024IBZ
-40 to 85
20 Ld SOIC
(Pb-free)
M20.3
HA5024IBZ96 HA5024IBZ
(See Note)
-40 to 85
M20.3
20 Ld SOIC
Tape and Reel
(Pb-free)
High Speed Op Amp DIP Evaluation
Board
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
• Individual Output Enable/Disable
• Input Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . 800V
• Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . . 125MHz
• Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475V/s
• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.03%
• Differential Phase . . . . . . . . . . . . . . . . . . . . . 0.03 Degrees
• Supply Current (per Amplifier) . . . . . . . . . . . . . . . . 7.5mA
• ESD Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000V
• Guaranteed Specifications at 5V Supplies
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Video Multiplexers; Video Switching and Routing
• Video Gain Block
• Video Distribution Amplifier/RGB Amplifier
• Flash A/D Driver
PKG.
DWG. #
HA5024IP
HA5024EVAL
3550.6
• Current to Voltage Converter
• Medical Imaging
• Radar and Imaging Systems
Pinout
HA5024
(PDIP, SOIC)
TOP VIEW
OUT1
1
20 OUT4
-IN1
2
+IN1
3
DIS1
4
17 DIS4
NC
5
16 NC
V+
6
15 V-
DIS2
7
14 DIS3
+IN2
8
-IN2
9
OUT2 10
-
+
+
-
-
+
+
-
19 -IN4
18 +IN4
13 +IN3
12 -IN3
11 OUT3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1998, 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HA5024
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . 36V
DC Input Voltage (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V
Output Current (Note 4) . . . . . . . . . . . . . . . . Short Circuit Protected
ESD Rating (Note 3)
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V
Thermal Resistance (Typical, Note 2)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . 4.5V to 15V
JA (°C/W)
PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
Maximum Junction Temperature (Note 1) . . . . . . . . . . . . . . . . . 175°C
Maximum Junction Temperature (Plastic Package, Note 1) . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Maximum power dissipation, including output load, must be designed to maintain junction temperature below 175°C for die, and below 150°C
for plastic packages. See Application Information section for safe operating area information.
2. JA is measured with the component mounted on an evaluation PC board in free air.
3. The non-inverting input of unused amplifiers must be connected to GND.
4. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle)
output current should not exceed 15mA for maximum reliability.
Electrical Specifications
VSUPPLY = 5V, RF = 1k AV = +1, RL = 400 CL 10pF,Unless Otherwise Specified
(NOTE 11)
TEST
LEVEL
TEMP.
(°C)
MIN
TYP
MAX
UNITS
A
25
-
0.8
3
mV
A
Full
-
-
5
mV
Delta VIO Between Channels
A
Full
-
1.2
3.5
mV
Average Input Offset Voltage Drift
B
Full
-
5
-
V/°C
A
25
53
-
-
dB
A
Full
50
-
-
dB
A
25
60
-
-
dB
A
Full
55
-
-
dB
A
Full
2.5
-
-
V
A
25
-
3
8
A
A
Full
-
-
20
A
A
25
-
-
0.15
A/V
A
Full
-
-
0.5
A/V
A
25
-
-
0.1
A/V
A
Full
-
-
0.3
A/V
A
25,85
-
4
12
A
A
-40
-
10
30
A
A
25,85
-
6
15
A
A
-40
-
10
30
A
A
25
-
-
0.4
A/V
A
Full
-
-
1.0
A/V
PARAMETER
TEST CONDITIONS
INPUT CHARACTERISTICS
Input Offset Voltage (VIO)
VIO Common Mode Rejection Ratio
VIO Power Supply Rejection Ratio
Input Common Mode Range
Note 5
3.5V  VS  6.5V
Note 5
Non-Inverting Input (+IN) Current
+IN Common Mode Rejection
1 )
(+IBCMR =--------R IN
Note 5
+IN Power Supply Rejection
3.5V  VS  6.5V
Inverting Input (-IN) Current
Delta -IN BIAS Current Between Channels
-IN Common Mode Rejection
Note 5
2
3550.6
February 8, 2006
HA5024
Electrical Specifications
VSUPPLY = 5V, RF = 1k AV = +1, RL = 400 CL 10pF,Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
3.5V  VS  6.5V
-IN Power Supply Rejection
(NOTE 11)
TEST
LEVEL
TEMP.
(°C)
MIN
TYP
MAX
UNITS
A
25
-
-
0.2
A/V
A
Full
-
-
0.5
A/V
Input Noise Voltage
f = 1kHz
B
25
-
4.5
-
nV/Hz
+Input Noise Current
f = 1kHz
B
25
-
2.5
-
pA/Hz
-Input Noise Current
f = 1kHz
B
25
-
25.0
-
pA/Hz
Note 16
A
25
1.0
-
-
M
A
Full
0.85
-
-
M
25A
25
70
-
-
dB
A
Full
65
-
-
dB
A
25
50
-
-
dB
A
Full
45
-
-
dB
A
25
2.5
3.0
-
V
A
Full
2.5
3.0
-
V
TRANSFER CHARACTERISTICS
Transimpedence
Open Loop DC Voltage Gain
RL = 400, VOUT =2.5V
RL = 100, VOUT = 2.5V
Open Loop DC Voltage Gain
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 150
Output Current
RL = 150
B
Full
16.6
20.0
-
mA
Output Current, Short Circuit
VIN = 2.5V, VOUT = 0V
A
Full
40
60
-
mA
Output Current, Disabled (Note 5)
DISABLE = 0V,
VOUT = 2.5V, VIN = 0V
A
Full
-
-
2
A
Output Disable Time
Note 12
B
25
-
40
-
s
Output Enable Time
Note 13
B
25
-
40
-
ns
Output Capacitance Disabled
Note 14
B
25
-
15
-
pF
Supply Voltage Range
A
25
5
-
15
V
Quiescent Supply Current
A
Full
-
7.5
10
mA/Op Amp
POWER SUPPLY CHARACTERISTICS
Supply Current, Disabled
DISABLE = 0V
A
Full
-
5
7.5
mA/Op Amp
Disable Pin Input Current
DISABLE = 0V
A
Full
-
1.0
1.5
mA
Minimum Pin 8 Current to Disable
Note 6
A
Full
350
-
-
A
Maximum Pin 8 Current to Enable
Note 7
A
Full
-
-
20
A
Slew Rate
Note 8
B
25
275
350
-
V/s
Full Power Bandwidth
Note 9
B
25
22
28
-
MHz
Rise Time
Note 10
B
25
-
6
-
ns
Fall Time
Note 10
B
25
-
6
-
ns
Propagation Delay
Note 10
B
25
-
6
-
ns
B
25
-
4.5
-
%
AC CHARACTERISTICS (AV = +1)
Overshoot
-3dB Bandwidth
VOUT = 100mV
B
25
-
125
-
MHz
Settling Time to 1%
2V Output Step
B
25
-
50
-
ns
Settling Time to 0.25%
2V Output Step
B
25
-
75
-
ns
3
3550.6
February 8, 2006
HA5024
Electrical Specifications
VSUPPLY = 5V, RF = 1k AV = +1, RL = 400 CL 10pF,Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
(NOTE 11)
TEST
LEVEL
TEMP.
(°C)
MIN
TYP
MAX
UNITS
AC CHARACTERISTICS (AV = +2, RF = 681)
Slew Rate
Note 8
B
25
-
475
-
V/s
Full Power Bandwidth
Note 9
B
25
-
26
-
MHz
Rise Time
Note 10
B
25
-
6
-
ns
Fall Time
Note 10
B
25
-
6
-
ns
Propagation Delay
Note 10
B
25
-
6
-
ns
B
25
-
12
-
%
Overshoot
-3dB Bandwidth
VOUT = 100mV
B
25
-
95
-
MHz
Settling Time to 1%
2V Output Step
B
25
-
50
-
ns
Settling Time to 0.25%
2V Output Step
B
25
-
100
-
ns
Gain Flatness
5MHz
B
25
-
0.02
-
dB
20MHz
B
25
-
0.07
-
dB
AC CHARACTERISTICS (AV = +10, RF = 383)
Slew Rate
Note 8
B
25
350
475
-
V/s
Full Power Bandwidth
Note 9
B
25
28
38
-
MHz
Rise Time
Note 10
B
25
-
8
-
ns
Fall Time
Note 10
B
25
-
9
-
ns
Propagation Delay
Note 10
B
25
-
9
-
ns
B
25
-
1.8
-
%
Overshoot
-3dB Bandwidth
VOUT = 100mV
B
25
-
65
-
MHz
Settling Time to 1%
2V Output Step
B
25
-
75
-
ns
Settling Time to 0.1%
2V Output Step
B
25
-
130
-
ns
Differential Gain (Note 15)
RL = 150
B
25
-
0.03
-
%
Differential Phase (Note 15)
RL = 150
B
25
-
0.03
-
Degrees
VIDEO CHARACTERISTICS
NOTES:
5. VCM = 2.5V. At -40°C Product is tested at VCM = 2.25V because short test duration does not allow self heating.
6. RL = 100, VIN = 2.5V. This is the minimum current which must be pulled out of the Disable pin in order to disable the output. The output is
considered disabled when -10mV  VOUT  +10mV.
7. VIN = 0V. This is the maximum current that can be pulled out of the Disable pin with the HA5024 remaining enabled. The HA5024 is
considered disabled when the supply current has decreased by at least 0.5mA.
8. VOUT switches from -2V to +2V, or from +2V to -2V. Specification is from the 25% to 75% points.
Slew Rate
9. FPBW = ----------------------------; V
= 2V .
2V PEAK PEAK
10. RL = 100, VOUT = 1V. Measured from 10% to 90% points for rise/fall times; from 50% points of input and output for propagation delay.
11. A. Production Tested; B. Typical or Guaranteed Limit based on characterization; C. Design Typical for information only.
12. VIN = +2V, DISABLE = +5V to 0V. Measured from the 50% point of DISABLE to VOUT = 0V.
13. VIN = +2V, DISABLE = 0V to +5V. Measured from the 50% point of DISABLE to VOUT = 2V.
14. VIN = 0V, Force VOUT from 0V to 2.5V, tR = tF = 50ns, DISABLE = 0V.
15. Measured with a VM700A video tester using an NTC-7 composite VITS.
16. VOUT = 2.5V. At -40°C Product is tested at VOUT = 2.25V because short test duration does not allow self heating.
4
3550.6
February 8, 2006
HA5024
Test Circuits and Waveforms
+
-
DUT
50
HP4195
NETWORK
ANALYZER
50
FIGURE 1. TEST CIRCUIT FOR TRANSIMPEDANCE MEASUREMENTS
(NOTE 17)
100
(NOTE 17)
100
VIN
+
VIN
DUT
VOUT
-
50
RL
100
+
DUT
VOUT
-
50
RI
681
RF, 681
RL
400
RF, 1k
FIGURE 2. SMALL SIGNAL PULSE RESPONSE CIRCUIT
FIGURE 3. LARGE SIGNAL PULSE RESPONSE CIRCUIT
NOTE:
17. A series input resistor of 100 is recommended to limit input currents in case input signals are present before the HA5024 is powered up.
Vertical Scale: VIN = 100mV/Div., VOUT = 100mV/Div.
Horizontal Scale: 20ns/Div.
FIGURE 4. SMALL SIGNAL RESPONSE
5
Vertical Scale: VIN = 1V/Div., VOUT = 1V/Div.
Horizontal Scale: 50ns/Div.
FIGURE 5. LARGE SIGNAL RESPONSE
3550.6
February 8, 2006
Schematic
(One Amplifier of Four)
V+
R2
800
R5
2.5K
R6
15K
R10
820
D2
QP8
R15
400
QP9
R19
400
QP14
QP11
QP1
QP5
R11
1K
R17
280
QN5
R24
140
6
QP10
R7
15K
QN1
QP6
QN6
R12
280
QP4
R28
20
QP17
QN13
+IN
QN17
QP13
R25
20
C2
1.4pF
QN15
QN2
R21
140
QN10
R14
280
QP7
QN4
R16
400
QN21
R25
140
QN16
QN14
R13
1K
QN7
R22
280
HA5024
DIS
QN3
QP20
-IN
R3
6K
D1
QP16
QP12
QP3
R1
60K
R31
5
C1
1.4pF
QN8
QP2
QP19
R20
140
QP15
QN12
R8
1.25K
QP18
R18
280
R29
9.5
R33
2K
R27
200
QN18
R23
400
R26
200
R32
5
QN19
QN20
R26
200
R30
7
OUT
R4
800
V-
R33
800
R9
820
QN9
QN11
3550.6
February 8, 2006
HA5024
as short as possible to minimize the capacitance from this
node to ground.
Application Information
Optimum Feedback Resistor
The plots of inverting and non-inverting frequency response,
see Figure 11 and Figure 12 in the Typical Performance
Curves section, illustrate the performance of the HA5024 in
various closed loop gain configurations. Although the
bandwidth dependency on closed loop gain isn’t as severe
as that of a voltage feedback amplifier, there can be an
appreciable decrease in bandwidth at higher gains. This
decrease may be minimized by taking advantage of the
current feedback amplifier’s unique relationship between
bandwidth and RF. All current feedback amplifiers require a
feedback resistor, even for unity gain applications, and RF,
in conjunction with the internal compensation capacitor, sets
the dominant pole of the frequency response. Thus, the
amplifier’s bandwidth is inversely proportional to RF. The
HA5024 design is optimized for a 1000 RF at a gain of +1.
Decreasing RF in a unity gain application decreases stability,
resulting in excessive peaking and overshoot. At higher
gains the amplifier is more stable, so RF can be decreased
in a trade-off of stability for bandwidth.
The table below lists recommended RF values for various
gains, and the expected bandwidth.
GAIN (ACL)
RF ()
BANDWIDTH (MHz)
-1
750
100
+1
1000
125
+2
681
95
+5
1000
52
+10
383
65
-10
750
22
Driving Capacitive Loads
Capacitive loads will degrade the amplifier’s phase margin
resulting in frequency response peaking and possible
oscillations. In most cases the oscillation can be avoided by
placing an isolation resistor (R) in series with the output as
shown in Figure 6.
100
VIN
R
+
VOUT
-
RT
CL
RF
RI
FIGURE 6. PLACEMENT OF THE OUTPUT ISOLATION
RESISTOR, R
The selection criteria for the isolation resister is highly
dependent on the load, but 27 has been determined to be
a good starting value.
Power Dissipation Considerations
Due to the high supply current inherent in quad amplifiers, care
must be taken to insure that the maximum junction temperature
(TJ, see Absolute Maximum Ratings) is not exceeded. Figure 7
shows the maximum ambient temperature versus supply
voltage for the available package styles (Plastic DIP, SOIC). At
5VDC quiescent operation both package styles may be
operated over the full industrial range of -40°C to 85°C. It is
recommended that thermal calculations, which take into
account output power, be performed by the designer.
PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The use
of low inductance components such as chip resistors and
chip capacitors is strongly recommended. If leaded
components are used the leads must be kept short
especially for the power supply decoupling components and
those components connected to the inverting input.
Attention must be given to decoupling the power supplies. A
large value (10F) tantalum or electrolytic capacitor in
parallel with a small value (0.1F) chip capacitor works well
in most cases.
A ground plane is strongly recommended to control noise.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input (-IN). The
larger this capacitance, the worse the gain peaking, resulting
in pulse overshoot and possible instability. It is
recommended that the ground plane be removed under
traces connected to -IN, and that connections to -IN be kept
7
MAX. AMBIENT TEMPERATURE
130
120
110
PDIP
100
90
80
70
SOIC
60
50
5
7
9
11
13
15
SUPPLY VOLTAGE (V)
FIGURE 7. MAXIMUM OPERATING AMBIENT
TEMPERATURE vs SUPPLY VOLTAGE
Enable/Disable Function
When enabled the amplifier functions as a normal current
feedback amplifier with all of the data in the electrical
specifications table being valid and applicable. When
disabled the amplifier output assumes a true high
3550.6
February 8, 2006
HA5024
impedance state and the supply current is reduced
significantly.
The circuit shown in Figure 8 is a simplified schematic of the
enable/disable function. The large value resistors in series with
the DISABLE pin makes it appear as a current source to the
driver. When the driver pulls this pin low current flows out of the
pin and into the driver. This current, which may be as large as
350A when external circuit and process variables are at their
extremes, is required to insure that point “A” achieves the
proper potential to disable the output.The driver must have the
compliance and capability of sinking all of this current.
When VCC is +5V the DISABLE pin may be driven with a
dedicated TTL gate. The maximum low level output voltage
of the TTL gate, 0.4V, has enough compliance to insure that
the amplifier will always be disabled even though D1 will not
turn on, and the TTL gate will sink enough current to keep
point “A” at its proper voltage. When VCC is greater than +5V
the DISABLE pin should be driven with an open collector
device that has a breakdown rating greater than VCC .
and 0.03 degrees respectively, determine the circuit’s
performance. The other three circuits, U1B through U1D,
operate in a similar manner.
When the plus supply rail is 5V the disable pin can be driven by
a dedicated TTL gate as discussed earlier. If a multiplexer IC or
its equivalent is used to select channels its logic must be break
before make. When these conditions are satisfied the
HA5024IP is often used as a remote video multiplexer, and the
multiplexer may be extended by adding more amplifier ICs.
Low Impedance Multiplexer
Two common problems surface when you try to multiplex
multiple high speed signals into a low impedance source such
as an A/D converter. The first problem is the low source
impedance which tends to make amplifiers oscillate and
causes gain errors. The second problem is the multiplexer
which supplies no gain, introduces all kinds of distortion and
limits the frequency response. Using op amps which have an
enable/disable function, such as the HA5024, eliminates the
multiplexer problems because the external mux chip is not
Referring to Figure 8, it can be seen that R6 will act as a pull-up
resistor to +VCC if the DISABLE pin is left open. In those cases
where the enable/disable function is not required on all circuits
some circuits can be permanently enabled by letting the
DISABLE pin float. If a driver is used to set the enable/disable
level, be sure that the driver does not sink more than 20A
when the DISABLE pin is at a high level. TTL gates, especially
CMOS versions, do not violate this criteria so it is permissible to
control the enable/disable function with TTL.
+VCC
R6
15K
R10
R33
QP18
D1
R8
R7
15K
A
QP3
ENABLE/DISABLE INPUT
FIGURE 8. SIMPLIFIED SCHEMATIC OF ENABLE/DISABLE
FUNCTION
Typical Applications
Four Channel Video Multiplexer
Referring to the amplifier U1A in Figure 9, R1 terminates the
cable in its characteristic impedance of 75, and R4 back
terminates the cable in its characteristic impedance. The
amplifier is set up in a gain configuration of +2 to yield an
overall network gain of +1 when driving a double terminated
cable. The value of R3 can be changed if a different network
gain is desired. R5 holds the disable pin at ground thus
inhibiting the amplifier until the switch, S1, is thrown to
position 1. At position 1 the switch pulls the disable pin up to
the plus supply rail thereby enabling the amplifier. Since all
of the actual signal switching takes place within the amplifier,
its differential gain and phase parameters, which are 0.03%
8
3550.6
February 8, 2006
HA5024
needed, and the HA5024 can drive low impedance (large
capacitance) loads if a series isolation resistor is used.
VIDEO
INPUT
#1
R1
75
(NOTE 17)
100
3
+
2 U1A
8
+
9 -
U1B
R6
75
R5
2000
10
R11
75
U1C
R10
2000
+5V
The circuit shown in Figure 10 was tested for the full range of
capacitor values with no oscillations being observed; thus,
problem one has been solved.The frequency and gain
characteristics of the circuit are now those of the amplifier
independent of any multiplexing action; thus, problem two
has been solved. The multiplexer transition time is
approximately 15s with the component values shown.
S1
ALL
OFF
R14
75
-
14
R15
2000
R12
681
R13
681
2
3
4
7
-5V
(NOTE 17)
15
100 13
11
12 +
VIDEO
INPUT
#3
1 R21
100
R9
75
R7
681
R8
681
VIDEO OUTPUT
TO 75 LOAD
4
R2
681
R3
681
(NOTE 17) 100
R4
75
1
gain of U2 will present the load with a small closed loop
output impedance while keeping the amplifier stable for all
values of load capacitance.
+5V
(NOTE 17)
100 18
VIDEO
INPUT
#4
19
U1D
R16
75
R18
681
6
+
-
R19
75
20
17
R17
681
R20
2000
+5V -5V IN
+5V IN
0.1F
10F
0.1F
-5V
10F
NOTES:
18. U1 is HA5024IP.
19. All resistors in 
20. S1 is break before make.
21. Use ground plane.
FIGURE 9. FOUR CHANNEL VIDEO MULTIPLEXER
Referring to Figure 10, both inputs are terminated in their
characteristic impedance; 75 is typical for video
applications. Since the drivers usually are terminated in their
characteristic impedance the input gain is 0.5, thus the
amplifiers, U2, are configured in a gain of +2 to set the circuit
gain equal to one. Resistors R2 and R3 determine the amplifier
gain, and if a different gain is desired R2 should be changed
according to the equation G = (1 + R3/R2). R3 sets the
frequency response of the amplifier so you should refer to the
manufacturers data sheet before changing its value. R5, C1
and D1 are an asymmetrical charge/discharge time circuit
which configures U1 as a break before make switch to prevent
both amplifiers from being active simultaneously. If this design
is extended to more channels the drive logic must be designed
to be break before make. R4 is enclosed in the feedback
loop of the amplifier so that the large open loop amplifier
9
3550.6
February 8, 2006
HA5024
R3A
681
INPUT B
R1A
681
R1A
75
R4A
U2A
27
16
1 +
4
-5V
2
100
3
(NOTE 17)
0.01F
INPUT A
D1A
1N4148
R1B
75
R5A
2000
U1C
R3B
681
C1A
0.047F
R2B
681
CHANNEL
SWITCH
U1A
INHIBIT
U1B
R5B
2000
U1D
100
(NOTE 17)
R4B
27
OUTPUT
+5V
0.01F
NOTES:
C1B
0.047F
D1B
1N4148
R6
100K
7 U2B
- 10
6 + 13
5
22. U2: HA5022/24.
23. U1: CD4011.
FIGURE 10. LOW IMPEDANCE MULTIPLEXER
Typical Performance Curves
VSUPPLY = 5V, AV = +1, RF = 1k RL = 400 TA = 25°C,
Unless Otherwise Specified
5
5
VOUT = 0.2VP-P
CL = 10pF
AV = +1, RF = 1k
3
AV = 2, RF = 681
2
AV = 5, RF = 1k
3
1
0
-1
-2
-3
VOUT = 0.2VP-P
CL = 10pF
RF = 750
4
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
4
AV = -1
2
1
AV = -2
0
-1
-2
AV = -10
-3
AV = 10, RF = 383
-4
AV = -5
-4
-5
2
10
FREQUENCY (MHz)
100
FIGURE 11. NON-INVERTING FREQUENCY RESPONSE
10
200
-5
2
10
FREQUENCY (MHz)
100
200
FIGURE 12. INVERTING FREQUENCY RESPONSE
3550.6
February 8, 2006
HA5024
-90
90
AV = -1, RF = 750
-135
45
AV = +10, RF = 383
-100
0
-225
-45
-270
-90
AV = -10, RF = 750
-315
-135
VOUT = 0.2VP-P
CL = 10pF
-360
2
-180
10
100
VOUT = 0.2VP-P
CL = 10pF
AV = +1
130
120
-3dB BANDWIDTH
5
GAIN PEAKING
200
500
700
FREQUENCY (MHz)
-3dB BANDWIDTH
10
5
GAIN PEAKING
350
500
650
800
0
1100
950
130
-3dB BANDWIDTH (MHz)
95
GAIN PEAKING (dB)
-3dB BANDWIDTH (MHz)
VOUT = 0.2VP-P
CL = 10pF
AV = +2
90
120
-3dB BANDWIDTH
110
6
100
GAIN PEAKING
VOUT = 0.2VP-P
90
CL = 10pF
AV = +1
80
0
200
400
600
800
4
2
0
1000
LOAD RESISTOR ()
FEEDBACK RESISTOR ()
FIGURE 15. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE
FIGURE 16. BANDWIDTH AND GAIN PEAKING vs LOAD
RESISTANCE
16
80
VOUT = 0.1VP-P
CL = 10pF
VOUT = 0.2VP-P
CL = 10pF
AV = +10
VSUPPLY = 5V, AV = +2
60
OVERSHOOT (%)
-3dB BANDWIDTH (MHz)
0
1500
900
1100
1300
FEEDBACK RESISTOR ()
FIGURE 14. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE
FIGURE 13. PHASE RESPONSE AS A FUNCTION OF
FREQUENCY
100
10
GAIN PEAKING (dB)
135
-45
140
GAIN PEAKING (dB)
AV = +1, RF = 1k
180
-3dB BANDWIDTH (MHz)
0
VSUPPLY = 5V, AV = +1, RF = 1k RL = 400 TA = 25°C,
Unless Otherwise Specified (Continued)
INVERTING PHASE (DEGREES)
NONINVERTING PHASE (DEGREES)
Typical Performance Curves
40
12
VSUPPLY = 15V, AV = +2
6
20
0
VSUPPLY = 5V, AV = +1
VSUPPLY = 15V, AV = +1
200
350
500
650
FEEDBACK RESISTOR ()
800
FIGURE 17. BANDWIDTH vs FEEDBACK RESISTANCE
11
950
0
0
200
400
600
LOAD RESISTANCE ()
800
1000
FIGURE 18. SMALL SIGNAL OVERSHOOT vs LOAD
RESISTANCE
3550.6
February 8, 2006
HA5024
Typical Performance Curves
VSUPPLY = 5V, AV = +1, RF = 1k RL = 400 TA = 25°C,
Unless Otherwise Specified (Continued)
0.08
0.10
FREQUENCY = 3.58MHz
DIFFERENTIAL GAIN (%)
0.08
DIFFERENTIAL PHASE (DEGREES)
FREQUENCY = 3.58MHz
RL = 75
0.06
RL = 150
0.04
0.02
RL = 1k
0.00
3
5
7
9
11
SUPPLY VOLTAGE (V)
0.06
0.04
RL = 150
0.02
RL = 1k
0.00
13
15
3
-40
VOUT = 2.0VP-P
CL = 30pF
13
15
-10
-60
3RD ORDER IMD
HD2
-20
REJECTION RATIO (dB)
HD2
DISTORTION (dBc)
7
9
11
SUPPLY VOLTAGE (V)
AV = +1
0
-50
HD3
-30
-40
CMRR
-50
-60
NEGATIVE PSRR
-70
-80
-80
HD3
-90
0.3
1
FREQUENCY (MHz)
10
POSITIVE PSRR
0.001
0.01
0.1
FREQUENCY (MHz)
1
10
30
FIGURE 22. REJECTION RATIOS vs FREQUENCY
FIGURE 21. DISTORTION vs FREQUENCY
12
8.0
RL = 100
VOUT = 1.0VP-P
AV = +1
RLOAD = 100
VOUT = 1.0VP-P
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
5
FIGURE 20. DIFFERENTIAL PHASE vs SUPPLY VOLTAGE
FIGURE 19. DIFFERENTIAL GAIN vs SUPPLY VOLTAGE
-70
RL = 75
7.5
7.0
6.5
10
AV = +10, RF = 383
8
AV = +2, RF = 681
6
AV = +1, RF = 1k
4
6.0
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
FIGURE 23. PROPAGATION DELAY vs TEMPERATURE
12
3
5
7
9
11
SUPPLY VOLTAGE (V)
13
15
FIGURE 24. PROPAGATION DELAY vs SUPPLY VOLTAGE
3550.6
February 8, 2006
HA5024
Typical Performance Curves
VSUPPLY = 5V, AV = +1, RF = 1k RL = 400 TA = 25°C,
Unless Otherwise Specified (Continued)
500
0.8
VOUT = 2VP-P
NORMALIZED GAIN (dB)
SLEW RATE (V/s)
0.4
+ SLEW RATE
400
VOUT = 0.2VP-P
CL = 10pF
0.6
450
350
- SLEW RATE
300
250
200
0.2
0
AV= +2, RF = 681
-0.2
-0.4
AV= +5, RF = 1k
-0.6
AV = +1, RF = 1k
-0.8
150
-1.0
100
-25
0
25
50
75
TEMPERATURE (°C)
100
125
5
0.8
VOLTAGE NOISE (nV/Hz)
NORMALIZED GAIN (dB)
AV = -1
0
-0.2
-0.4
-0.6
AV = -5
-0.8
1000
-INPUT NOISE CURRENT
80
600
60
+INPUT NOISE CURRENT
400
40
INPUT NOISE VOLTAGE
200
20
0
0.01
-1.2
10
15
20
25
30
0.1
1
0
100
10
FREQUENCY (kHz)
FREQUENCY (MHz)
FIGURE 28. INPUT NOISE CHARACTERISTICS
FIGURE 27. INVERTING GAIN FLATNESS vs FREQUENCY
1.5
BIAS CURRENT (A)
2
VIO (mV)
1.0
0.5
0.0
-60
800
AV = -2
AV = -10
5
30
AV = +10, RF = 383
0.2
-1.0
25
100
VOUT = 0.2VP-P
CL = 10pF
RF = 750
0.4
15
20
FREQUENCY (MHz)
FIGURE 26. NON-INVERTING GAIN FLATNESS vs FREQUENCY
FIGURE 25. SLEW RATE vs TEMPERATURE
0.6
10
CURRENT NOISE (pA/Hz)
-50
AV = +10, RF = 383
-1.2
0
-2
-4
-40
-20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
FIGURE 29. INPUT OFFSET VOLTAGE vs TEMPERATURE
13
-60
-40
-20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
FIGURE 30. +INPUT BIAS CURRENT vs TEMPERATURE
3550.6
February 8, 2006
HA5024
Typical Performance Curves
VSUPPLY = 5V, AV = +1, RF = 1k RL = 400 TA = 25°C,
Unless Otherwise Specified (Continued)
4000
TRANSIMPEDANCE (k)
BIAS CURRENT (A)
22
20
18
16
-60
-40
-20
0
20
40
60
80
100
120
3000
2000
1000
-60
140
-40
-20
0
TEMPERATURE (°C)
72
REJECTION RATIO (dB)
55°C
20
ICC (mA)
125°C
15
10
80
100
120
140
3
4
5
6
+PSRR
70
68
-PSRR
66
64
62
60
25°C
7
8
9
10
11
12
13
14
CMRR
58
-100
15
-50
0
50
100
200
150
250
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
FIGURE 34. REJECTION RATIO vs TEMPERATURE
FIGURE 33. SUPPLY CURRENT vs SUPPLY VOLTAGE
4.0
40
30
+10V
+5V
+15V
OUTPUT SWING (V)
SUPPLY CURRENT (mA)
60
74
25
20
10
0
40
FIGURE 32. TRANSIMPEDANCE vs TEMPERATURE
FIGURE 31. -INPUT BIAS CURRENT vs TEMPERATURE
5
20
TEMPERATURE (°C)
3.8
3.6
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
DISABLE INPUT VOLTAGE (V)
FIGURE 35. SUPPLY CURRENT vs DISABLE INPUT VOLTAGE
14
-60
-40
-20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
FIGURE 36. OUTPUT SWING vs TEMPERATURE
3550.6
February 8, 2006
HA5024
Typical Performance Curves
VSUPPLY = 5V, AV = +1, RF = 1k RL = 400 TA = 25°C,
Unless Otherwise Specified (Continued)
30
1.2
VS = 15V
VIO (mV)
VS = 10V
1.0
10
0.9
VS = 4.5V
0
0.01
0.8
0.10
1.00
10.00
-60
-40
-20
0
LOAD RESISTANCE (k)
FIGURE 37. OUTPUT SWING vs LOAD RESISTANCE
40
60
80
120
140
30
25
-55°C
ICC (mA)
1.0
0.5
25°C
20
15
10
0.0
-60
125°C
5
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
FIGURE 39. INPUT BIAS CURRENT CHANGE BETWEEN
CHANNELS vs TEMPERATURE
3
4
5
6
7
8
9 10 11
SUPPLY VOLTAGE (V)
13
ENABLE
ENABLE TIME (ns)
28
-50
-60
16
14
26
ENABLE
24
12
22
10
20
8
18
6
DISABLE
4
16
-70
14
10
FIGURE 41. CHANNEL SEPARATION vs FREQUENCY
15
15
18
30
-40
1
FREQUENCY (MHz)
14
20
32
AV = +1
VOUT = 2VP-P
-80
0.1
12
FIGURE 40. DISABLE SUPPLY CURRENT vs SUPPLY
VOLTAGE
-30
SEPARATION (dB)
100
FIGURE 38. INPUT OFFSET VOLTAGE CHANGE BETWEEN
CHANNELS vs TEMPERATURE
1.5
BIAS CURRENT (A)
20
TEMPERATURE (°C)
30
DISABLE TIME (s)
VOUT (VP-P)
1.1
20
2
DISABLE
12
-2.5 -2.0 -1.5 -1.0
-0.5
0
0.5
1.0
1.5
2.0
0
2.5
OUTPUT VOLTAGE (V)
FIGURE 42. ENABLE/DISABLE TIME vs OUTPUT VOLTAGE
3550.6
February 8, 2006
HA5024
Typical Performance Curves
-20
-30
-40
-50
10
RL = 100
1
0.1
0.01
180
0.001
135
90
45
-60
0
-70
-45
-80
-90
0.1
1
FREQUENCY (MHz)
10
0.001
20
0.1
1
FREQUENCY (MHz)
10
-135
100
FIGURE 44. TRANSIMPEDANCE vs FREQUENCY
FIGURE 43. DISABLE FEEDTHROUGH vs FREQUENCY
TRANSIMPEDANCE (M)
0.01
PHASE ANGLE (DEGREES)
DISABLE = 0V
VIN = 5VP-P
RF = 750
10
RL = 400
1
0.1
0.01
180
0.001
135
90
45
0
-45
-90
0.001
0.01
0.1
1
10
100
-135
PHASE ANGLE (DEGREES)
FEEDTHROUGH (dB)
-10
TRANSIMPEDANCE (M)
0
VSUPPLY = 5V, AV = +1, RF = 1k RL = 400 TA = 25°C,
Unless Otherwise Specified (Continued)
FREQUENCY (MHz)
FIGURE 45. TRANSIMPEDENCE vs FREQUENCY
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
3550.6
February 8, 2006
HA5024
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
2680m x 2600m x 483m
Type: Nitride
Thickness: 4kÅ 0.4kÅ
METALLIZATION:
TRANSISTOR COUNT:
Type: Metal 1: AlCu (1%)
Thickness: Metal 1: 8kÅ 0.4kÅ
248
Type: Metal 2: AlCu (1%)
Thickness: Metal 2: 16kÅ 0.8kÅ
PROCESS:
High Frequency Bipolar Dielectric Isolation
SUBSTRATE POTENTIAL (Powered Up):
V-
Metallization Mask Layout
HA5024
-IN1
OUT1
OUT4
-IN4
2
1
20
19
1
1
1
1
1
9
10
11
12
-IN2
OUT2
OUT3
-IN3
17
3550.6
February 8, 2006
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