DATASHEET

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1-888-
200MHz, Video Op Amp with High Speed
Sync Stripper
The HFA1103 is a high-speed, wideband, fast settling
current feedback op amp with a sync stripping function. The
HFA1103 is a basic op amp with a modified output stage that
enables it to strip the sync from a component video signal.
The output stage has an open emitter NPN transistor that
prevents the output from going low during the sync pulse.
Removing the sync signal benefits digitizing systems
because only the active video information is applied to the
A/D converter. This enables the full dynamic range of the
A/D converter to be used to process the video signal. The
HFA1103 includes inverting input bias current adjust pins
(pins 1 and 5) for adjusting the output offset voltage.
HFA1103IB
(H1103I)
June 2004
FN3957.4
Features
• Removes Sync Signal From Component Video
• Low Residual Sync. . . . . . . . . . . . . . . . . . . . . . 8mV (Typ)
• -3dB Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 200MHz
• Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . . . 600V/µs
• Fast Settling Time (0.1%). . . . . . . . . . . . . . . . . . . . . . 9ns
• Excellent Gain Flatness, 32MHz . . . . . . . . . . . . . . ±0.1dB
• Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . . . <12ns
Applications
• RGB Video Sync Stripping
• RGB Video Distribution Amplifier for Workstations and PC
Networks
Part # Information
PART NUMBER
(BRAND)
HFA1103
TEMP.
RANGE (oC)
-40 to 85
PKG.
NO.
PACKAGE
8 Ld SOIC
M8.15
• Video Conferencing Systems
• RGB Video Monitor Preamp
• Fiberoptic Receivers
Sync Stripper Waveforms
Pinout
HFA1103
(SOIC)
TOP VIEW
0 TO
+0.7V
0 TO
+0.7V
0 TO
-0.3V
COMPONENT (RGB)
VIDEO INPUT
HFA1103 OUTPUT
BAL
1
-IN
2
+IN
3
V-
4
+
V+
8
NC
7
V+
6
OUT
5
BAL
Application Schematic
+5V
4.7K
RB
2K
HFA1103
VIN
+
VOUT
-
RIN
75
RG
750
RT
75
RF
750
RL
75
1
RT
75
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
HFA1103
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V
Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . 60mA
Thermal Resistance (Typical, Note 1)
Operating Conditions
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
170
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(Lead Tips Only)
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
VSUPPLY = ±5V, AV = +2, RF = 750Ω, RL = 50Ω, Unless Otherwise Specified
Electrical Specifications
PARAMETER
TEST CONDITIONS
TEMP
(oC)
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
VIN = -300mV, AV = +1
Residual Sync (Note 2)
Output Offset Voltage (Notes 3, 5)
Output Offset Voltage Drift (Note 3)
VOS PSRR
∆VS = ±1.25V
Non-Inverting Input Bias Current
+IN = 0V
Inverting Input Bias Current
-IN = 0V
25
-
8
10
mV
Full
-
-
12
mV
25
-
10
30
mV
Full
-
-
40
mV
Full
-
10
-
µV/oC
25
39
45
-
dB
Full
35
-
-
dB
25
-
5
40
µA
Full
-
-
65
µA
25
-
5
50
µA
Full
-
-
60
µA
-IBIAS Adjust Range (Notes 4, 6)
25
100
200
-
µA
Non-Inverting Input Resistance
25
25
50
-
kΩ
Inverting Input Resistance
25
-
16
30
Ω
Input Capacitance
25
-
2
-
pF
Input Common Mode Range
Full
±2.5
±3.0
-
V
Input Noise Voltage
100kHz
25
-
4
-
nV/√Hz
+Input Noise Current
100kHz
25
-
18
-
pA/√Hz
-Input Noise Current
100kHz
25
-
21
-
pA/√Hz
25
-
500
-
kΩ
25
-
200
-
MHz
TRANSFER CHARACTERISTICS AV = +2, Unless Otherwise Specified
Open Loop Transimpedance
-3dB Bandwidth
VOUT = 1.0VP-P, AV = +2
Gain Flatness
To ±0.1dB
Minimum Stable Gain
25
-
32
-
MHz
Full
1
-
-
V/V
25, 85
2.5
3.0
-
V
-40oC
1.75
2.5
-
V
25, 85
50
60
-
mA
-40oC
35
50
-
mA
25
-
0.01
-
%
25
-
2
-
ns
OUTPUT CHARACTERISTICS AV = +2, Unless Otherwise Specified
Output Voltage (Note 3)
Output Current
Linearity Near Zero
TRANSIENT RESPONSE
AV = +2, Unless Otherwise Specified
VOUT = 2.0V Step
Rise Time
2
HFA1103
VSUPPLY = ±5V, AV = +2, RF = 750Ω, RL = 50Ω, Unless Otherwise Specified (Continued)
Electrical Specifications
TEMP
(oC)
MIN
TYP
MAX
UNITS
VOUT = 2.0V Step
25
-
10
-
%
Slew Rate
AV = +2, VOUT = 0 to 2V, +2V to 0V
25
-
600
-
V/µs
0.1% Settling
VOUT = 2V to 0V
25
-
9
-
ns
Overdrive Recovery Time
2X Overdrive
25
-
12
-
ns
Supply Voltage Range
Full
±4.5
-
±5.5
V
Supply Current (No Load)
25
-
11
16
mA
Full
-
-
23
mA
PARAMETER
TEST CONDITIONS
Overshoot
POWER SUPPLY CHARACTERISTICS
NOTES:
2. The residual sync is specified at the output of a doubly terminated circuit (see page 1 of this data sheet).
3. Since the HFA1103 has an open emitter NPN output stage, this measurement is only valid for positive values.
4. The -IBIAS current can be used to adjust the offset voltage to zero, but -IBIAS does not flow bidirectionally because the HFA1103 output stage
is an open emitter NPN transistor.
5. VOS includes the error contribution of IBSN at RF = 750Ω.
6. This is the minimum change in inverting input bias current when a BAL pin is connected to V- through a 50Ω resistor.
Test Circuit
may cause oscillations. In most cases, the oscillation can be
avoided by placing a resistor in series with the output.
DUT
VIN
+
VOUT
-
RIN
50Ω
RF
750Ω
RG
750Ω
RL
50Ω
FIGURE 1. TEST CIRCUIT
Application Information
Offset Adjustment
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input. The larger this
capacitance, the worse the gain peaking, resulting in pulse
overshoot and possible instability. To this end, it is
recommended that the ground plane be removed under
traces connected to pin 2, and connections to pin 2 should
be kept as short as possible.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
Evaluation Board
The HFA1103 allows for adjustment of the inverting input bias
current to null the output offset voltage. -IBIAS flows through
RF, so any change in bias current forces a corresponding
change in output voltage. The amount of adjustment is a
function of RF. With RF = 750Ω, the typical adjust range is
150mV. For offset adjustment connect a 10kΩ potentiometer
between pins 1 and 5 with the wiper connected to V-.
The HFA1100 series evaluation board may be used for the
HFA1103 with minor modifications. The evaluation board
may be ordered using part number HFA11XXEVAL. Please
note that an HFA1103 sample is not included with the
evaluation board and must be ordered separately.
The layout and schematic of the board are shown below:
PC Board Layout
500Ω
500Ω
The frequency performance of these amplifiers depends a
great deal on the amount of care taken in designing the PC
board. The use of low inductance components such as
chip resistors and chip capacitors is strongly
recommended, while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
chip (0.1µF) capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Output capacitance, such as
that resulting from an improperly terminated transmission
line will degrade the frequency response of the amplifier and
3
50Ω
VH
1
8
2
7
0.1µF
10µF
+5V
50Ω
IN
10µF
3
6
4
5
0.1µF
OUT
VL
GND
-5V
GND
FIGURE 2. EVALUATION BOARD SCHEMATIC
HFA1103
BOTTOM LAYOUT
TOP LAYOUT
VH
1
OUT
+IN
VL
V+
VGND
Typical Application
FIGURE 3. EVALUATION BOARD ARTWORK
A circuit which performs the sync stripper and DC restore
functions is shown in Figure 4. Please reference Intersil
Application Note AN9514, titled “Video Amplifier with Sync
Stripper and DC Restore”, for details on this circuit.
TO SYNC
SEPARATOR
+
IC1b
R6
750
-
-
C1
0.1µF
VIN
+5VDC
-5V
+
IC2
R4
1K
OPT.
R8
6.8K
R7
750
R3
10K
R2
10K
IC1a
-
IC1a + IC1b = CA5260 DUAL AMP
IC2 = 74HC4053 SWITCH
IC3 = HFA1103 VIDEO OP AMP
+5V
S/H
CONTROL
R1
1K
The standard output of a VM700 video measurement set is
shown in Figure 5. The output, after passing through the
Applications Schematic shown on the first page of this data
sheet, is shown in Figure 6.
R11
75
IC3
VOUT
+
R5
1K
R10
75
C2
47µF
R12
75
R9
10K
FIGURE 4. VIDEO AMPLIFIER WITH SYNC STRIPPER AND DC RESTORE
VOLTS
IRE:FLT
100.0
0.6
0.4
50.0
0.2
0.0
0.0
-0.2
-50.0
-40.0
-30.0
525 LINE NTSC
-20.0
-10.0
0.0
MICROSECONDS
FIGURE 5. OUTPUT OF VM700 VIDEO MEASUREMENT SET
4
10.0
HFA1103
VOLTS
IRE:FLT
100.0
0.6
0.4
50.0
0.2
0.0
0.0
-0.2
-50.0
-40.0
525 LINE NTSC
-30.0
-20.0
-10.0
0.0
10.0
MICROSECONDS
FIGURE 6. OUTPUT OF HFA1103 SYNC STRIPPER CONFIGURED AS ON THE FIRST PAGE OF THIS DATA SHEET
5
HFA1103
Die Characteristics
DIE DIMENSIONS:
SUBSTRATE POTENTIAL (POWERED UP):
63 mils x 44 mils x 19 mils
1600µm x 1130µm x 483µm
Floating (Recommend Connection to V-)
PASSIVATION:
METALLIZATION:
Type: Nitride
Thickness: 4kÅ ±0.5kÅ
Type: Metal 1: AlCu (2%)/TiW
Thickness: Metal1: 8kÅ ±0.4kÅ
Type: Metal 2: AlCu (2%)
Thickness: 16kÅ ±0.8kÅ
TRANSISTOR COUNT:
50
Metallization Mask Layout
HFA1103
BAL
NC
-IN
V+
+IN
OUT
V-
NC
BAL
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
6
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
HFA1103
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
0.25(0.010) M
H
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
µα
A1
B
0.25(0.010) M
C
C A M
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
MILLIMETERS
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
NOTES:
MAX
A1
e
0.10(0.004)
MIN
α
8
0o
8
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
7
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